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----------------------------------------------------------------------------
-- Increment_PC
-- This unit is a simple Adder, which increment the current value of PC,
-- coming from the PC register, by 4(since the addresses in memory must be
-- word-aligned). The output of this unit feed the MUX_branch unit.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity increment_pc is
port (
-- INPUTS
from_pc : in std_logic_vector(31 downto 0); -- address coming from PC register that shoudl be incremented
-- OUTPUTS
to_mux_branch : out std_logic_vector(31 downto 0) -- address to the MUX_branch unit incremented by 4
);
end increment_pc;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of increment_pc is
begin
to_mux_branch <= std_logic_vector(unsigned(from_pc) + X"0000004");
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity seven_segment is
port (
clk : in std_logic;
val : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
mode: in std_logic
);
end seven_segment;
architecture arch of seven_segment is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
signal spinner : std_logic_vector(5 downto 0) := "111110";
signal spin_spinner: std_logic;
begin
p1: pulser generic map(delay=>5000000) port map(clk,'1',spin_spinner);
spinner_pro: process(spin_spinner)
begin
if(spin_spinner'event and spin_spinner = '1')then
if(spinner = "011111")then
spinner <= "111110";
else
spinner <= spinner(4 downto 0) & '1';
end if;
end if;
end process spinner_pro;
disp_pro: process(clk,val,mode)
begin
if(mode = '0') then
case val is
when "0001" => led <= "1111001";
when "0010" => led <= "0100100";
when "0011" => led <= "0110000";
when "0100" => led <= "0011001";
when "0101" => led <= "0010010";
when "0110" => led <= "0000010";
when "0111" => led <= "1111000";
when "1000" => led <= "0000000";
when "1001" => led <= "0010000";
when "1010" => led <= "0001000";
when "1011" => led <= "0000011";
when "1100" => led <= "1000110";
when "1101" => led <= "0100001";
when "1110" => led <= "0000110";
when "1111" => led <= "0001110";
when others => led <= "1000000";
end case;
else
if( val = "0001") then
led <= "1000111";
else if ( val = "0010") then
led <= "0010010";
else if ( val = "0011") then
led <= '1'&spinner;
else
led <= "1111111";
end if;
end if;
end if;
end if;
end process disp_pro;
end arch;
|
architecture test of test2 is
constant foo : bar := baz;
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity xtc_top_ppro is
port (
CLK: in std_logic;
-- Connection to the main SPI flash
--SPI_SCK: out std_logic;
--SPI_MISO: in std_logic;
--SPI_MOSI: out std_logic;
--SPI_CS: out std_logic;
-- WING connections
--WING_A: inout std_logic_vector(15 downto 0);
--WING_B: inout std_logic_vector(15 downto 0);
--WING_C: inout std_logic_vector(15 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic
--DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
-- DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
-- DRAM_CAS_N : OUT STD_LOGIC;
-- DRAM_CKE : OUT STD_LOGIC;
-- DRAM_CLK : OUT STD_LOGIC;
-- DRAM_CS_N : OUT STD_LOGIC;
-- DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
-- DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
-- DRAM_RAS_N : OUT STD_LOGIC;
-- DRAM_WE_N : OUT STD_LOGIC;
-- The LED
--LED: out std_logic
);
end entity xtc_top_ppro;
architecture behave of xtc_top_ppro is
component uart is
generic (
bits: integer := 11
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 2);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
enabled: out std_logic;
tx: out std_logic;
rx: in std_logic
);
end component;
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clkout2x: out std_logic;
rstout: out std_logic
);
end component;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
component xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end component;
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_tag_i: std_logic_vector(31 downto 0);
signal wb_tag_o: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_int: std_logic;
signal wb_stall: std_logic;
signal wb_clk_i_2x: std_ulogic;
begin
cpu: xtc_top_bram
port map (
wb_syscon.clk => wb_clk_i,
wb_syscon.rst => wb_rst_i,
-- Master wishbone interface
iowbi.ack => wb_ack,
iowbi.dat => wb_read,
iowbi.tag => wb_tag_i,
iowbi.int => wb_int,
iowbi.stall => '0',
iowbo.dat => wb_write,
iowbo.adr => wb_address,
iowbo.cyc => wb_cyc,
iowbo.tag => wb_tag_o,
iowbo.stb => wb_stb,
iowbo.sel => wb_sel,
iowbo.we => wb_we
);
-- Simple tag generator
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_cyc='1' and wb_stb='1' and wb_ack='0' then
wb_tag_o <= wb_tag_i;
end if;
end if;
end process;
myuart: uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => wb_read,
wb_dat_i => wb_write,
wb_adr_i => wb_address(31 downto 2),
wb_we_i => wb_we,
wb_cyc_i => wb_cyc,
wb_stb_i => wb_stb,
wb_ack_o => wb_ack,
wb_inta_o => wb_int,
tx => txd,
rx => rxd
);
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
-- rstgen: zpuino_serialreset
-- generic map (
-- SYSTEM_CLOCK_MHZ => 96
-- )
-- port map (
-- clk => sysclk,
-- rx => rx,
-- rstin => clkgen_rst,
-- rstout => sysrst
-- );
sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout2x => wb_clk_i_2x,
rstout => clkgen_rst
);
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity parampow_tb is
end parampow_tb;
architecture tb of parampow_tb is
component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
rst : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal Start : std_logic := '0';
signal Done : std_logic := '0';
signal X : sfixed(11 downto -12);
signal A : sfixed(11 downto -12);
signal Output : sfixed(11 downto -12);
begin
ParamPow_uut : ParamPow
generic map(
BIT_TOP => 11,
BIT_BOTTOM => -12
)
port map ( clk => clk,
rst => rst,
Start => Start,
Done => Done,
X => X,
A => A,
Output => Output
);
process
begin
wait for 10ns;
clk <= not(clk);
wait for 10ns;
clk <= not(clk);
end process;
process (Done)
begin
if Done'event and Done = '1' then
report "The value of " & real'image(to_real(A)) & "^" & real'image(to_real(X))& " = " & real'image(to_real(Output));
end if;
end process;
process
begin
-- wait for Reset to complete
-- wait until rst='1';
rst<='1';
wait for 40 ns;
rst<='0';
wait for 40 ns;
A <= to_sfixed(2.5,11,-12);
X <= to_sfixed(1,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(2,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(3,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(4,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(5,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
end process;
end tb;
|
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0_10;
use dist_mem_gen_v8_0_10.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0_10
-- component declaration for dist_mem_gen_v8_0_10
component dist_mem_gen_v8_0_10
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0_10 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0_10 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0_10 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10";
--xcc include
end comp_defs;
|
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
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-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
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-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0_10;
use dist_mem_gen_v8_0_10.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0_10
-- component declaration for dist_mem_gen_v8_0_10
component dist_mem_gen_v8_0_10
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0_10 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0_10 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0_10 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10";
--xcc include
end comp_defs;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_dc_huffsize;
architecture augh of huff_make_dhuff_tb_dc_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_dc_huffsize;
architecture augh of huff_make_dhuff_tb_dc_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
|
use std.textio.all; -- Imports the standard textio package.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Defines a design entity, without any ports.
entity tests is
end tests;
architecture behaviour of tests is
begin
process
variable l : line;
variable a : natural := 1;
begin
report "a = " & natural'simple_name(a);
wait;
end process;
end behaviour;
|
use std.textio.all; -- Imports the standard textio package.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Defines a design entity, without any ports.
entity tests is
end tests;
architecture behaviour of tests is
begin
process
variable l : line;
variable a : natural := 1;
begin
report "a = " & natural'simple_name(a);
wait;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
|
package pkg1 is
generic (
type value_t);
end package;
package pkg2 is
generic (
type value_t);
package pkg1_inst is new work.pkg1 generic map (value_t => value_t);
use pkg1_inst.all;
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_stub.vhdl
-- Design : RAT_xlconstant_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_xlconstant_0_0 is
Port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_xlconstant_0_0;
architecture stub of RAT_xlconstant_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "dout[9:0]";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:01 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_stub.vhdl
-- Design : RAT_xlconstant_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_xlconstant_0_0 is
Port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end RAT_xlconstant_0_0;
architecture stub of RAT_xlconstant_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "dout[9:0]";
begin
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: comma_detect
-- File: comma_detect.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII' comma detector with bitslip output signal
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
entity comma_detect is
generic (
bsbreak : integer range 0 to 31 := 0; -- number of extra deassertion cycles between bitslip assertions in a sequence
bswait : integer range 0 to 127 := 7 -- number of cycles to pause recognition after a sequence is issued
);
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end entity;
architecture arch of comma_detect is
type fsm_state_type is (idle, bitslip1, bitslip2, bitslip3);
type reg_type is record
data : std_logic_vector(19 downto 0);
state : fsm_state_type;
slipcnt : integer range 0 to 15;
slipbreak : integer range 0 to 31;
slipwait : integer range 0 to 127;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := (
data => (others => '0'),
state => idle,
slipcnt => 0,
slipbreak => 0,
slipwait => 0
);
signal r, rin : reg_type;
begin
comb : process( rstn, r, indata )
variable v : reg_type;
--variable vbitslip : std_logic_vector(15 downto 0);
begin
v := r;
v.data(19 downto 10) := r.data(9 downto 0);
v.data(9 downto 0) := indata;
-- -- we match pattern comma+, present in +K.28.x
-- for i in 19 downto 10 loop
-- if r.data(i downto i-6) = "0011111" then
-- vbitslip(9-(i-10)) := '1'; -- unary representation of number of bitslips
-- exit;
-- end if;
-- end loop ;
-- v.slipcnt := unary_to_slv(vbitslip);
case r.state is
when idle =>
-- we match pattern comma+, present in +K.28.x
if r.data(18 downto 12) = "0011111" then
v.slipcnt := 9;
elsif r.data(17 downto 11) = "0011111" then
v.slipcnt := 8;
elsif r.data(16 downto 10) = "0011111" then
v.slipcnt := 7;
elsif r.data(15 downto 9) = "0011111" then
v.slipcnt := 6;
elsif r.data(14 downto 8) = "0011111" then
v.slipcnt := 5;
elsif r.data(13 downto 7) = "0011111" then
v.slipcnt := 4;
elsif r.data(12 downto 6) = "0011111" then
v.slipcnt := 3;
elsif r.data(11 downto 5) = "0011111" then
v.slipcnt := 2;
elsif r.data(10 downto 4) = "0011111" then
v.slipcnt := 1;
else
v.slipcnt := 0;
end if;
if v.slipcnt /= 0 then
v.state := bitslip1;
end if;
when bitslip1 =>
v.slipcnt := r.slipcnt - 1;
v.state := bitslip2;
v.slipbreak := 0;
when bitslip2 =>
if r.slipcnt /= 0 then
if r.slipbreak = bsbreak then
v.state := bitslip1;
else
v.slipbreak := r.slipbreak + 1;
end if;
else
v.slipwait := 0;
v.state := bitslip3;
end if;
when bitslip3 =>
if r.slipwait = bswait then
v.state := idle;
v.data := (others => '0');
else
v.slipwait := r.slipwait + 1;
end if;
when others =>
end case ;
if (not RESET_ALL) and (rstn = '0') then
v.data := (others => '0');
v.state := idle;
end if;
rin <= v;
if r.state = bitslip1 then
bitslip <= '1';
else
bitslip <= '0';
end if;
end process ;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rstn = '0' then
r <= RES;
end if;
end if;
end process;
end architecture ;
|
--
-- synthesis test 2:
-- * without clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: (same as hw1_grain)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw2_grain is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw2_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for concatenation of function call results.
library ieee;
use ieee.std_logic_1164.all;
entity concat_func is
port(in_word : in std_logic_vector(7 downto 0);
out_word : out std_logic_vector(7 downto 0));
end entity concat_func;
architecture test of concat_func is
begin
process(in_word)
begin
out_word <= in_word(7 downto 6) & to_unsigned(in_word, 3) & resize(in_word, 3);
end process;
end architecture test;
|
-- $Id: tb_nexys2_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys2_core is
port (
I_SWI : out slv8; -- n2 switches
I_BTN : out slv4; -- n2 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys2_core;
architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' THEN
b <= '0';
elsif c = '1' THEN
b <= '1';
else
if x = '1' THEN
z <= '0';
elsif x = '0' THEN
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' THEN
b <= '0';
elsif c = '1' THEN
b <= '1';
else
if x = '1' THEN
z <= '0';
elsif x = '0' THEN
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Adder for Convolutional Codes example project
-- Module Name: MyADDER - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity MyADDER is
port (INP1, INP2, INP3, INP4, INP5, INP6, INP7, INP8 : in integer;
INP9, INP10, INP11, INP12, INP13, INP14, INP15, INP16 : in integer;
ADDer_clk : in std_logic;
ADDer_count : in integer;
OUP1_1, OUP1_5, OUP5_3, OUP5_7, OUP3_2, OUP3_6, OUP7_4, OUP7_8 : out integer:=0;
OUP2_1, OUP2_5, OUP6_3, OUP6_7, OUP4_2, OUP4_6, OUP8_4, OUP8_8 : out integer :=0);
end MyADDER;
architecture Behavioral of MyADDER is
begin
process (ADDer_clk)
type matrix is array(seq downto 0) of integer;
variable sum : matrix := ((0),(0),(0),(0),(0),(0),(0),(0));
variable sum_old : matrix := ((0),(0),(0),(0),(0),(0),(0),(0));
begin
if (falling_edge(ADDer_clk)) then
if (ADDer_count> 0) then
OUP1_1 <= INP1 + sum_old(0);
if (ADDer_count <= 3) then sum(0) := sum_old(0) + INP1; end if;
OUP1_5 <= INP2 + sum_old(0);
if (ADDer_count <= 3) then sum(4) := sum_old(0) + INP2; end if;
if (ADDer_count > 1) then
OUP5_3 <= INP9 + sum_old(4);
if (ADDer_count <= 3) then sum(2) := sum_old(4) + INP9; end if;
OUP5_7 <= INP10 + sum_old(4);
if (ADDer_count <= 3) then sum(6) := sum_old(4) + INP10; end if;
if (ADDer_count > 2) then
OUP3_2 <= INP5 + sum_old(2);
if (ADDer_count <= 3) then sum(1) := sum_old(2) + INP5; end if;
OUP3_6 <= INP6 + sum_old(2);
if (ADDer_count <= 3) then sum(5) := sum_old(2) + INP6; end if;
OUP7_4 <= INP13 + sum_old(6);
if (ADDer_count <= 3) then sum(3) := sum_old(6) + INP13; end if;
OUP7_8 <= INP14 + sum_old(6);
if (ADDer_count <= 3) then sum(7) := sum_old(6) + INP14; end if;
if (ADDer_count > 3) then
OUP2_1 <= INP3 + sum_old(1);
OUP2_5 <= INP4 + sum_old(1);
OUP6_3 <= INP11 + sum_old(5);
OUP6_7 <= INP12 + sum_old(5);
OUP4_2 <= INP7 + sum_old(3);
OUP4_6 <= INP8 + sum_old(3);
OUP8_4 <= INP15 + sum_old(7);
OUP8_8 <= INP16 + sum_old(7);
end if;
end if;
end if;
if (ADDer_count > 3) then
if ((sum_old(0) + INP1)>(sum_old(1) + INP3)) then
sum(0) := sum_old(0) + INP1;
else sum(0) := sum_old(1) + INP3; end if;
if ((sum_old(0) + INP2)>(sum_old(1) + INP4)) then
sum(4) := sum_old(0) + INP2;
else sum(4) := sum_old(1) + INP4; end if;
if ((sum_old(4) + INP9)>(sum_old(5) + INP11)) then
sum(2) := sum_old(4) + INP9;
else sum(2) := sum_old(5) + INP11; end if;
if ((sum_old(4) + INP10)>(sum_old(5) + INP12)) then
sum(6) := sum_old(4) + INP10;
else sum(6) := sum_old(5) + INP12; end if;
if ((sum_old(2) + INP5)>(sum_old(3) + INP7)) then
sum(1) := sum_old(2) + INP5;
else sum(1) := sum_old(3) + INP7; end if;
if ((sum_old(2) + INP6)>(sum_old(3) + INP8)) then
sum(5) := sum_old(2) + INP6;
else sum(5) := sum_old(3) + INP8; end if;
if ((sum_old(6) + INP13)>(sum_old(7) + INP15)) then
sum(3) := sum_old(6) + INP13
else sum(3) := sum_old(7) + INP15; end if;
if ((sum_old(6) + INP14)>(sum_old(7) + INP16)) then
sum(7) := sum_old(6) + INP14
else sum(7) := sum_old(7) + INP16; end if;
end if;
sum_old:=sum;
if (ADDer_count = 0) then
sum_old := ((0),(0),(0),(0),(0),(0),(0),(0));
sum := ((0),(0),(0),(0),(0),(0),(0),(0));
end if;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end small_fifo;
architecture Behavioral of small_fifo is
type mem_array is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal fifo : mem_array ;
signal rd_ptr, wr_ptr : integer range 0 to DEPTH-1 ;
signal full_t, empty_t : std_logic ;
signal nb_available : integer range 0 to DEPTH-1 ;
begin
process(clk, resetn)
begin
if resetn = '0' then
rd_ptr <= 0 ;
wr_ptr <= 0 ;
nb_available <= 0 ;
elsif clk'event and clk = '1' then
if push = '1' and full_t = '0' then
wr_ptr <= (wr_ptr + 1) ;
fifo(wr_ptr) <= data_in ;
if pop = '0' then
nb_available <= nb_available + 1 ;
end if ;
end if ;
if pop = '1' and empty_t = '0' then
rd_ptr <= rd_ptr + 1 ;
if push = '0' then
nb_available <= nb_available - 1 ;
end if ;
end if ;
end if ;
end process ;
full_t <= '1' when nb_available = DEPTH-1 else
'0' ;
empty_t <= '1' when nb_available = 0 else
'0' ;
data_out <= fifo(rd_ptr) when empty_t = '0' else
(others => '0');
limit <= '1' when nb_available >= THRESHOLD else
'0' ;
empty <= empty_t ;
full <= full_t ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:31:55 03/22/2013
-- Design Name:
-- Module Name: smal_stack - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end small_fifo;
architecture Behavioral of small_fifo is
type mem_array is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0);
signal fifo : mem_array ;
signal rd_ptr, wr_ptr : integer range 0 to DEPTH-1 ;
signal full_t, empty_t : std_logic ;
signal nb_available : integer range 0 to DEPTH-1 ;
begin
process(clk, resetn)
begin
if resetn = '0' then
rd_ptr <= 0 ;
wr_ptr <= 0 ;
nb_available <= 0 ;
elsif clk'event and clk = '1' then
if push = '1' and full_t = '0' then
wr_ptr <= (wr_ptr + 1) ;
fifo(wr_ptr) <= data_in ;
if pop = '0' then
nb_available <= nb_available + 1 ;
end if ;
end if ;
if pop = '1' and empty_t = '0' then
rd_ptr <= rd_ptr + 1 ;
if push = '0' then
nb_available <= nb_available - 1 ;
end if ;
end if ;
end if ;
end process ;
full_t <= '1' when nb_available = DEPTH-1 else
'0' ;
empty_t <= '1' when nb_available = 0 else
'0' ;
data_out <= fifo(rd_ptr) when empty_t = '0' else
(others => '0');
limit <= '1' when nb_available >= THRESHOLD else
'0' ;
empty <= empty_t ;
full <= full_t ;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_target
-- File: pt_pci_target.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Target emulator.
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.pt_pkg.all;
--use gaisler.pcilib.all;
--use gaisler.ambatest.all;
library std;
use std.textio.all;
entity pt_pci_target is
generic (
slot : integer := 0;
abits : integer := 10;
bars : integer := 1;
resptime : integer := 2;
latency : integer := 0;
rbuf : integer := 8;
stopwd : boolean := true;
tval : time := 7 ns;
conf : config_header_type := config_init;
dbglevel : integer := 1);
port (
-- PCI signals
pciin : in pci_type;
pciout : out pci_type;
-- TB signals
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end pt_pci_target;
architecture tb of pt_pci_target is
constant T_O : integer := 9;
constant word : std_logic_vector(2 downto 0) := "100";
type response_element_type;
type response_element_ptr is access response_element_type;
type response_element_type is record
id : integer;
resp : pt_pci_response_type;
nxt : response_element_ptr;
end record;
signal resp : pt_pci_response_type;
constant non_resp : pt_pci_response_type := ((others => '0'), 0, 0, 0, 0, 0, 0, 0, true);
type resp_print_type is array (0 to 8) of string(1 to 5);
constant resp_print : resp_print_type := ("-----", "retry", "-----", "disw ", "diswo", "abort", "parer", "debug", "-----");
signal pci_core : pt_pci_target_in_type;
signal core_pci : pt_pci_target_out_type;
type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
type state_type is(idle,b_busy,respwait,tabort,write,read,latw,retry,dis);
type reg_type is record
state : state_type;
pci : pci_type;
pcien : std_logic;
aden : std_logic;
paren : std_logic;
erren : std_logic;
write : std_logic;
waitcycles : integer;
latcnt : integer;
curword : integer;
first : boolean;
di : std_logic_vector(31 downto 0);
ad : std_logic_vector(31 downto 0);
comm : std_logic_vector(3 downto 0);
config : config_header_type;
cbe : std_logic_vector(3 downto 0); -- *** sub-word write
retrycnt : std_logic_vector(7 downto 0);
resp : pt_pci_response_type;
resp_addr : std_logic_vector(31 downto 0);
parerr : std_logic;
firstacc : std_logic;
perren : std_logic_vector(1 downto 0);
pcirad : std_logic_vector(31 downto 0);
pcircbe : std_logic_vector(3 downto 0);
sigperr : std_logic_vector(2 downto 0);
end record;
signal r,rin : reg_type;
signal do : std_logic_vector(31 downto 0);
procedure readconf(ad : in std_logic_vector(5 downto 0); data : out std_logic_vector(31 downto 0)) is
begin
case conv_integer(ad) is
when 0 => data(31 downto 16) := (conv_std_logic_vector(slot,4) & r.config.devid(11 downto 0));
data(15 downto 0) := r.config.vendid;
when 1 => data(31 downto 16) := r.config.status; data(15 downto 0) := r.config.command;
when 2 => data(31 downto 8) := r.config.class_code; data(7 downto 0) := r.config.revid;
when 3 => data(31 downto 24) := r.config.bist; data(23 downto 16) := r.config.header_type;
data(15 downto 8) := r.config.lat_timer; data(7 downto 0) := r.config.cache_lsize;
when 4 => data := r.config.bar(0)(31 downto abits) & zero32(abits-1 downto 0);
when 5 => if bars > 1 then data := r.config.bar(1)(31 downto 9) & zero32(8 downto 1) & '1';
else data := (others => '0'); end if;
when 6 => if bars > 2 then data := r.config.bar(2)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 7 => if bars > 3 then data := r.config.bar(3)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 8 => if bars > 4 then data := r.config.bar(4)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 9 => if bars > 5 then data := r.config.bar(5)(31 downto abits) & zero32(abits-1 downto 0);
else data := (others => '0'); end if;
when 10 => data := r.config.cis_p;
when 11 => data(31 downto 16) := r.config.subid; data(15 downto 0) := r.config.subvendid;
when 12 => data := r.config.exp_rom_ba;
when 13 => data(31 downto 24) := r.config.max_lat; data(23 downto 16) := r.config.min_gnt;
data(15 downto 8) := r.config.int_pin; data(7 downto 0) := r.config.int_line;
when others =>
end case;
end procedure;
procedure writeconf(ad : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
cbe : in std_logic_vector(3 downto 0);
vconfig : out config_header_type) is
variable new_data : std_logic_vector(31 downto 0);
begin
readconf(ad,new_data);
if cbe(3) = '0' then new_data(31 downto 24) := data(31 downto 24); end if;
if cbe(2) = '0' then new_data(23 downto 16) := data(23 downto 16); end if;
if cbe(1) = '0' then new_data(15 downto 8) := data(15 downto 8); end if;
if cbe(0) = '0' then new_data( 7 downto 0) := data( 7 downto 0); end if;
case conv_integer(ad) is
-- when 0 => vconfig.devid := new_data(31 downto 16); vconfig.vendid <= new_data(15 downto 0);
when 1 => vconfig.status := new_data(31 downto 16); vconfig.command := new_data(15 downto 0);
when 2 => vconfig.class_code := new_data(31 downto 8); vconfig.revid := new_data(7 downto 0);
when 3 => vconfig.bist := new_data(31 downto 24); vconfig.header_type := new_data(23 downto 16);
vconfig.lat_timer := new_data(15 downto 8); vconfig.cache_lsize := new_data(7 downto 0);
when 4 => vconfig.bar(0) := new_data;
when 5 => vconfig.bar(1) := new_data;
when 6 => vconfig.bar(2) := new_data;
when 7 => vconfig.bar(3) := new_data;
when 8 => vconfig.bar(4) := new_data;
when 9 => vconfig.bar(5) := new_data;
when 10 => vconfig.cis_p := new_data;
when 11 => vconfig.subid := new_data(31 downto 16); vconfig.subvendid := new_data(15 downto 0);
when 12 => vconfig.exp_rom_ba := new_data;
when 13 => vconfig.max_lat := new_data(31 downto 24); vconfig.min_gnt := new_data(23 downto 16);
vconfig.int_pin := new_data(15 downto 8); vconfig.int_line := new_data(7 downto 0);
when others =>
end case;
end procedure;
function pci_hit(ad : std_logic_vector(31 downto 0);
c : std_logic_vector(3 downto 0);
idsel : std_logic;
con : config_header_type) return boolean is
variable hit : boolean;
begin
hit := false;
if ((c = CONF_READ or c = CONF_WRITE)
and idsel = '1' and ad(1 downto 0) = "00")
then hit := true;
else
for i in 0 to bars-1 loop
if i = 1 then
if ((c = IO_READ or c = IO_WRITE)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
else
if ((c = MEM_READ or c = MEM_WRITE or c = MEM_R_MULT or c = MEM_R_LINE or c = MEM_W_INV)
and ad(31 downto abits) = con.bar(i)(31 downto abits))
then hit := true; end if;
end if;
end loop;
end if;
return(hit);
end function;
-- Description: Insert a response into the linked list of responses
procedure insert_resp (
constant id : in integer;
variable resp_root : inout response_element_ptr;
signal resp : in pt_pci_response_type) is
variable elem : response_element_ptr;
begin -- insert_resp
elem := resp_root;
if elem /= NULL then
while elem.nxt /= NULL loop elem := elem.nxt; end loop;
elem.nxt := new response_element_type'(id, resp, NULL);
else
resp_root := new response_element_type'(id, resp, NULL);
end if;
end insert_resp;
-- Description: Searches the list for a response to a particular address.
-- If a response is found the response is returned via 'resp' and 'found'
-- is set to true, otherwise 'found' is set to false.
procedure get_resp (
variable resp_root : inout response_element_ptr;
signal addr : in std_logic_vector(31 downto 0);
signal resp : out pt_pci_response_type;
variable found : out boolean) is
variable elem, prev : response_element_ptr;
variable lfound : boolean := false;
begin -- get_resp
prev := resp_root;
elem := resp_root;
--print(tost(NOW/1 ns) & "ns get_resp: addr[" & tost(addr) & "]");
while elem /= NULL and not lfound loop
-- Check if response is a match for address
if addr(abits-1 downto 0) = elem.resp.addr(abits-1 downto 0) then
resp <= elem.resp;
lfound := true;
resp.valid <= true;
--if prev = resp_root then
-- resp_root := elem.nxt;
--else
-- prev.nxt := elem.nxt;
--end if;
--deallocate(elem);
end if;
if not lfound then
prev := elem;
elem := elem.nxt;
end if;
end loop;
--print(tost(NOW/1 ns) & "ns get_resp: found[" & tost(lfound) & "]");
if lfound then found := true;
else
found := false;
resp.retry <= 0;
resp.ws <= 0;
resp.diswithout <= 0;
resp.diswith <= 0;
resp.parerr <= 0;
resp.abort <= 0;
resp.debug <= 0;
resp.valid <= false;
end if;
end get_resp;
-- Description: Searches the list for a response with a particular addr.
-- If a response is found the response is removed and the id
-- will match the input id.
procedure rm_resp (
variable resp_root : inout response_element_ptr;
constant addr : in std_logic_vector(31 downto 0) )is
variable elem, prev : response_element_ptr;
variable lfound : boolean := false;
begin -- rm_resp
prev := resp_root;
elem := resp_root;
while elem /= NULL and not lfound loop
if addr(abits-1 downto 0) = elem.resp.addr(abits-1 downto 0) then
if prev = resp_root then
resp_root := elem.nxt;
else
prev.nxt := elem.nxt;
end if;
deallocate(elem);
lfound := true;
else
prev := elem;
elem := elem.nxt;
end if;
end loop;
end rm_resp;
-- Description: Removes all responses in list
procedure rm_all_resp (
variable resp_root : inout response_element_ptr) is
variable elem, curr : response_element_ptr;
variable lfound : boolean := false;
begin -- rm_all_resp
curr := resp_root;
elem := resp_root;
while elem /= NULL loop
curr := elem;
elem := elem.nxt;
deallocate(curr);
end loop;
resp_root := NULL;
end rm_all_resp;
begin
cont : process
variable first : boolean := true;
variable mem : mem_type;
begin
if first then
for i in 0 to ((2**abits)-1) loop
mem(i) := (others => '0');
end loop;
first := false;
elsif r.ad(0) /= 'U' then
do <= mem(conv_integer(to_x01(r.ad)));
--if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := r.di; end if; -- *** sub-word write
if r.write = '1' then
case r.cbe is
when "1110" =>
mem(conv_integer(to_x01(r.ad)))(7 downto 0) := r.di(7 downto 0);
when "1101" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 8) := r.di(15 downto 8);
when "1011" =>
mem(conv_integer(to_x01(r.ad)))(23 downto 16) := r.di(23 downto 16);
when "0111" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 24) := r.di(31 downto 24);
when "1100" =>
mem(conv_integer(to_x01(r.ad)))(15 downto 0) := r.di(15 downto 0);
when "0011" =>
mem(conv_integer(to_x01(r.ad)))(31 downto 16) := r.di(31 downto 16);
when others =>
mem(conv_integer(to_x01(r.ad))) := r.di;
end case;
end if;
end if;
wait for 1 ns;
end process;
core_resp : process
variable resp_root : response_element_ptr := NULL;
variable found : boolean;
begin
if pci_core.req /= '1' and dbgi.req /= '1' then
wait until pci_core.req = '1' or dbgi.req = '1';
end if;
if dbgi.req = '1' then
if dbgi.insert = '1' then
insert_resp(0, resp_root, dbgi.resp);
elsif dbgi.remove = '1' then
if dbgi.rmall = '1' then
rm_all_resp(resp_root);
else
rm_resp(resp_root, dbgi.addr);
end if;
else
dbgo.valid <= '0';
get_resp(resp_root, pci_core.addr, dbgo.resp, found);
if found = true then dbgo.valid <= '1'; end if;
end if;
dbgo.ack <= '1';
wait until dbgi.req = '0';
dbgo.ack <= '0';
end if;
if pci_core.req = '1' then
if pci_core.insert = '1' then
insert_resp(0, resp_root, pci_core.resp);
else
core_pci.valid <= '0';
get_resp(resp_root, pci_core.addr, core_pci.resp, found);
if found = true then core_pci.valid <= '1'; end if;
end if;
core_pci.ack <= '1';
wait until pci_core.req = '0';
core_pci.ack <= '0';
end if;
end process;
--comb : process(pciin, do)
comb : process
variable v : reg_type;
procedure sync_with_core is
begin
pci_core.req <= '1';
wait until core_pci.ack = '1';
pci_core.req <= '0';
wait until core_pci.ack = '0';
end sync_with_core;
begin
if pciin.syst.rst = '0' then
v.state := idle;
v.config := conf;
v.waitcycles := 1;
v.latcnt := latency;
v.ad := (others => '0');
v.di := (others => '0');
v.retrycnt := (others => '0');
v.resp.valid := false;
v.perren := (others => '0');
v.sigperr := (others => '0');
elsif rising_edge(pciin.syst.clk) then
v := r; v.write := '0';
v.pci.ad.par := xorv(r.pci.ad.ad & pciin.ad.cbe);
v.pci.ad.par := v.pci.ad.par xor r.parerr; -- Add par error
v.paren := r.aden; v.erren := not (r.perren(1) or r.perren(0)); --v.erren := r.paren;
v.perren(1) := v.perren(0);
v.pcirad := pciin.ad.ad; v.pcircbe := pciin.ad.cbe;
v.pci.err.perr := not r.perren(0) or not (xorv(r.pcirad & r.pcircbe & pciin.ad.par) or r.sigperr(1));-- or '1'; -- FIXME: ... disable perr
v.sigperr(1) := r.sigperr(0); v.sigperr(2) := r.sigperr(1); v.sigperr(0) := '0';
case r.state is
when idle =>
v.perren(0) := '0';
v.firstacc := '1';
if (r.pci.ifc.trdy and r.pci.ifc.stop and r.pci.ifc.devsel) = '1' then v.pcien := '1'; end if;
v.aden := '1'; v.waitcycles := 1; v.latcnt := latency; v.first := true;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.curword := 0;
v.pci.ifc.devsel := '1'; --v.pci.err.perr := '1';
if pciin.ifc.frame = '0' then
v.comm := pciin.ad.cbe;
if pci_hit(pciin.ad.ad,pciin.ad.cbe,pciin.ifc.idsel(slot),v.config) then
pci_core.addr <= zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0); pci_core.insert <= '0';
pci_core.resp.retry <= 0; pci_core.resp.ws <= 0; pci_core.resp.diswithout <= 0; pci_core.resp.diswith <= 0;
sync_with_core;
if core_pci.valid = '1' and r.resp.valid = false then
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp1: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
v.resp := core_pci.resp;
v.resp.valid := true;
--if resptime > core_pci.resp.ws then v.resp.ws := resptime; end if; -- use resptime if grater, else use access waitstates
--v.resp.ws := resptime; -- Always use resptime
elsif r.resp.valid = false then
v.resp := non_resp;
end if;
--if r.retrycnt /= x"00" then -- retry response
-- if r.retrycnt = x"ff" then v.retrycnt := x"02";
-- else v.retrycnt := v.retrycnt - 1; end if;
-- v.state := respwait;
--else
-- v.retrycnt := x"ff";
v.ad := zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0);
--if r.waitcycles = resptime then
if r.waitcycles = resptime and v.resp.retry = 0 then
--if v.resp.ws = 0 and v.resp.retry = 0 then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if pciin.ad.cbe(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
--if v.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
--if v.resp.abort = 1 then v.pci.ifc.trdy := '1'; end if;
if v.resp.abort = 1 then
v.state := tabort;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.pci.ifc.devsel := '0';
end if;
if v.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := v.ad + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp2: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
else v.state := read; v.aden := '0'; end if;
else v.state := respwait; v.waitcycles := r.waitcycles+1; end if;
--else v.state := respwait; if v.resp.ws /= 0 then v.resp.ws := v.resp.ws - 1; end if; end if;
--end if;
else
v.state := b_busy;
end if;
end if;
when b_busy =>
if (pciin.ifc.frame and pciin.ifc.irdy) = '1' then
v.state := idle;
end if;
when retry => -- retry response
v.resp.ws := 0;
if pciin.ifc.frame = '1' then
v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1'; v.pcien := '1';
v.state := idle;
if r.resp.retry /= 0 then v.resp.retry := r.resp.retry - 1; end if;
end if;
when respwait => -- Initial response time
--if r.retrycnt /= x"ff" then
if r.resp.valid = true and r.resp.retry /= 0 then
v.pci.ifc.devsel := '0'; v.pci.ifc.stop := '0'; v.pcien := '0';
v.state := retry;
elsif r.waitcycles = resptime then
--elsif r.resp.ws <= 1 then
v.pci.ifc.devsel := '0'; v.pcien := '0';
if r.comm(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
--if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; end if;
--if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := r.ad + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
else v.state := read; v.aden := '0'; v.resp.ws := 0; end if;
if r.resp.abort = 1 then
v.state := tabort;
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.pci.ifc.devsel := '0';
end if;
else v.waitcycles := r.waitcycles+1; end if;
--v.resp.ws := 0;
--else v.resp.ws := r.resp.ws - 1; end if;
when tabort => -- Target abort on first data phase
v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1';
if pciin.ifc.frame = '1' and pciin.ifc.irdy = '0' and (r.pci.ifc.trdy and r.pci.ifc.stop) = '0' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
end if;
when write => -- Write access
v.perren(0) := '1';
--if pciin.ifc.irdy = '0' then
if pciin.ifc.irdy = '0' and r.pci.ifc.trdy = '0' then
v.curword := r.curword+1;
if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,pciin.ad.cbe,v.config);
--else v.di := pciin.ad.ad; v.write := '1'; end if; -- *** sub-word write
else v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
if r.resp.ws = 0 then
v.firstacc := '0';
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
if r.resp.parerr = 1 then v.sigperr(0) := '1'; end if;
v.resp_addr := r.resp_addr + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
end if;
--elsif r.resp.abort = 1 then -- Target abort on first data phase
-- v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1';
end if;
if r.write = '1' then v.ad := r.ad + "100"; end if;
if pciin.ifc.frame = '1' and pciin.ifc.irdy = '0' and (r.pci.ifc.trdy and r.pci.ifc.stop) = '0' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
--elsif (r.latcnt > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.latcnt := r.latcnt-1;
elsif (r.resp.ws > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.resp.ws := r.resp.ws-1;
end if;
when read => -- Read access
v.perren(0) := '0';
v.pci.ifc.trdy := '0';
if (pciin.ifc.irdy = '0' or r.first = true) then
v.ad := r.ad + "100"; v.first := false;
if r.comm = CONF_READ then readconf(r.ad(7 downto 2),v.pci.ad.ad);
else v.pci.ad.ad := do; end if;
if r.resp.parerr = 1 then v.parerr := '1'; else v.parerr := '0'; end if; -- Add par error
if r.resp.ws = 0 then
v.firstacc := '0';
if r.firstacc = '0' and (r.resp.diswith = 1 or r.resp.diswithout = 1) then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.firstacc = '0' and r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; v.state := dis; end if;
pci_core.addr <= v.ad; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
end if;
end if;
if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then v.curword := r.curword+1; end if;
if (pciin.ifc.frame and not (pciin.ifc.trdy and pciin.ifc.stop)) = '1' then
v.state := idle; v.aden := '1';
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
v.resp.valid := false;
--elsif (r.latcnt > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
elsif (r.resp.ws > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
--v.state := latw; v.latcnt := r.latcnt-1; v.pci.ifc.trdy := '1';
v.state := latw; v.resp.ws := r.resp.ws-1; v.pci.ifc.trdy := '1';
end if;
when latw => -- Latency between data phases
v.pci.ifc.trdy := '1';
if r.write = '1' then v.ad := r.ad + "100"; end if;
--if (r.latcnt <= 1 and r.comm(0) = '0') then
if (r.resp.ws <= 1 and r.comm(0) = '0') then
--v.latcnt := latency;
v.resp.ws := 0;
v.state := read; v.aden := '0'; v.pci.ifc.trdy := '0';
--elsif r.latcnt = 0 then
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
pci_core.addr <= r.ad; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
elsif r.resp.ws = 0 then
--v.latcnt := latency;
v.resp.ws := 0;
v.state := write; v.pci.ifc.trdy := '0';
if r.resp.diswith = 1 or r.resp.diswithout = 1 then v.pci.ifc.stop := '0'; v.state := dis; end if;
if r.resp.diswithout = 1 then v.pci.ifc.trdy := '1'; end if;
if r.resp.abort = 1 then v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '0'; v.pci.ifc.devsel := '1'; end if;
v.resp_addr := r.resp_addr + "100"; pci_core.addr <= v.resp_addr; pci_core.insert <= '0'; sync_with_core;
if core_pci.valid = '1' then v.resp := core_pci.resp; v.resp.valid := true;
if core_pci.resp.debug > 0 then print(tost(NOW/1 ns) & "ns Resp: " & tost(core_pci.resp.addr) & ", "
& resp_print(core_pci.resp.retry*1) & ", " & "ws:" & tost(core_pci.resp.ws) & ", " & resp_print(core_pci.resp.diswith*3+core_pci.resp.diswithout*4)
& ", " & resp_print(core_pci.resp.abort*5) & ", " & resp_print(core_pci.resp.parerr*6) & ", " & tost(core_pci.resp.valid));
end if;
else v.resp := non_resp; end if;
--else v.latcnt := r.latcnt-1; end if;
else v.resp.ws := r.resp.ws-1; end if;
if (pciin.ifc.frame and not r.pci.ifc.stop) = '1' then -- done if disconnect ???
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
v.resp.valid := false;
end if;
when dis =>
v.perren(0) := '0';
v.pci.ifc.stop := '0';
if r.write = '1' then v.ad := r.ad + "100"; end if;
if pciin.ifc.irdy = '0' then
v.pci.ifc.trdy := '1';
if r.pci.ifc.trdy = '0' then
if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,pciin.ad.cbe,v.config);
elsif r.comm(0) = '1' then v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
end if;
end if;
if pciin.ifc.frame = '1' then
v.state := idle;
v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1'; v.pci.ifc.stop := '1';
v.resp.valid := false;
end if;
when others =>
end case;
-- Disconnect type
--if ((v.curword+1) >= rbuf) then
-- if pciin.ifc.frame = '1' then
-- v.pci.ifc.stop := '1';
-- elsif stopwd then
-- if r.pci.ifc.stop = '1' then
-- v.pci.ifc.stop := v.pci.ifc.trdy;
-- else
-- if pciin.ifc.irdy = '0' then v.pci.ifc.trdy := '1'; end if;
-- v.pci.ifc.stop := '0';
-- end if;
-- else
-- v.pci.ifc.stop := '0';
-- v.pci.ifc.trdy := '1';
-- end if;
--end if;
end if;
r <= v;
--rin <= v;
wait on pciin.syst.clk, pciin.syst.rst;
end process;
--clockreg : process(pciin.syst)
--begin
-- if rising_edge(pciin.syst.clk) then
-- r <= rin;
-- end if;
--end process;
pciout.ad.ad <= r.pci.ad.ad after tval when r.aden = '0' else (others => 'Z') after tval;
pciout.ad.par <= r.pci.ad.par after tval when (r.paren = '0' and (r.pci.ad.par = '1' or r.pci.ad.par = '0')) else 'Z' after tval;
pciout.ifc.trdy <= r.pci.ifc.trdy after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.stop <= r.pci.ifc.stop after tval when r.pcien = '0' else 'Z' after tval;
pciout.ifc.devsel <= r.pci.ifc.devsel after tval when r.pcien = '0' else 'Z' after tval;
pciout.err.perr <= r.pci.err.perr after tval when r.erren = '0' else 'Z' after tval;
-- Unused signals
pciout.ad.cbe <= (others => 'Z');
pciout.ifc.frame <= 'Z';
pciout.ifc.irdy <= 'Z';
pciout.ifc.lock <= 'Z';
pciout.ifc.idsel <= (others => 'Z');
pciout.err.serr <= 'Z';
pciout.arb <= arb_const;
pciout.syst <= syst_const;
pciout.ext64 <= ext64_const;
pciout.cache <= cache_const;
pciout.int <= (others => 'Z');
end;
-- pragma translate_on
|
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for an entity may be read passed
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (port) of mode 'inout' for a block may be read failed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (port) of mode 'inout' for an entity may be read failed
-- NEED RESULT: ARCH00659.Proc2: The predefined attributes of an interface object (variable parameter) of mode 'inout' for a subp may be read failed
-- NEED RESULT: ARCH00659: The predefined attributes of an interface object (signal parameter) of mode 'inout' for a subp may be read failed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (signal parameter) of mode 'inout' for a subp may be read passed
-- NEED RESULT: ARCH00659: The predefined signal attributes of an interface object (port) of mode 'inout' for a block may be read passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00659
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (17)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00659
-- PKG00659/BODY
-- ENT00659(ARCH00659)
-- ENT00659_Test_Bench(ARCH00659_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00659 is
subtype ST is Bit_Vector ( 10 to 20 ) ;
type Bit_Vector_Array is array (Integer range <>) of ST;
function bf_BV (P : Bit_Vector_Array) return ST;
subtype rBV is bf_BV ST ;
type Int_Arr is array ( Integer range <> ) of Integer ;
function bf_I ( P : Int_Arr ) return Integer ;
subtype rI is bf_I Integer ;
end PKG00659 ;
package body PKG00659 is
function bf_BV (P : Bit_Vector_Array) return ST is
begin
return P(P'Left) ;
end bf_BV ;
function bf_I ( P : Int_Arr ) return Integer is
begin
return P(P'Left) ;
end bf_I ;
end PKG00659 ;
use WORK.STANDARD_TYPES.all, WORK.PKG00659.all ;
entity ENT00659 is
port ( Pt1 : inout rBV ;
Pt2 : inout rI ) ;
end ENT00659 ;
--
architecture ARCH00659 of ENT00659 is
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
procedure Proc2 ( variable G : inout Bit_Vector ) is
subtype ST_Up is integer range G'RANGE ;
subtype ST_Down is integer range G'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659.Proc2" ,
"The predefined attributes of an interface "&
"object (variable parameter) of mode 'inout' for a "&
"subp may be read" ,
(G'LEFT = 10) and
(G'RIGHT(1) = 20) and
(G'HIGH(1) = 20) and
(G'LOW = 10) and
(G'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10) ) ;
end Proc2 ;
Procedure Proc3 ( signal Pt1 : inout Bit_Vector;
variable correct : out boolean ) is
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
correct := (Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
;
end Proc3 ;
procedure Proc4 ( signal Pt2 : inout Integer;
variable correct : out boolean ) is
begin
correct :=
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
;
end Proc4 ;
begin
P2 :
process -- Check formal port on entity (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (port) of mode 'inout' for an entity may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process P2 ;
P3 :
process ( Pt2 ) -- Check formal port on entity (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'inout' for an entity may "&
"be read" ,
(Pt2'DELAYED(10 ns) = -2) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2)
) ;
end if ;
end process P3 ;
P4 :
process ( Pt2 ) -- Check formal parameters in a subprogram
variable V : Bit_Vector (10 to 20) ;
variable First_Time : boolean := True ;
variable correct : boolean ;
begin
if First_Time then
First_Time := false ;
else
Proc2 (G => V) ;
Proc3 (Pt1, correct) ;
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (signal parameter) of mode 'inout' for a subp "&
"may be read" ,
correct
) ;
Proc4 (Pt2, correct) ;
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (signal parameter) of mode 'inout' for a subp "&
"may be read" ,
correct
) ;
end if ;
end process P4 ;
L1 : -- Check block ports/generics
block
port ( Pt1 : inout Bit_Vector ;
Pt2 : inout Real ) ;
port map ( Pt1 => Pt1, To_Integer(Pt2) => To_Real(Pt2) ) ;
begin
BP2 :
process -- Check formal port on block (no signal attributes)
subtype ST_Up is integer range Pt1'RANGE ;
subtype ST_Down is integer range Pt1'REVERSE_RANGE(1) ;
begin
test_report ( "ARCH00659" ,
"The predefined attributes of an interface "&
"object (port) of mode 'inout' for a block may be read" ,
(Pt1'LEFT = 10) and
(Pt1'RIGHT(1) = 20) and
(Pt1'HIGH(1) = 20) and
(Pt1'LOW = 10) and
(Pt1'LENGTH = 11) and
(ST_Up'LEFT = 10) and
(ST_Up'RIGHT = 20) and
(ST_Down'LEFT = 20) and
(ST_Down'RIGHT = 10)
) ;
wait ;
end process BP2 ;
BP3 :
process ( Pt2 ) -- Check formal port on a block (signal attributes)
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00659" ,
"The predefined signal attributes of an interface "&
"object (port) of mode 'inout' for a block may be read" ,
(Pt2'DELAYED(10 ns) = -2.0) and
(Not Pt2'STABLE(10 ns)) and
(Not Pt2'QUIET(10 ns)) and
(Pt2'EVENT) and
(Pt2'ACTIVE) and
(STD.STANDARD.NOW - Pt2'LAST_EVENT = 10 ns) and
(STD.STANDARD.NOW - Pt2'LAST_ACTIVE = 10 ns) and
(Pt2'LAST_VALUE = -2.0)
) ;
end if ;
end process BP3 ;
end block L1 ;
end ARCH00659 ;
--
use WORK.PKG00659.all;
entity ENT00659_Test_Bench is
end ENT00659_Test_Bench ;
architecture ARCH00659_Test_Bench of ENT00659_Test_Bench is
begin
L1:
block
component UUT
end component ;
constant C : ST := B"10101010101" ;
signal S1 : rBV := C;
signal S2 : rI := -2;
for CIS1 : UUT use entity WORK.ENT00659 ( ARCH00659 )
port map ( S1, S2 ) ;
begin
SigA : S2 <= transport -1 after 10 ns ;
CIS1 : UUT ;
end block L1 ;
end ARCH00659_Test_Bench ;
--
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_bram.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Block memory-based Decoder for decoding 8b/10b encoded symbols
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.textio.ALL; -- required to initialize bram from .mif
LIBRARY decode_8b10b;
USE decode_8b10b.decode_8b10b_pkg.ALL;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_bram IS
GENERIC (
C_ELABORATION_DIR : STRING := "./../../src/";
C_HAS_BPORTS : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000";
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_bram;
-----------------------------------------------------------------------------
-- Architecture
-----------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_bram IS
-----------------------------------------------------------------------------
-- .MIF file support
-----------------------------------------------------------------------------
-- Specify relative path for .mif file
CONSTANT mif_file_name : STRING := "dec.mif";
-- Initialize inferred ROM from mif file
TYPE RomType IS ARRAY(0 TO 1023) OF BIT_VECTOR(13 DOWNTO 0);
IMPURE FUNCTION InitRomFromFile (RomFileName : IN STRING) RETURN RomType IS
FILE RomFile : TEXT OPEN READ_MODE IS RomFileName;
VARIABLE RomFileLine : LINE;
VARIABLE ROM : RomType;
BEGIN
FOR I IN RomType'range LOOP
READLINE (RomFile, RomFileLine);
READ (RomFileLine, ROM(I));
END LOOP;
RETURN ROM;
END FUNCTION;
SIGNAL ROM : RomType := InitRomFromFile(mif_file_name);
-----------------------------------------------------------------------------
-- Constant initialization values for internal signals ROM_data(_b)
-----------------------------------------------------------------------------
CONSTANT INIT_DATA : STRING :=
concat_sinit(C_SINIT_RUN_DISP,C_SINIT_KOUT, C_SINIT_DOUT);
CONSTANT INIT_DATA_B : STRING :=
concat_sinit(C_SINIT_RUN_DISP_B,C_SINIT_KOUT_B, C_SINIT_DOUT_B);
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT_B,8);
SIGNAL kout_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT_B);
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
SIGNAL run_disp_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP_B);
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP_B,2);
--Internal signals tied to the 14x1k block memory----------------------------
SIGNAL ROM_address : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ROM_data : STD_LOGIC_VECTOR(13 DOWNTO 0) :=
str_to_slv(INIT_DATA, 14);
-----------------------------------------------------------------------------
-- BEGIN ARCHITECTURE
-----------------------------------------------------------------------------
BEGIN
-- Map internal signals to outputs
DOUT <= dout_i;
KOUT <= kout_i;
DOUT_B <= dout_b_i;
KOUT_B <= kout_b_i;
RUN_DISP <= run_disp_i;
RUN_DISP_B <= run_disp_b_i;
SYM_DISP <= sym_disp_i;
SYM_DISP_B <= sym_disp_b_i;
-----------------------------------------------------------------------------
-- Decoder A
-----------------------------------------------------------------------------
ROM_address <= DIN;
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (CE = '1') THEN
IF (SINIT = '1') THEN
ROM_data <= str_to_slv(INIT_DATA, 14) AFTER TFF;
ELSE
ROM_data <= to_stdlogicvector(ROM(conv_integer(ROM_address))) AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Map ROM data into dout, kout, and code_err outputs
dout_i <= ROM_data(7 DOWNTO 0);
kout_i <= ROM_data(8);
CODE_ERR <= ROM_data(9);
-----------------------------------------------------------------------------
-- Instantiate disparity logic block for Decoder A
-----------------------------------------------------------------------------
dla : ENTITY decode_8b10b.decode_8b10b_disp
GENERIC MAP(
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_SYM_DISP => C_HAS_SYM_DISP
)
PORT MAP(
SINIT => SINIT,
CE => CE,
CLK => CLK,
SYM_DISP => ROM_data(13 DOWNTO 10),
DISP_IN => DISP_IN,
RUN_DISP => run_disp_i,
DISP_ERR => DISP_ERR,
USER_SYM_DISP => sym_disp_i
);
-- create ND output
gndr : IF (C_HAS_ND = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF ((SINIT = '1') AND (CE = '1')) THEN
ND <= '0' AFTER TFF;
ELSE
ND <= CE AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gndr;
-------------------------------------------------------------------------------
-- Generate Decoder B
-------------------------------------------------------------------------------
gdp : IF (C_HAS_BPORTS=1) GENERATE
--Internal signals tied to the 14x1k block memory (B)----------------------
SIGNAL ROM_address_b : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ROM_data_b : STD_LOGIC_VECTOR(13 DOWNTO 0) :=
str_to_slv(INIT_DATA_B, 14);
BEGIN
ROM_address_b <= DIN_B;
PROCESS (CLK_B)
BEGIN
IF (CLK_B'event AND CLK_B = '1') THEN
IF (CE_B = '1') THEN
IF (SINIT_B = '1') THEN
ROM_data_b <= str_to_slv(INIT_DATA_B, 14) AFTER TFF;
ELSE
ROM_data_b <= to_stdlogicvector(ROM(conv_integer(ROM_address_b)))
AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Map ROM_data_b into dout_b, kout_b, and code_err_b outputs
dout_b_i <= ROM_data_b(7 DOWNTO 0);
kout_b_i <= ROM_data_b(8);
CODE_ERR_B <= ROM_data_b(9);
-----------------------------------------------------------------------------
-- Instantiate disparity logic block for Decoder B
-----------------------------------------------------------------------------
dlb : ENTITY decode_8b10b.decode_8b10b_disp
GENERIC MAP(
C_SINIT_DOUT => C_SINIT_DOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B,
C_HAS_DISP_IN => C_HAS_DISP_IN_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP_B
)
PORT MAP(
SINIT => SINIT_B,
CE => CE_B,
CLK => CLK_B,
SYM_DISP => ROM_data_b(13 DOWNTO 10),
DISP_IN => DISP_IN_B,
RUN_DISP => run_disp_b_i,
DISP_ERR => DISP_ERR_B,
USER_SYM_DISP => sym_disp_b_i
);
-- create ND_B output
gndbr : IF (C_HAS_ND_B = 1) GENERATE
PROCESS (CLK_B)
BEGIN
IF (CLK_B'event AND CLK_B = '1') THEN
IF ((SINIT_B = '1') AND (CE_B = '1')) THEN
ND_B <= '0' AFTER TFF;
ELSE
ND_B <= CE_B AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gndbr;
END GENERATE gdp;
END xilinx;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
--------------------------------------------------------------------------------------------------
-- Interpolator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.interpolator_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_interpolator is
end tb_interpolator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_interpolator is
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig_decimated.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig_interpolated.csv";
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs_decimated.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs_interpolated.csv";
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decimated.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_interpolated.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_20ns,
sig(data) => sig_in);
--Instantiate unit under test
uut : entity work.interpolator(behave)
-- generic map(h => LOW_PASS)
generic map(h => PR_SYNTHESIS_LOW)
port map( clk_high => clk_10ns,
clk_low => clk_20ns,
rst => rst,
sig_low => sig_in,
sig_high => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 36ns;
rst <= '0';
wait;
end process;
end sim;
|
-- Copyright (c) 2015-2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for shift operators (logical and arithmetic)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity shifter is
port(input : in signed(7 downto 0);
out_srl, out_sll, out_sra, out_sla : out signed(7 downto 0);
out_shl_u, out_shr_u : out unsigned(7 downto 0);
out_shl_s, out_shr_s : out signed(7 downto 0)
);
end entity shifter;
architecture test of shifter is
begin
process(input)
-- test the unsigned variant of shift_left/right() functions
variable unsigned_input : unsigned(7 downto 0);
begin
unsigned_input := input;
out_srl <= input srl 1;
out_sll <= input sll 1;
out_sra <= input sra 1;
out_sla <= input sla 1;
out_shl_s <= shift_left(input, 2);
out_shr_s <= shift_right(input, 2);
out_shl_u <= shift_left(unsigned_input, 2);
out_shr_u <= shift_right(unsigned_input, 2);
end process;
end architecture test;
|
-- Copyright (c) 2015-2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for shift operators (logical and arithmetic)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity shifter is
port(input : in signed(7 downto 0);
out_srl, out_sll, out_sra, out_sla : out signed(7 downto 0);
out_shl_u, out_shr_u : out unsigned(7 downto 0);
out_shl_s, out_shr_s : out signed(7 downto 0)
);
end entity shifter;
architecture test of shifter is
begin
process(input)
-- test the unsigned variant of shift_left/right() functions
variable unsigned_input : unsigned(7 downto 0);
begin
unsigned_input := input;
out_srl <= input srl 1;
out_sll <= input sll 1;
out_sra <= input sra 1;
out_sla <= input sla 1;
out_shl_s <= shift_left(input, 2);
out_shr_s <= shift_right(input, 2);
out_shl_u <= shift_left(unsigned_input, 2);
out_shr_u <= shift_right(unsigned_input, 2);
end process;
end architecture test;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc100.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p29n06i00100pkg is
type int_1 is range 1 to 32;
attribute pin_number : int_1;
end c04s03b02x00p29n06i00100pkg;
use work.c04s03b02x00p29n06i00100pkg.all;
ENTITY c04s03b02x00p29n06i00100ent IS
port ( P2 : out bit) ;
attribute pin_number of P2 : signal is 1;
END c04s03b02x00p29n06i00100ent;
ARCHITECTURE c04s03b02x00p29n06i00100arch OF c04s03b02x00p29n06i00100ent IS
BEGIN
TESTING: PROCESS
variable pn : int_1;
BEGIN
pn := 1;
assert NOT( P2'pin_number = pn )
report "***PASSED TEST: c04s03b02x00p29n06i00100" severity NOTE;
assert ( P2'pin_number = pn )
report "***FAILED TEST: c04s03b02x00p29n06i00100 - Reading user defined attributes of interface elements of mode 'out' should be permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc100.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p29n06i00100pkg is
type int_1 is range 1 to 32;
attribute pin_number : int_1;
end c04s03b02x00p29n06i00100pkg;
use work.c04s03b02x00p29n06i00100pkg.all;
ENTITY c04s03b02x00p29n06i00100ent IS
port ( P2 : out bit) ;
attribute pin_number of P2 : signal is 1;
END c04s03b02x00p29n06i00100ent;
ARCHITECTURE c04s03b02x00p29n06i00100arch OF c04s03b02x00p29n06i00100ent IS
BEGIN
TESTING: PROCESS
variable pn : int_1;
BEGIN
pn := 1;
assert NOT( P2'pin_number = pn )
report "***PASSED TEST: c04s03b02x00p29n06i00100" severity NOTE;
assert ( P2'pin_number = pn )
report "***FAILED TEST: c04s03b02x00p29n06i00100 - Reading user defined attributes of interface elements of mode 'out' should be permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00100arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc100.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x00p29n06i00100pkg is
type int_1 is range 1 to 32;
attribute pin_number : int_1;
end c04s03b02x00p29n06i00100pkg;
use work.c04s03b02x00p29n06i00100pkg.all;
ENTITY c04s03b02x00p29n06i00100ent IS
port ( P2 : out bit) ;
attribute pin_number of P2 : signal is 1;
END c04s03b02x00p29n06i00100ent;
ARCHITECTURE c04s03b02x00p29n06i00100arch OF c04s03b02x00p29n06i00100ent IS
BEGIN
TESTING: PROCESS
variable pn : int_1;
BEGIN
pn := 1;
assert NOT( P2'pin_number = pn )
report "***PASSED TEST: c04s03b02x00p29n06i00100" severity NOTE;
assert ( P2'pin_number = pn )
report "***FAILED TEST: c04s03b02x00p29n06i00100 - Reading user defined attributes of interface elements of mode 'out' should be permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00100arch;
|
-----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ahb2mig_series7
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_SERIES7 = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x25v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_SERIES7 = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_series7 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4,
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 5.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model;
end generate;
no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 32)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 2)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_gtxclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 9, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx KC705 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: tcp_tx_packet - Behavioral
--
-- Description: Construct and send out TCP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
tcp_tx_busy : out std_logic;
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end tcp_tx_packet;
architecture Behavioral of tcp_tx_packet is
signal busy_countdown : unsigned(7 downto 0) := (others => '0');
-- For holding the destination and port details on the first data transfer
signal tcp_tx_hdr_valid_last : STD_LOGIC := '0';
signal tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_length : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal pre_tcp_valid : STD_LOGIC := '0';
signal pre_tcp_data : STD_LOGIC_VECTOR (7 downto 0);
component buffer_count_and_checksum_data is
generic (min_length : natural);
Port ( clk : in STD_LOGIC;
hdr_valid_in : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0);
data_checksum : out std_logic_vector(15 downto 0));
end component;
signal data_length : std_logic_vector(15 downto 0);
signal data_checksum : std_logic_vector(15 downto 0);
component tcp_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
tcp_src_port : in std_logic_vector(15 downto 0);
tcp_dst_port : in std_logic_vector(15 downto 0);
tcp_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : in std_logic := '0';
tcp_flag_ack : in std_logic := '0';
tcp_flag_psh : in std_logic := '0';
tcp_flag_rst : in std_logic := '0';
tcp_flag_syn : in std_logic := '0';
tcp_flag_fin : in std_logic := '0';
tcp_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end component;
signal pre_ip_valid : STD_LOGIC := '0';
signal pre_ip_data : STD_LOGIC_VECTOR (7 downto 0);
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_data_length : std_logic_vector(15 downto 0);
component ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end component;
signal pre_header_valid : STD_LOGIC := '0';
signal pre_header_data : STD_LOGIC_VECTOR (7 downto 0);
component ethernet_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_type : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ether_dst_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal complete_valid : STD_LOGIC := '0';
signal complete_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component transport_commit_buffer
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
begin
process(clk)
begin
if rising_edge(clk) then
-- Capture the destination address data on the first cycle of the data packet
if tcp_tx_hdr_valid = '1' then
if tcp_tx_hdr_valid_last = '0' then
tx_src_port <= tcp_tx_src_port;
tx_dst_mac <= tcp_tx_dst_mac;
tx_dst_ip <= tcp_tx_dst_ip;
tx_dst_port <= tcp_tx_dst_port;
busy_countdown <= to_unsigned(8+64+12-4,8);
-- 8 = preamble
-- 64 = minimum ethernet header
-- 12 = minimum inter-packet gap
-- and -4 is a fix for latency
tcp_tx_busy <= '1';
else
-- Allow for the bytes that will be added
if busy_countdown > 8+14+20+8+4+12 -3 then
-- allow for premable (8)
-- and ethernet Header(14)
-- and ip header (20)
-- and udp hereader (8)
-- and ethernet FCS (4)
-- and minimum inter-packet gap
-- and -3 is a fix for latency
busy_countdown <= busy_countdown-1;
end if;
end if;
else
-- Keep udp_tx_busy asserted to allow for
-- everything to be wrapped around the data
if busy_countdown > 0 then
busy_countdown <= busy_countdown - 1;
else
tcp_tx_busy <= '0';
end if;
end if;
tcp_tx_hdr_valid_last <= tcp_tx_hdr_valid;
end if;
end process;
i_buffer_count_and_checksum_data: buffer_count_and_checksum_data generic map (
min_length => 60-14-20-20
) port map (
clk => clk,
hdr_valid_in => tcp_tx_hdr_valid,
data_valid_in => tcp_tx_data_valid,
data_in => tcp_tx_data,
data_valid_out => pre_tcp_valid,
data_out => pre_tcp_data,
data_length => data_length,
data_checksum => data_checksum);
i_tcp_add_header: tcp_add_header port map (
clk => clk,
data_valid_in => pre_tcp_valid,
data_in => pre_tcp_data,
data_valid_out => pre_ip_valid,
data_out => pre_ip_data,
data_length => data_length,
data_checksum => data_checksum,
ip_src_ip => our_ip,
ip_dst_ip => tcp_tx_dst_ip,
tcp_src_port => tcp_tx_src_port,
tcp_dst_port => tcp_tx_dst_port,
tcp_seq_num => tcp_tx_seq_num,
tcp_ack_num => tcp_tx_ack_num,
tcp_window => tcp_tx_window,
tcp_flag_urg => tcp_tx_flag_urg,
tcp_flag_ack => tcp_tx_flag_ack,
tcp_flag_psh => tcp_tx_flag_psh,
tcp_flag_rst => tcp_tx_flag_rst,
tcp_flag_syn => tcp_tx_flag_syn,
tcp_flag_fin => tcp_tx_flag_fin,
tcp_urgent_ptr => tcp_tx_urgent_ptr);
ip_data_length <= std_logic_vector(unsigned(data_length)+20);
i_ip_add_header: ip_add_header port map (
clk => clk,
data_valid_in => pre_ip_valid,
data_in => pre_ip_data,
data_valid_out => pre_header_valid,
data_out => pre_header_data,
ip_data_length => ip_data_length,
ip_protocol => x"06",
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip);
i_ethernet_add_header: ethernet_add_header port map (
clk => clk,
data_valid_in => pre_header_valid,
data_in => pre_header_data,
data_valid_out => complete_valid,
data_out => complete_data,
ether_type => x"0800",
ether_dst_mac => tx_dst_mac,
ether_src_mac => our_mac);
i_transport_commit_buffer: transport_commit_buffer port map (
clk => clk,
data_valid_in => complete_valid,
data_in => complete_data,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
end Behavioral; |
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
-- File: dyplo_user_logic_stub.vhd
--
-- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED.
--
-- This file contains confidential and proprietary information of
-- Topic Embedded Products B.V. and is protected under Dutch and
-- International copyright and other international intellectual property laws.
--
-- Disclaimer
--
-- This disclaimer is not a license and does not grant any rights to the
-- materials distributed herewith. Except as otherwise provided in a valid
-- license issued to you by Topic Embedded Products B.V., and to the maximum
-- extend permitted by applicable law:
--
-- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no
-- warranty, express or implied, with respect to the capability of Dyplo. All
-- warranties of any type, express or implied, including the warranties of
-- merchantability, fitness for a particular purpose and non-infringement of
-- third party rights are expressly disclaimed.
--
-- 2. Topic�s maximum total liability shall be limited to general money
-- damages in an amount not to exceed the total amount paid for in the year
-- in which the damages have occurred. Under no circumstances including
-- negligence shall Topic be liable for direct, indirect, incidental, special,
-- consequential or punitive damages, or for loss of profits, revenue, or data,
-- that are directly or indirectly related to the use of, or the inability to
-- access and use Dyplo and related services, whether in an action in contract,
-- tort, product liability, strict liability, statute or otherwise even if
-- Topic has been advised of the possibility of those damages.
--
-- This copyright notice and disclaimer must be retained as part of this file at all times.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
library dyplo_hdl_node_lib;
use dyplo_hdl_node_lib.hdl_node_package.all;
use dyplo_hdl_node_lib.hdl_node_user_params.all;
entity dyplo_user_logic_subtractor is
generic(
INPUT_STREAMS : integer := 4;
OUTPUT_STREAMS : integer := 4
);
port(
-- Processor bus interface
dab_clk : in std_logic;
dab_rst : in std_logic;
dab_addr : in std_logic_vector(15 DOWNTO 0);
dab_sel : in std_logic;
dab_wvalid : in std_logic;
dab_rvalid : in std_logic;
dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0);
-- Streaming input interfaces
cin_tdata : in cin_tdata_ul_type;
cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0);
cin_tlevel : in cin_tlevel_ul_type;
-- Streaming output interfaces
cout_tdata : out cout_tdata_ul_type;
cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0);
-- Clock signals
user_clocks : in std_logic_vector(3 downto 0)
);
end dyplo_user_logic_subtractor;
architecture rtl of dyplo_user_logic_subtractor is
type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0);
signal value_to_subtract : signed_matrix_4x32;
signal cin_tdata_i : signed_matrix_4x32;
signal cout_tdata_i : signed_matrix_4x32;
begin
config_reg : process (dab_clk)
variable index : integer;
begin
if rising_edge(dab_clk) then
if (dab_rst = '1') then
value_to_subtract <= (others => (others => '0'));
else
index := to_integer(unsigned(dab_addr(3 downto 2)));
if (dab_sel = '1') and (dab_wvalid = '1') then
value_to_subtract(index) <= signed(dab_wdata);
end if;
dab_rdata <= std_logic_vector(value_to_subtract(index));
end if;
end if;
end process config_reg;
subtractors : for i in 0 to 3 generate
type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH);
signal sm_calc : sm_calc_states;
signal tdata : signed(31 downto 0);
begin
calc_data : process (dab_clk)
begin
if rising_edge(dab_clk) then
if (dab_rst = '1') then
cout_tdata_i(i) <= (others => '0');
cout_tvalid(i) <= '0';
cin_tready(i) <= '0';
sm_calc <= S_FETCH;
tdata <= (others => '0');
else
case sm_calc is
when S_FETCH =>
if (cin_tvalid(i) = '1') and (conv_integer(cin_tlevel(i)) /= 0) then
cin_tready(i) <= '1';
tdata <= to_signed(conv_integer(cin_tdata(i)),32);
sm_calc <= S_CALC;
end if;
when S_CALC =>
cin_tready(i) <= '0';
cout_tdata_i(i) <= tdata - value_to_subtract(i);
cout_tvalid(i) <= '1';
sm_calc <= S_SEND;
when S_SEND =>
if (cout_tready(i) = '1') then
cout_tvalid(i) <= '0';
sm_calc <= S_FINISH;
end if;
when S_FINISH =>
sm_calc <= S_FETCH;
end case;
end if;
end if;
end process calc_data;
end generate subtractors;
cout_tdata(0) <= std_logic_vector(cout_tdata_i(0));
cout_tdata(1) <= std_logic_vector(cout_tdata_i(1));
cout_tdata(2) <= std_logic_vector(cout_tdata_i(2));
cout_tdata(3) <= std_logic_vector(cout_tdata_i(3));
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1395.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p05n02i01395ent IS
END c08s05b00x00p05n02i01395ent;
ARCHITECTURE c08s05b00x00p05n02i01395arch OF c08s05b00x00p05n02i01395ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of integer;
variable XC1, XC2 : A1;
BEGIN
XC1 := (1 => 1, 2 => 2);
(XC2(1), XC2(1)):= A1'(XC1);
assert FALSE
report "***FAILED TEST: c08s05b00x00p05n02i01395 - The same element is being assigned a value by more than one association."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p05n02i01395arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1395.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p05n02i01395ent IS
END c08s05b00x00p05n02i01395ent;
ARCHITECTURE c08s05b00x00p05n02i01395arch OF c08s05b00x00p05n02i01395ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of integer;
variable XC1, XC2 : A1;
BEGIN
XC1 := (1 => 1, 2 => 2);
(XC2(1), XC2(1)):= A1'(XC1);
assert FALSE
report "***FAILED TEST: c08s05b00x00p05n02i01395 - The same element is being assigned a value by more than one association."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p05n02i01395arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1395.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p05n02i01395ent IS
END c08s05b00x00p05n02i01395ent;
ARCHITECTURE c08s05b00x00p05n02i01395arch OF c08s05b00x00p05n02i01395ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of integer;
variable XC1, XC2 : A1;
BEGIN
XC1 := (1 => 1, 2 => 2);
(XC2(1), XC2(1)):= A1'(XC1);
assert FALSE
report "***FAILED TEST: c08s05b00x00p05n02i01395 - The same element is being assigned a value by more than one association."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p05n02i01395arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:15 11/22/2013
-- Design Name:
-- Module Name: PC_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC_Register is
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_OR_NOT : in STD_LOGIC := WRITE_PC_YES;
CLK : in STD_LOGIC);
end PC_Register;
architecture Behavioral of PC_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
-- update pc value at up edge
if (WRITE_OR_NOT = WRITE_PC_YES) then
PC_OUT <= PC_IN;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:19:15 11/22/2013
-- Design Name:
-- Module Name: PC_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC_Register is
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO;
WRITE_OR_NOT : in STD_LOGIC := WRITE_PC_YES;
CLK : in STD_LOGIC);
end PC_Register;
architecture Behavioral of PC_Register is
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
-- update pc value at up edge
if (WRITE_OR_NOT = WRITE_PC_YES) then
PC_OUT <= PC_IN;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:39:23 11/19/2013
-- Design Name:
-- Module Name: My_16bitMult_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_16bitMult_948282 is
Port ( A_inputM : in STD_LOGIC_VECTOR (15 downto 0);
B_inputM : in STD_LOGIC_VECTOR (15 downto 0);
Hi_out : out STD_LOGIC_VECTOR (15 downto 0);
Lo_out : out STD_LOGIC_VECTOR (15 downto 0));
end My_16bitMult_948282;
architecture Behavioral of My_16bitMult_948282 is
component My_16bitAdder_948282 is
Port ( A_input : in STD_LOGIC_VECTOR (15 downto 0);
B_input : in STD_LOGIC_VECTOR (15 downto 0);
Sum_out : out STD_LOGIC_VECTOR (15 downto 0);
Carry_in : in STD_LOGIC;
Carry_out : out STD_LOGIC);
end component;
component My_16bitAnd_948282 is
Port ( A_in_8282 : in STD_LOGIC_VECTOR (15 downto 0);
B_in_8282 : in STD_LOGIC_VECTOR (15 downto 0);
R_in_8282 : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Extend_1to16bits is
Port ( In_1bit : in STD_LOGIC;
Out_16bit : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component My_shift_948282 is
Port ( FirstBit : in STD_LOGIC;
Rest : in STD_LOGIC_VECTOR (15 downto 0);
nextIn : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15: std_logic_vector (15 downto 0);
signal sig1, sig2, sig3, sig4, sig5, sig6, sig7, sig8, sig9, sig10, sig11, sig12, sig13, sig14, sig15: std_logic_vector (15 downto 0);
signal sig16, sig17, sig18, sig19, sig20, sig21, sig22, sig23, sig24, sig25, sig26, sig27, sig28, sig29, sig30: std_logic_vector (15 downto 0);
signal sig31, sig32, sig33, sig34: std_logic_vector (15 downto 0);
signal s1, s2, s3, s4, s5, s6, s7, s8, s9,s10, s11,s12,s13,s14,s15,s16: std_logic;
signal l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15: std_logic_vector (15 downto 0);
signal sig0: std_logic;
begin
--Sign Extend
u0: Extend_1to16bits port map (In_1bit=>A_inputM(0), Out_16bit=>i0);
u1: Extend_1to16bits port map (In_1bit=>A_inputM(1), Out_16bit=>i1);
u2: Extend_1to16bits port map (In_1bit=>A_inputM(2), Out_16bit=>i2);
u3: Extend_1to16bits port map (In_1bit=>A_inputM(3), Out_16bit=>i3);
u4: Extend_1to16bits port map (In_1bit=>A_inputM(4), Out_16bit=>i4);
u5: Extend_1to16bits port map (In_1bit=>A_inputM(5), Out_16bit=>i5);
u6: Extend_1to16bits port map (In_1bit=>A_inputM(6), Out_16bit=>i6);
u7: Extend_1to16bits port map (In_1bit=>A_inputM(7), Out_16bit=>i7);
u8: Extend_1to16bits port map (In_1bit=>A_inputM(8), Out_16bit=>i8);
u9: Extend_1to16bits port map (In_1bit=>A_inputM(9), Out_16bit=>i9);
u10: Extend_1to16bits port map (In_1bit=>A_inputM(10), Out_16bit=>i10);
u11: Extend_1to16bits port map (In_1bit=>A_inputM(11), Out_16bit=>i11);
u12: Extend_1to16bits port map (In_1bit=>A_inputM(12), Out_16bit=>i12);
u13: Extend_1to16bits port map (In_1bit=>A_inputM(13), Out_16bit=>i13);
u14: Extend_1to16bits port map (In_1bit=>A_inputM(14), Out_16bit=>i14);
u15: Extend_1to16bits port map (In_1bit=>A_inputM(15), Out_16bit=>i15);
--p0: sig0<='0';
--Mult i0
u16: My_16bitAnd_948282 port map (A_in_8282=>i0, B_in_8282=>B_inputM, R_in_8282=>sig1); --sig34 in 1st adder
u17: Lo_out(0)<=sig1(0);
instr: My_shift_948282 port map (FirstBit=>'0', Rest=>sig1, nextIn=>sig34);--sig3 in 2nd adder
u18: My_16bitAnd_948282 port map (A_in_8282=>i1, B_in_8282=>B_inputM, R_in_8282=>sig2); --sig2 in 1st adder
--1st Adder
u19: My_16bitAdder_948282 port map (A_input=>sig34, B_input=>sig2, Carry_in=>'0', Carry_out=>s1, Sum_out=>l1); --l1 in shift + s1 in front of l1
u20: Lo_out(1)<=l1(0);
u21: My_shift_948282 port map (FirstBit=>s1, Rest=>l1, nextIn=>sig3);--sig3 in 2nd adder
u22: My_16bitAnd_948282 port map (A_in_8282=>i2, B_in_8282=>B_inputM, R_in_8282=>sig4); --sig4 in 2nd adder
--2nd Adder
u23: My_16bitAdder_948282 port map (A_input=>sig3, B_input=>sig4, Carry_in=>'0', Carry_out=>s2, Sum_out=>l2); --l2 in shift + s2 in front of l2
u24: Lo_out(2)<=l2(0);
u25: My_shift_948282 port map (FirstBit=>s2, Rest=>l2, nextIn=>sig5);--sig5 in 3rd adder
u26: My_16bitAnd_948282 port map (A_in_8282=>i3, B_in_8282=>B_inputM, R_in_8282=>sig6); --sig5 in 3rd adder
--3rd Adder
u27: My_16bitAdder_948282 port map (A_input=>sig4, B_input=>sig5, Carry_in=>'0', Carry_out=>s3, Sum_out=>l3); --l3 in shift + s3 in front of l3
u28: Lo_out(3)<=l3(0);
u29: My_shift_948282 port map (FirstBit=>s3, Rest=>l3, nextIn=>sig7);--sig7 in 4th adder
u30: My_16bitAnd_948282 port map (A_in_8282=>i4, B_in_8282=>B_inputM, R_in_8282=>sig8); --sig8 in 4th adder
--4th Adder
u31: My_16bitAdder_948282 port map (A_input=>sig7, B_input=>sig8, Carry_in=>'0', Carry_out=>s4, Sum_out=>l4); --l4 in shift + s4 in front of l4
u32: Lo_out(4)<=l4(0);
u33: My_shift_948282 port map (FirstBit=>s4, Rest=>l4, nextIn=>sig9);--sig9 in 5th adder
u34: My_16bitAnd_948282 port map (A_in_8282=>i5, B_in_8282=>B_inputM, R_in_8282=>sig10); --sig10 in 5th adder
--5th Adder
u35: My_16bitAdder_948282 port map (A_input=>sig9, B_input=>sig10, Carry_in=>'0', Carry_out=>s5, Sum_out=>l5); --l5 in shift + s5 in front of l5
u36: Lo_out(5)<=l5(0);
u37: My_shift_948282 port map (FirstBit=>s5, Rest=>l5, nextIn=>sig11);--sig11 in 6th adder
u38: My_16bitAnd_948282 port map (A_in_8282=>i6, B_in_8282=>B_inputM, R_in_8282=>sig12); --sig12 in 6th adder
--6th Adder
u39: My_16bitAdder_948282 port map (A_input=>sig11, B_input=>sig12, Carry_in=>'0', Carry_out=>s6, Sum_out=>l6); --l5 in shift + s5 in front of l5
u40: Lo_out(6)<=l6(0);
u41: My_shift_948282 port map (FirstBit=>s6, Rest=>l6, nextIn=>sig13);--sig13 in 7th adder
u42: My_16bitAnd_948282 port map (A_in_8282=>i7, B_in_8282=>B_inputM, R_in_8282=>sig14); --sig14 in 7th adder
--7th Adder
u43: My_16bitAdder_948282 port map (A_input=>sig13, B_input=>sig14, Carry_in=>'0', Carry_out=>s7, Sum_out=>l7); --l5 in shift + s5 in front of l5
u44: Lo_out(7)<=l7(0);
u45: My_shift_948282 port map (FirstBit=>s7, Rest=>l7, nextIn=>sig15);--sig15 in 8th adder
u46: My_16bitAnd_948282 port map (A_in_8282=>i8, B_in_8282=>B_inputM, R_in_8282=>sig16); --sig16 in 8th adder
--8th Adder
u47: My_16bitAdder_948282 port map (A_input=>sig15, B_input=>sig16, Carry_in=>'0', Carry_out=>s8, Sum_out=>l8); --l5 in shift + s5 in front of l5
u48: Lo_out(8)<=l8(0);
u49: My_shift_948282 port map (FirstBit=>s8, Rest=>l8, nextIn=>sig17);--sig17 in 9th adder
u50: My_16bitAnd_948282 port map (A_in_8282=>i9, B_in_8282=>B_inputM, R_in_8282=>sig18); --sig18 in 9th adder
--9th Adder
u51: My_16bitAdder_948282 port map (A_input=>sig17, B_input=>sig18, Carry_in=>'0', Carry_out=>s9, Sum_out=>l9); --l5 in shift + s5 in front of l5
u52: Lo_out(9)<=l9(0);
u53: My_shift_948282 port map (FirstBit=>s9, Rest=>l9, nextIn=>sig19);--sig19 in 10th adder
u54: My_16bitAnd_948282 port map (A_in_8282=>i10, B_in_8282=>B_inputM, R_in_8282=>sig20); --sig20 in 10th adder
--10th Adder
u55: My_16bitAdder_948282 port map (A_input=>sig19, B_input=>sig20, Carry_in=>'0', Carry_out=>s10, Sum_out=>l10); --l5 in shift + s5 in front of l5
u56: Lo_out(10)<=l10(0);
u57: My_shift_948282 port map (FirstBit=>s10, Rest=>l10, nextIn=>sig21);--sig21 in 11th adder
u58: My_16bitAnd_948282 port map (A_in_8282=>i11, B_in_8282=>B_inputM, R_in_8282=>sig22); --sig22 in 11th adder
--11th Adder
u59: My_16bitAdder_948282 port map (A_input=>sig21, B_input=>sig22, Carry_in=>'0', Carry_out=>s11, Sum_out=>l11); --l5 in shift + s5 in front of l5
u60: Lo_out(11)<=l11(0);
u61: My_shift_948282 port map (FirstBit=>s11, Rest=>l11, nextIn=>sig23);--sig23 in 12th adder
u62: My_16bitAnd_948282 port map (A_in_8282=>i12, B_in_8282=>B_inputM, R_in_8282=>sig24); --sig24 in 12th adder
--12th Adder
u63: My_16bitAdder_948282 port map (A_input=>sig23, B_input=>sig24, Carry_in=>'0', Carry_out=>s12, Sum_out=>l12); --l5 in shift + s5 in front of l5
u64: Lo_out(12)<=l12(0);
u65: My_shift_948282 port map (FirstBit=>s12, Rest=>l12, nextIn=>sig25);--sig25 in 13th adder
u66: My_16bitAnd_948282 port map (A_in_8282=>i13, B_in_8282=>B_inputM, R_in_8282=>sig26); --sig26 in 13th adder
--13th Adder
u67: My_16bitAdder_948282 port map (A_input=>sig25, B_input=>sig26, Carry_in=>'0', Carry_out=>s13, Sum_out=>l13); --l5 in shift + s5 in front of l5
u68: Lo_out(13)<=l13(0);
u69: My_shift_948282 port map (FirstBit=>s13, Rest=>l13, nextIn=>sig27);--sig27 in 14th adder
u70: My_16bitAnd_948282 port map (A_in_8282=>i14, B_in_8282=>B_inputM, R_in_8282=>sig28); --sig28 in 14th adder
--14th Adder
u71: My_16bitAdder_948282 port map (A_input=>sig27, B_input=>sig28, Carry_in=>'0', Carry_out=>s14, Sum_out=>l14); --l5 in shift + s5 in front of l5
u72: Lo_out(14)<=l14(0);
u73: My_shift_948282 port map (FirstBit=>s14, Rest=>l14, nextIn=>sig29);--sig29 in 15th adder
u74: My_16bitAnd_948282 port map (A_in_8282=>i15, B_in_8282=>B_inputM, R_in_8282=>sig30); --sig30 in 15th adder
--15th Adder
u75: My_16bitAdder_948282 port map (A_input=>sig29, B_input=>sig30, Carry_in=>'0', Carry_out=>s15, Sum_out=>l15); --l5 in shift + s5 in front of l5
u76: Lo_out(15)<=l15(0);
u77: My_shift_948282 port map (FirstBit=>s15, Rest=>l15, nextIn=>sig31);--sig31 in hi
u78: Hi_out<=sig31;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000101000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GN4GVGE46N is
Begin
-- Constant
output <= "0000000101000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000101000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GN4GVGE46N is
Begin
-- Constant
output <= "0000000101000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN4GVGE46N is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000101000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GN4GVGE46N is
Begin
-- Constant
output <= "0000000101000000";
end architecture; |
-- VHDL Entity R6502_TC.Reg_PC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:48 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg_PC IS
PORT(
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic;
sel_pc_in_i : IN std_logic;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END Reg_PC ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:49 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF Reg_PC IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ci_o_i : std_logic;
SIGNAL cout_pc_o_i : std_logic;
SIGNAL load3_o_i : std_logic;
SIGNAL load_o_i : std_logic;
SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);
BEGIN
-- ModuleWare code(v1.9) for instance 'U_2' of 'add'
u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_low_o_i;
temp_din1 := '0' & val_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
cout_pc_o_i <= temp_sum(8) ;
END PROCESS u_2combo_proc;
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_high_o_i;
temp_din1 := '0' & offset_high_o_i;
temp_carry := ci_o_i;
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
END PROCESS u_11combo_proc;
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_0reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1') THEN
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_4reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load3_o_i = '1') THEN
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
END IF;
END IF;
END PROCESS u_4seq_proc;
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i AND ld_i(0);
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i AND ld_i(1);
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i AND ld_pc_i;
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
BEGIN
CASE sel_pc_in_i IS
WHEN '0' => adr_pc_o_i <= adr_pc_o_internal;
WHEN '1' => adr_pc_o_i <= adr_i;
WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
BEGIN
CASE sel_pc_val_i IS
WHEN "00" => val_o_i <= val_one;
WHEN "01" => val_o_i <= val_zero;
WHEN "10" => val_o_i <= offset_low_o_i;
WHEN "11" => val_o_i <= val_zero;
WHEN OTHERS => val_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_13combo_proc;
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
mw_U_3temp_din <= adr_pc_o_i;
u_3combo_proc: PROCESS (mw_U_3temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_3temp_din(15 DOWNTO 0);
adr_pc_low_o_i <= temp_din(7 DOWNTO 0);
adr_pc_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_3combo_proc;
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
mw_U_5temp_din <= offset_i;
u_5combo_proc: PROCESS (mw_U_5temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_5temp_din(15 DOWNTO 0);
offset_low_o_i <= temp_din(7 DOWNTO 0);
offset_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_5combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
adr_pc_o <= adr_pc_o_internal;
END struct;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00592
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (15)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00592)
-- ENT00592_Test_Bench(ARCH00592_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00592 of E00000 is
begin
process
procedure p1 is
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
alias av_boolean_1 : a_boolean
is va_boolean_1 ;
alias av_bit_1 : a_bit
is va_bit_1 ;
alias av_severity_level_1 : a_severity_level
is va_severity_level_1 ;
alias av_character_1 : a_character
is va_character_1 ;
alias av_t_enum1_1 : a_t_enum1
is va_t_enum1_1 ;
alias av_st_enum1_1 : a_st_enum1
is va_st_enum1_1 ;
alias av_integer_1 : a_integer
is va_integer_1 ;
alias av_t_int1_1 : a_t_int1
is va_t_int1_1 ;
alias av_st_int1_1 : a_st_int1
is va_st_int1_1 ;
alias av_time_1 : a_time
is va_time_1 ;
alias av_t_phys1_1 : a_t_phys1
is va_t_phys1_1 ;
alias av_st_phys1_1 : a_st_phys1
is va_st_phys1_1 ;
alias av_real_1 : a_real
is va_real_1 ;
alias av_t_real1_1 : a_t_real1
is va_t_real1_1 ;
alias av_st_real1_1 : a_st_real1
is va_st_real1_1 ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
alias av_bit_vector_1 : a_bit_vector
is va_bit_vector_1 ;
alias av_string_1 : a_string
is va_string_1 ;
alias av_t_rec1_1 : a_t_rec1
is va_t_rec1_1 ;
alias av_st_rec1_1 : a_st_rec1
is va_st_rec1_1 ;
alias av_t_rec2_1 : a_t_rec2
is va_t_rec2_1 ;
alias av_st_rec2_1 : a_st_rec2
is va_st_rec2_1 ;
alias av_t_rec3_1 : a_t_rec3
is va_t_rec3_1 ;
alias av_st_rec3_1 : a_st_rec3
is va_st_rec3_1 ;
alias av_t_arr1_1 : a_t_arr1
is va_t_arr1_1 ;
alias av_st_arr1_1 : a_st_arr1
is va_st_arr1_1 ;
alias av_t_arr2_1 : a_t_arr2
is va_t_arr2_1 ;
alias av_st_arr2_1 : a_st_arr2
is va_st_arr2_1 ;
alias av_t_arr3_1 : a_t_arr3
is va_t_arr3_1 ;
alias av_st_arr3_1 : a_st_arr3
is va_st_arr3_1 ;
begin
-- test that variables denote same object
av_boolean_1 := new boolean'(c_boolean_1) ;
av_bit_1 := new bit'(c_bit_1) ;
av_severity_level_1 := new severity_level'(c_severity_level_1) ;
av_character_1 := new character'(c_character_1) ;
av_t_enum1_1 := new t_enum1'(c_t_enum1_1) ;
av_st_enum1_1 := new st_enum1'(c_st_enum1_1) ;
av_integer_1 := new integer'(c_integer_1) ;
av_t_int1_1 := new t_int1'(c_t_int1_1) ;
av_st_int1_1 := new st_int1'(c_st_int1_1) ;
av_time_1 := new time'(c_time_1) ;
av_t_phys1_1 := new t_phys1'(c_t_phys1_1) ;
av_st_phys1_1 := new st_phys1'(c_st_phys1_1) ;
av_real_1 := new real'(c_real_1) ;
av_t_real1_1 := new t_real1'(c_t_real1_1) ;
av_st_real1_1 := new st_real1'(c_st_real1_1) ;
correct := correct and av_boolean_1.all
= c_boolean_1 ;
correct := correct and av_bit_1.all
= c_bit_1 ;
correct := correct and av_severity_level_1.all
= c_severity_level_1 ;
correct := correct and av_character_1.all
= c_character_1 ;
correct := correct and av_t_enum1_1.all
= c_t_enum1_1 ;
correct := correct and av_st_enum1_1.all
= c_st_enum1_1 ;
correct := correct and av_integer_1.all
= c_integer_1 ;
correct := correct and av_t_int1_1.all
= c_t_int1_1 ;
correct := correct and av_st_int1_1.all
= c_st_int1_1 ;
correct := correct and av_time_1.all
= c_time_1 ;
correct := correct and av_t_phys1_1.all
= c_t_phys1_1 ;
correct := correct and av_st_phys1_1.all
= c_st_phys1_1 ;
correct := correct and av_real_1.all
= c_real_1 ;
correct := correct and av_t_real1_1.all
= c_t_real1_1 ;
correct := correct and av_st_real1_1.all
= c_st_real1_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00592" ,
"Variable declarations - all access subtypes" ,
correct) ;
end p1 ;
--
procedure p2 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
variable correct : boolean := true ;
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
alias av_bit_vector_1 : a_bit_vector
is va_bit_vector_1 ;
alias av_string_1 : a_string
is va_string_1 ;
alias av_t_rec1_1 : a_t_rec1
is va_t_rec1_1 ;
alias av_st_rec1_1 : a_st_rec1
is va_st_rec1_1 ;
alias av_t_rec2_1 : a_t_rec2
is va_t_rec2_1 ;
alias av_st_rec2_1 : a_st_rec2
is va_st_rec2_1 ;
alias av_t_rec3_1 : a_t_rec3
is va_t_rec3_1 ;
alias av_st_rec3_1 : a_st_rec3
is va_st_rec3_1 ;
alias av_t_arr1_1 : a_t_arr1
is va_t_arr1_1 ;
alias av_st_arr1_1 : a_st_arr1
is va_st_arr1_1 ;
alias av_t_arr2_1 : a_t_arr2
is va_t_arr2_1 ;
alias av_st_arr2_1 : a_st_arr2
is va_st_arr2_1 ;
alias av_t_arr3_1 : a_t_arr3
is va_t_arr3_1 ;
alias av_st_arr3_1 : a_st_arr3
is va_st_arr3_1 ;
begin
av_bit_vector_1 := new st_bit_vector'(c_st_bit_vector_1) ;
av_string_1 := new st_string'(c_st_string_1) ;
av_t_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_st_rec1_1 := new st_rec1'(c_st_rec1_1) ;
av_t_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_st_rec2_1 := new st_rec2'(c_st_rec2_1) ;
av_t_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_st_rec3_1 := new st_rec3'(c_st_rec3_1) ;
av_t_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_st_arr1_1 := new st_arr1'(c_st_arr1_1) ;
av_t_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_st_arr2_1 := new st_arr2'(c_st_arr2_1) ;
av_t_arr3_1 := new st_arr3'(c_st_arr3_1) ;
av_st_arr3_1 := new st_arr3'(c_st_arr3_1) ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_1 ;
correct := correct and av_string_1.all
= c_st_string_1 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_1 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_1 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_1 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_1 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_1 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_1 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_1 ;
av_bit_vector_1.all := c_st_bit_vector_2 ;
av_string_1.all := c_st_string_2 ;
av_t_rec1_1.all := c_st_rec1_2 ;
av_st_rec1_1.all := c_st_rec1_2 ;
av_t_rec2_1.all := c_st_rec2_2 ;
av_st_rec2_1.all := c_st_rec2_2 ;
av_t_rec3_1.all := c_st_rec3_2 ;
av_st_rec3_1.all := c_st_rec3_2 ;
av_t_arr1_1.all := c_st_arr1_2 ;
av_st_arr1_1.all := c_st_arr1_2 ;
av_t_arr2_1.all := c_st_arr2_2 ;
av_st_arr2_1.all := c_st_arr2_2 ;
av_t_arr3_1.all := c_st_arr3_2 ;
av_st_arr3_1.all := c_st_arr3_2 ;
correct := correct and av_bit_vector_1.all
= c_st_bit_vector_2 ;
correct := correct and av_string_1.all
= c_st_string_2 ;
correct := correct and av_t_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_st_rec1_1.all
= c_st_rec1_2 ;
correct := correct and av_t_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_st_rec2_1.all
= c_st_rec2_2 ;
correct := correct and av_t_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_st_rec3_1.all
= c_st_rec3_2 ;
correct := correct and av_t_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_st_arr1_1.all
= c_st_arr1_2 ;
correct := correct and av_t_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_st_arr2_1.all
= c_st_arr2_2 ;
correct := correct and av_t_arr3_1.all
= c_st_arr3_2 ;
correct := correct and av_st_arr3_1.all
= c_st_arr3_2 ;
test_report ( "ARCH00592" ,
"Alias declarations - composite dynamic access subtypes" ,
correct) ;
end p2 ;
begin
p1 ;
p2 ;
wait ;
end process ;
end ARCH00592 ;
--
entity ENT00592_Test_Bench is
end ENT00592_Test_Bench ;
--
architecture ARCH00592_Test_Bench of ENT00592_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00592 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00592_Test_Bench ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 106688)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 106688)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 106688)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1817.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01817ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01817ent;
ARCHITECTURE c07s01b00x00p08n01i01817arch OF c07s01b00x00p08n01i01817ent IS
signal s_int : small_int;
BEGIN
with small_int select -- type name illegal here
s_int <= 6 after 10 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01817 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1817.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01817ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01817ent;
ARCHITECTURE c07s01b00x00p08n01i01817arch OF c07s01b00x00p08n01i01817ent IS
signal s_int : small_int;
BEGIN
with small_int select -- type name illegal here
s_int <= 6 after 10 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01817 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1817.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01817ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01817ent;
ARCHITECTURE c07s01b00x00p08n01i01817arch OF c07s01b00x00p08n01i01817ent IS
signal s_int : small_int;
BEGIN
with small_int select -- type name illegal here
s_int <= 6 after 10 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01817 - Type names are not permitted as primaries in an attribute argument."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1213.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n02i01213ent IS
END c08s01b00x00p25n02i01213ent;
ARCHITECTURE c08s01b00x00p25n02i01213arch OF c08s01b00x00p25n02i01213ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
A <= '1' after 1 ns;
ShouldBeTime := NOW + 1 ns;
wait on A for 20 ns;
assert NOT(ShouldBeTime = NOW)
report "***PASSED TEST: c08s01b00x00p25n02i01213"
severity NOTE;
assert (ShouldBeTime = NOW)
report "***FAILED TEST: c08s01b00x00p25n02i01213 - When NO condition_clause is present, the condition clause 'until TRUE' is assumed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n02i01213arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1213.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n02i01213ent IS
END c08s01b00x00p25n02i01213ent;
ARCHITECTURE c08s01b00x00p25n02i01213arch OF c08s01b00x00p25n02i01213ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
A <= '1' after 1 ns;
ShouldBeTime := NOW + 1 ns;
wait on A for 20 ns;
assert NOT(ShouldBeTime = NOW)
report "***PASSED TEST: c08s01b00x00p25n02i01213"
severity NOTE;
assert (ShouldBeTime = NOW)
report "***FAILED TEST: c08s01b00x00p25n02i01213 - When NO condition_clause is present, the condition clause 'until TRUE' is assumed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n02i01213arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1213.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n02i01213ent IS
END c08s01b00x00p25n02i01213ent;
ARCHITECTURE c08s01b00x00p25n02i01213arch OF c08s01b00x00p25n02i01213ent IS
signal A : BIT;
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
A <= '1' after 1 ns;
ShouldBeTime := NOW + 1 ns;
wait on A for 20 ns;
assert NOT(ShouldBeTime = NOW)
report "***PASSED TEST: c08s01b00x00p25n02i01213"
severity NOTE;
assert (ShouldBeTime = NOW)
report "***FAILED TEST: c08s01b00x00p25n02i01213 - When NO condition_clause is present, the condition clause 'until TRUE' is assumed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n02i01213arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package types_pkg is
type endianness_type is (
little_endian,
big_endian
);
subtype void_type is std_ulogic_vector(-1 downto 0);
constant void : void_type := "";
constant log2_byte_bits : natural := 3;
constant byte_bits : natural := 2**log2_byte_bits;
subtype byte_type is std_ulogic_vector(byte_bits-1 downto 0);
type std_ulogic_vector2 is array(natural range <>, natural range <>) of std_ulogic;
type std_logic_vector2 is array(natural range <>, natural range <>) of std_logic;
type std_ulogic_vector3 is array(natural range <>, natural range <>, natural range <>) of std_ulogic;
type std_logic_vector3 is array(natural range <>, natural range <>, natural range <>) of std_logic;
pure function std_ulogic_vector2_slice1(v : std_ulogic_vector2; n : natural) return std_ulogic_vector;
pure function std_ulogic_vector2_slice2(v : std_ulogic_vector2; n : natural) return std_ulogic_vector;
pure function std_ulogic_to_character(value : in std_ulogic) return character;
pure function std_logic_to_character(value : in std_logic) return character;
pure function character_to_std_ulogic(value : in character) return std_ulogic;
pure function character_to_std_logic(value : in character) return std_logic;
pure function std_ulogic_vector_to_string(value : in std_ulogic_vector) return string;
pure function std_logic_vector_to_string(value : in std_logic_vector) return string;
pure function string_to_std_ulogic_vector(value : in string) return std_ulogic_vector;
pure function string_to_std_logic_vector(value : in string) return std_ulogic_vector;
pure function boolean_to_string(value : in boolean) return string;
pure function string_to_boolean(value : in string) return boolean;
pure function integer_to_string(value : in integer) return string;
pure function string_to_integer(value : in string) return integer;
end package;
package body types_pkg is
pure function std_ulogic_vector2_slice1(v : std_ulogic_vector2; n : natural) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range(1));
begin
for m in v'range(1) loop
ret(m) := v(m, n);
end loop;
return ret;
end function;
pure function std_ulogic_vector2_slice2(v : std_ulogic_vector2; n : natural) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range(2));
begin
for m in v'range(2) loop
ret(m) := v(n, m);
end loop;
return ret;
end function;
pure function std_ulogic_to_character(value : in std_ulogic) return character is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
end case;
end function;
pure function std_logic_to_character(value : in std_logic) return character is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
end case;
end function;
pure function character_to_std_ulogic(value : in character) return std_ulogic is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
when others =>
assert false
report "invalid std_ulogic character: " & value
severity failure;
end case;
end function;
pure function character_to_std_logic(value : in character) return std_logic is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
when others =>
assert false
report "invalid std_logic character: " & value
severity failure;
end case;
end function;
pure function std_ulogic_vector_to_string(value : in std_ulogic_vector) return string is
variable ret : string(1 to value'length);
begin
if value'ascending then
for n in value'range loop
ret(n-value'left+ret'left) := std_ulogic_to_character(value(n));
end loop;
else
for n in value'range loop
ret(value'left-n+ret'left) := std_ulogic_to_character(value(n));
end loop;
end if;
return ret;
end function;
pure function std_logic_vector_to_string(value : in std_logic_vector) return string is
variable ret : string(1 to value'length);
begin
if value'ascending then
for n in value'range loop
ret(n-value'left+ret'left) := std_logic_to_character(value(n));
end loop;
else
for n in value'range loop
ret(value'left-n+ret'left) := std_logic_to_character(value(n));
end loop;
end if;
return ret;
end function;
pure function string_to_std_ulogic_vector(value : in string) return std_ulogic_vector is
variable ret : std_ulogic_vector(value'length-1 downto 0);
begin
if not value'ascending then
for n in value'range loop
ret(n-value'right+ret'right) := character_to_std_ulogic(value(n));
end loop;
else
for n in value'range loop
ret(value'right-n+ret'right) := character_to_std_ulogic(value(n));
end loop;
end if;
return ret;
end function;
pure function string_to_std_logic_vector(value : in string) return std_ulogic_vector is
variable ret : std_ulogic_vector(value'length-1 downto 0);
begin
if not value'ascending then
for n in value'range loop
ret(n-value'right+ret'right) := character_to_std_logic(value(n));
end loop;
else
for n in value'range loop
ret(value'right-n+ret'right) := character_to_std_logic(value(n));
end loop;
end if;
return ret;
end function;
pure function boolean_to_string(value : in boolean) return string is
begin
if value then
return "true";
else
return "false";
end if;
end function;
pure function string_to_boolean(value : in string) return boolean is
begin
if value = "true" then
return true;
elsif value = "false" then
return false;
else
assert false
report "invalid boolean string: " & value
severity failure;
end if;
end function;
pure function integer_to_string(value : in integer) return string is
begin
return integer'image(value);
end function;
pure function string_to_integer(value : in string) return integer is
variable ret : integer;
begin
ret := 0;
for n in value'left to value'right loop
ret := ret * 10;
case value(n) is
when '0' => ret := ret + 0;
when '1' => ret := ret + 1;
when '2' => ret := ret + 2;
when '3' => ret := ret + 3;
when '4' => ret := ret + 4;
when '5' => ret := ret + 5;
when '6' => ret := ret + 6;
when '7' => ret := ret + 7;
when '8' => ret := ret + 8;
when '9' => ret := ret + 9;
when others =>
report "invalid integer string: " & value
severity failure;
end case;
end loop;
return ret;
end function;
end package body;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem1.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 65536,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 16,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem1.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 65536,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 16,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "video_mem1.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 65536,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 16,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "video_mem1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "video_mem1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_forward_buckets_if is
component nfa_forward_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_forward_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_forward_buckets_if_plb_master_if: component nfa_forward_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_forward_buckets_if_rd_data_user_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 32;
USER_DATA_WIDTH_2N : integer := 32;
USER_ADDR_SHIFT : integer := 2; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_forward_buckets_if is
component nfa_forward_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component nfa_forward_buckets_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto USER_ADDR_SHIFT) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH - USER_ADDR_SHIFT -1) + USER_address(31 -USER_ADDR_SHIFT downto 0);
user_phy_address(USER_ADDR_SHIFT-1 downto 0) <= REMOTE_DESTINATION_ADDRESS(C_PLB_AWIDTH - USER_ADDR_SHIFT to C_PLB_AWIDTH -1);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_nfa_forward_buckets_if_req_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize(31 downto USER_ADDR_SHIFT) <= req_fifo_dout_req_size(31-USER_ADDR_SHIFT downto 0);
req_fifo_dout_req_size_normalize(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_nfa_forward_buckets_if_plb_master_if: component nfa_forward_buckets_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_nfa_forward_buckets_if_rsp_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_nfa_forward_buckets_if_rd_data_user_fifo: component nfa_forward_buckets_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01646ent IS
END c08s13b00x00p03n01i01646ent;
ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if TRUE then
k := 5;
NULL;
elsif FALSE then
k := 5;
NULL;
end if;
assert NOT(k = 5)
report "***PASSED TEST: c08s13b00x00p03n01i01646"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01646arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01646ent IS
END c08s13b00x00p03n01i01646ent;
ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if TRUE then
k := 5;
NULL;
elsif FALSE then
k := 5;
NULL;
end if;
assert NOT(k = 5)
report "***PASSED TEST: c08s13b00x00p03n01i01646"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01646arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01646ent IS
END c08s13b00x00p03n01i01646ent;
ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if TRUE then
k := 5;
NULL;
elsif FALSE then
k := 5;
NULL;
end if;
assert NOT(k = 5)
report "***PASSED TEST: c08s13b00x00p03n01i01646"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01646arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end entity deblocking_filter_node;
architecture fsmd of deblocking_filter_node is
component h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end component h264_deblock_filter_core;
component priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--signals
signal is_chroma : std_logic;
signal boundary_strength : std_logic_vector(8 downto 0);
signal p0 : std_logic_vector(8 downto 0);
signal p1 : std_logic_vector(8 downto 0);
signal p2 : std_logic_vector(8 downto 0);
signal p3 : std_logic_vector(8 downto 0);
signal q0 : std_logic_vector(8 downto 0);
signal q1 : std_logic_vector(8 downto 0);
signal q2 : std_logic_vector(8 downto 0);
signal q3 : std_logic_vector(8 downto 0);
signal alpha : std_logic_vector(8 downto 0);
signal beta : std_logic_vector(8 downto 0);
signal tc0 : std_logic_vector(8 downto 0);
signal bS : std_logic_vector(8 downto 0);
signal p0_out : signed(8 downto 0);
signal p1_out : signed(8 downto 0);
signal p2_out : signed(8 downto 0);
signal q0_out : signed(8 downto 0);
signal q1_out : signed(8 downto 0);
signal q2_out : signed(8 downto 0);
signal p0_out_vector : std_logic_vector(8 downto 0);
signal p1_out_vector : std_logic_vector(8 downto 0);
signal p2_out_vector : std_logic_vector(8 downto 0);
signal q0_out_vector : std_logic_vector(8 downto 0);
signal q1_out_vector : std_logic_vector(8 downto 0);
signal q2_out_vector : std_logic_vector(8 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal has_rxd_q, has_rxd_d : std_logic;
signal recv_packet_q : std_logic_vector(127 downto 0);
signal recv_packet_d : std_logic_vector(127 downto 0);
signal send_data_0 : std_logic_vector(63 downto 0);
signal send_data_1 : std_logic_vector(63 downto 0);
--constants
constant p_index : integer := 96;
constant q_index : integer := 64;
constant param_index : integer := 32;
constant sys_param_index : integer := 0;
--states
type db_filter_states is (idle, select_vc, rx_0, rx_1, wait_rx_0, tx_0, tx_1, dequeue_0, dequeue_1, wait_tx_0, wait_tx_1);
signal next_state, current_state : db_filter_states;
begin
---------------------------------------------------------------------------
-- DATAPATH
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
recv_packet_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
recv_packet_q <= recv_packet_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
recv_packet_d(63 downto 0) <= recv_data when current_state = rx_0 else recv_packet_q(63 downto 0);
recv_packet_d(127 downto 64) <= recv_data when current_state = rx_1 else recv_packet_q(127 downto 64);
selected_vc_d <= selected_vc_enc when current_state = select_vc else selected_vc_q;
selected_vc_one_hot <= "01" when selected_vc_q = "0" else "10";
--parse input
p3( 7 downto 0 ) <= (recv_packet_q( p_index + 31 downto p_index + 24));
p2( 7 downto 0 ) <= (recv_packet_q( p_index + 23 downto p_index + 16));
p1( 7 downto 0 ) <= (recv_packet_q( p_index + 15 downto p_index + 8));
p0( 7 downto 0 ) <= (recv_packet_q( p_index + 7 downto p_index + 0));
q3( 7 downto 0 ) <= (recv_packet_q( q_index + 31 downto q_index + 24));
q2( 7 downto 0 ) <= (recv_packet_q( q_index + 23 downto q_index + 16));
q1( 7 downto 0 ) <= (recv_packet_q( q_index + 15 downto q_index + 8));
q0( 7 downto 0 ) <= (recv_packet_q( q_index + 7 downto q_index + 0));
alpha( 7 downto 0 ) <= (recv_packet_q( param_index + 31 downto param_index + 24));
beta( 7 downto 0 ) <= (recv_packet_q( param_index + 23 downto param_index + 16));
bS( 7 downto 0 ) <= (recv_packet_q( param_index + 15 downto param_index + 8 ));
tc0( 7 downto 0 ) <= (recv_packet_q( param_index + 7 downto param_index + 0 ));
p3( 8 ) <= '0';
p2( 8 ) <= '0';
p1( 8 ) <= '0';
p0( 8 ) <= '0';
q3( 8 ) <= '0';
q2( 8 ) <= '0';
q1( 8 ) <= '0';
q0( 8 ) <= '0';
alpha( 8 ) <= '0';
beta( 8 ) <= '0';
bS( 8 ) <= '0';
tc0( 8 ) <= '0';
is_chroma <= recv_packet_q( sys_param_index + 16 );
identifier <= recv_packet_q( sys_param_index + 15 downto sys_param_index + 8 );
--form response
p0_out_vector <= std_logic_vector(p0_out);
p1_out_vector <= std_logic_vector(p1_out);
p2_out_vector <= std_logic_vector(p2_out);
q0_out_vector <= std_logic_vector(q0_out);
q1_out_vector <= std_logic_vector(q1_out);
q2_out_vector <= std_logic_vector(q2_out);
send_data_1 <= p3(7 downto 0) &
p2_out_vector(7 downto 0) &
p1_out_vector(7 downto 0) &
p0_out_vector(7 downto 0) &
q3(7 downto 0) &
q2_out_vector(7 downto 0) &
q1_out_vector(7 downto 0) &
q0_out_vector(7 downto 0);
send_data_0 <= X"00000000" &
x"000000" &
identifier;
send_data <= send_data_0 when current_state = wait_tx_0 or current_state = dequeue_1 or current_state = tx_0 else
send_data_1;
--network controls
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
select_vc_read <= selected_vc_q;
set_tail_flit <= '1' when current_state = wait_tx_1 or current_state = tx_1 else '0';
send_flit <= '1' when current_state = tx_0 or current_state = tx_1 else '0';
dequeue <= selected_vc_one_hot when current_state = dequeue_0 or current_state = dequeue_1 else "00";
-- filter core
u0: component h264_deblock_filter_core port map(
clk => '0',
rst => '0',
is_chroma => is_chroma,
boundary_strength => signed( bs ),
p0 => signed( p0 ),
p1 => signed( p1 ),
p2 => signed( p2 ),
p3 => signed( p3 ),
q0 => signed( q0 ),
q1 => signed( q1 ),
q2 => signed( q2 ),
q3 => signed( q3 ),
alpha => signed( alpha ),
beta => signed( beta ),
tc0 => signed( tc0 ),
p0_out => p0_out,
p1_out => p1_out,
p2_out => p2_out,
q0_out => q0_out,
q1_out => q1_out,
q2_out => q2_out
);
-- select which bufer to read from
u1: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_enc);
---------------------------------------------------------------------------
-- STATE MACHINE
---------------------------------------------------------------------------
--state register
process(clk, rst) begin
if rst = '1' then
current_state <= idle;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
--update logic
process(current_state, data_in_buffer, ready_to_send) begin
--default
next_state <= current_state;
if current_state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= select_vc;
end if;
if current_state = select_vc then
next_state <= rx_0;
end if;
if current_state = rx_0 then
next_state <= dequeue_0;
end if;
if current_state = dequeue_0 then
next_state <= wait_rx_0;
end if;
if current_state = wait_rx_0 and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_state <= rx_1;
end if;
if current_state = rx_1 then
next_state <= dequeue_1;
end if;
if current_state = dequeue_1 then
next_state <= wait_tx_0;
end if;
if current_state = wait_tx_0 and ready_to_send = '1' then
next_state <= tx_0;
end if;
if current_state = tx_0 then
next_state <= wait_tx_1;
end if;
if current_state = wait_tx_1 and ready_to_send = '1' then
next_state <= tx_1;
end if;
if current_state = tx_1 then
next_state <= idle;
end if;
end process;
---------------------------------------------------------------------------
-- rx tester
---------------------------------------------------------------------------
--process(clk, rst) begin
-- if rst = '1' then
-- has_rxd_q <= '0';
-- elsif rising_edge(clk) then
-- has_rxd_q <= has_rxd_d;
-- end if;
--end process;
--has_rxd_d <= has_rxd_q or or_reduce(data_in_buffer);
----has_rxd <= or_reduce(data_in_buffer);--has_rxd_d;
----
----is_idle <= '1' when current_state = idle else '0';
----is_filtering <= '1' when current_state = filter else '0';
----is_tx_ing <= '1' when current_state = transmit else '0';
----is_cleanup_ing <= '1' when current_state = cleanup else '0';
----
----rx_non_zero <= or_reduce(recv_data);
----tx_non_zero <= or_reduce(
---- p3(7 downto 0) &
---- p2_out_vector(7 downto 0) &
---- p1_out_vector(7 downto 0) &
---- p0_out_vector(7 downto 0) &
---- q3(7 downto 0) &
---- q2_out_vector(7 downto 0) &
---- q1_out_vector(7 downto 0) &
---- q0_out_vector(7 downto 0) &
---- X"00000000" &
---- x"000000" &
---- identifier );
----
end architecture fsmd;
|
-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2007-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: xlib
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
-- 2008-05-23 149 1.0.4 add iob_io(_gen)
-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package xlib is
component iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end component;
component iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_io is -- registered IOB, in/output
generic (
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_io is -- un-registered IOB, in/output
generic (
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_oddr2_simple is -- DDR2 output I/O pad
generic (
ALIGN : string := "NONE"; -- ddr_alignment
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO0 : in slbit; -- output data
DO1 : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_io_gen is -- un-registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_keeper is -- keeper for IOB
port (
PAD : inout slbit -- i/o pad
);
end component;
component iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
end package xlib;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block3
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_1_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_9_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_9_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_9_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_10_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_10_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_9_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block3 IS
-- Signals
SIGNAL twdlXdin_9_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_9_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_10_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_10_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_9_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_9_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_10_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_10_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
BEGIN
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
twdlXdin_10_re_signed <= signed(twdlXdin_10_re);
twdlXdin_10_im_signed <= signed(twdlXdin_10_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_9_re_signed,
twdlXdin_9_im_signed, twdlXdin_10_re_signed, twdlXdin_10_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(17 DOWNTO 0);
VARIABLE add_cast_0 : signed(17 DOWNTO 0);
VARIABLE sub_cast : signed(17 DOWNTO 0);
VARIABLE sub_cast_0 : signed(17 DOWNTO 0);
VARIABLE add_cast_1 : signed(17 DOWNTO 0);
VARIABLE add_cast_2 : signed(17 DOWNTO 0);
VARIABLE sub_cast_1 : signed(17 DOWNTO 0);
VARIABLE sub_cast_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_9_re_signed, 18);
add_cast_0 := resize(twdlXdin_10_re_signed, 18);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_9_re_signed, 18);
sub_cast_0 := resize(twdlXdin_10_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_9_im_signed, 18);
add_cast_2 := resize(twdlXdin_10_im_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_9_im_signed, 18);
sub_cast_2 := resize(twdlXdin_10_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_9_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(16 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(16 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(16 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(16 DOWNTO 0);
dout_9_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re <= std_logic_vector(dout_10_re_tmp);
dout_10_im <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email : [email protected]
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 12/2006 : 0.1 Initial revision
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
--
-- Copyright (c) 2006 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software ; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation ; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY ; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http ://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- Uncomment the following with VHDL-2008 package generics.
-- For now they are defined in the package RandomBasePkg.vhd
-- package RandomGenericPkg is
-- generic (
-- type RandomSeedType ; -- base type for randomization
-- procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- function GenRandSeed(IV : integer_vector) return RandomSeedType ;
-- function GenRandSeed(I : integer) return RandomSeedType ;
-- function GenRandSeed(S : string) return RandomSeedType ;
-- ) ;
-- make things from SortListPkg_int visible
alias sort is work.SortListPkg_int.sort[integer_vector return integer_vector] ;
alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Parameters for randomization
-- RandomDistType specifies the distribution to use for randomize
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomParmType ) ;
type RandomPType is protected
-- Seed Manipulation
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure InitSeed (IV : integer_vector ) ;
-- SetSeed & GetSeed : Used to save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
-- SeedRandom = SetSeed & GetSeed for SV compatibility
-- replace with aliases when they work in popular simulators
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
-- Setting Randomization Parameters
-- Allows RandInt to have distributions other than uniform
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
-- Base Randomization Distributions
-- Uniform : Generate a random number with a Uniform distribution
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- Normal : Generate a random number with a normal distribution
impure function Normal (Mean, StdDeviation : real) return real ;
-- Normal + RandomVal >= Min and RandomVal < Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- Poisson : Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
impure function Poisson (Mean : real) return real ;
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- randomization with a range
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal(Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
-- randomization with a range and exclude vector
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
-- Randomly select a value within a set of values
impure function RandInt ( A : integer_vector ) return integer ;
impure function RandReal ( A : real_vector ) return real ;
impure function RandTime (A : time_vector) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
impure function RandInt ( A, Exclude : integer_vector ) return integer ;
impure function RandReal ( A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
impure function DistInt ( Weight : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed ;
-- Distribution with just weights and with exclude values
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
-- Distribution with weight and value
impure function DistValInt ( A : DistType ) return integer ;
impure function DistValSlv ( A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Size : natural) return signed ;
-- Distribution with weight and value and with exclude values
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
-- Large vector handling.
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
-- Convenience Functions
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal(Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
-----------------------------------------------------------------
-- Scale -- Scale a value to be within a given range
--
function Scale (A, Min, Max : real) return real is
variable ValRange : Real ;
begin
if Max >= Min then
ValRange := Max - Min ;
return A * ValRange + Min ;
else
return real'left ;
end if ;
end function Scale ;
function Scale (A : real ; Min, Max : integer) return integer is
variable ValRange : real ;
variable rMin, rMax : real ;
begin
if Max >= Min then
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
else
return integer'left ;
end if ;
end function Scale ;
-- create more smaller values
function FavorSmall (A : real) return real is
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-- create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
begin
return sqrt(A) ;
end FavorBig ;
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-- Local. Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- RandomParmType IO
-----------------------------------------------------------------
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-----------------------------------------------------------------
type RandomPType is protected body
--
-- RandomSeed manipulation
--
variable RandomSeed : RandomSeedType := GenRandSeed(integer_vector'(1,7)) ;
procedure InitSeed (S : string ) is
begin
RandomSeed := GenRandSeed(S) ;
end procedure InitSeed ;
procedure InitSeed (I : integer ) is
begin
RandomSeed := GenRandSeed(I) ;
end procedure InitSeed ;
procedure InitSeed (IV : integer_vector ) is
begin
RandomSeed := GenRandSeed(IV) ;
end procedure InitSeed ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
impure function GetSeed return RandomSeedType is
begin
return RandomSeed ;
end function GetSeed ;
impure function SeedRandom return RandomSeedType is
begin
return RandomSeed ;
end function SeedRandom ;
--
-- randomization mode
--
variable RandomParm : RandomParmType ; -- left most values ok for init
procedure SetRandomParm (RandomParmIn : RandomParmType) is
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
impure function GetRandomParm return RandomParmType is
begin
return RandomParm ;
end function GetRandomParm ;
impure function GetRandomParm return RandomDistType is
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
-- For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--
-- Base Randomization Distributions
--
--
-- Uniform : Generate a random number with a Uniform distribution
--
impure function Uniform (Min, Max : in real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function Uniform ;
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
impure function FavorSmall (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- real
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- integer
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
impure function FavorBig (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- real
end function FavorBig ;
impure function FavorBig (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- integer
end function FavorBig ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
-- Use polar method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Marsaglia_polar_method
--
impure function Normal (Mean, StdDeviation : real) return real is
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
Uniform (x01, RandomSeed) ;
Uniform (y01, RandomSeed) ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
impure function Poisson (Mean : real) return real is
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
Uniform(UniformRand, RandomSeed) ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--
-- integer randomization with a range
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
--
-- real randomization with a range
-- Distribution determined by RandomParm
--
impure function RandReal(Min, Max : Real) return real is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function RandReal ;
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := RandInt(0, (Max - Min)/Unit) ;
Return Min + Unit*IntVal ;
end function RandTime ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(Min, Max) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(Min, Max, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, Max/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--
-- integer randomization with a range and exclude vector
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
variable IntVal : integer ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, Max, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
begin
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values
-- Distribution determined by RandomParm
--
impure function RandInt ( A : integer_vector ) return integer is
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
impure function RandReal ( A : real_vector ) return real is
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
impure function RandTime ( A : time_vector ) return time is
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Distribution determined by RandomParm
--
impure function RandInt ( A, Exclude : integer_vector ) return integer is
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
impure function RandReal ( A, Exclude : real_vector ) return real is
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
impure function RandTime ( A, Exclude : time_vector ) return time is
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
impure function DistInt ( Weight : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--
-- Large vector handling.
--
impure function RandUnsigned (Size : natural) return unsigned is
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
impure function RandSlv (Size : natural) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
impure function RandSigned (Size : natural) return signed is
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
impure function RandUnsigned (Max : unsigned) return unsigned is
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := find_leftmost(normMax, '1') ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
impure function RandSigned (Max : signed) return signed is
begin
if max'length > 0 then
AlertIf (OSVVM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
impure function RandSigned (Min, Max : signed) return signed is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--
-- Convenience Functions. Resolve into calls into the other functions
--
impure function RandReal return real is
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
impure function RandReal(Max : Real) return real is -- 0.0 to Max
begin
return RandReal(0.0, Max) ;
end function RandReal ;
impure function RandInt (Max : integer) return integer is
begin
return RandInt(0, Max) ;
end function RandInt ;
impure function RandSlv (Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
end protected body RandomPType ;
end RandomPkg ; |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email : [email protected]
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 12/2006 : 0.1 Initial revision
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
--
-- Copyright (c) 2006 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software ; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation ; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY ; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http ://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- Uncomment the following with VHDL-2008 package generics.
-- For now they are defined in the package RandomBasePkg.vhd
-- package RandomGenericPkg is
-- generic (
-- type RandomSeedType ; -- base type for randomization
-- procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- function GenRandSeed(IV : integer_vector) return RandomSeedType ;
-- function GenRandSeed(I : integer) return RandomSeedType ;
-- function GenRandSeed(S : string) return RandomSeedType ;
-- ) ;
-- make things from SortListPkg_int visible
alias sort is work.SortListPkg_int.sort[integer_vector return integer_vector] ;
alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Parameters for randomization
-- RandomDistType specifies the distribution to use for randomize
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomParmType ) ;
type RandomPType is protected
-- Seed Manipulation
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure InitSeed (IV : integer_vector ) ;
-- SetSeed & GetSeed : Used to save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
-- SeedRandom = SetSeed & GetSeed for SV compatibility
-- replace with aliases when they work in popular simulators
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
-- Setting Randomization Parameters
-- Allows RandInt to have distributions other than uniform
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
-- Base Randomization Distributions
-- Uniform : Generate a random number with a Uniform distribution
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- Normal : Generate a random number with a normal distribution
impure function Normal (Mean, StdDeviation : real) return real ;
-- Normal + RandomVal >= Min and RandomVal < Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- Poisson : Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
impure function Poisson (Mean : real) return real ;
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- randomization with a range
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal(Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
-- randomization with a range and exclude vector
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
-- Randomly select a value within a set of values
impure function RandInt ( A : integer_vector ) return integer ;
impure function RandReal ( A : real_vector ) return real ;
impure function RandTime (A : time_vector) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
impure function RandInt ( A, Exclude : integer_vector ) return integer ;
impure function RandReal ( A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
impure function DistInt ( Weight : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed ;
-- Distribution with just weights and with exclude values
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
-- Distribution with weight and value
impure function DistValInt ( A : DistType ) return integer ;
impure function DistValSlv ( A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Size : natural) return signed ;
-- Distribution with weight and value and with exclude values
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
-- Large vector handling.
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
-- Convenience Functions
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal(Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
-----------------------------------------------------------------
-- Scale -- Scale a value to be within a given range
--
function Scale (A, Min, Max : real) return real is
variable ValRange : Real ;
begin
if Max >= Min then
ValRange := Max - Min ;
return A * ValRange + Min ;
else
return real'left ;
end if ;
end function Scale ;
function Scale (A : real ; Min, Max : integer) return integer is
variable ValRange : real ;
variable rMin, rMax : real ;
begin
if Max >= Min then
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
else
return integer'left ;
end if ;
end function Scale ;
-- create more smaller values
function FavorSmall (A : real) return real is
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-- create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
begin
return sqrt(A) ;
end FavorBig ;
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-- Local. Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- RandomParmType IO
-----------------------------------------------------------------
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-----------------------------------------------------------------
type RandomPType is protected body
--
-- RandomSeed manipulation
--
variable RandomSeed : RandomSeedType := GenRandSeed(integer_vector'(1,7)) ;
procedure InitSeed (S : string ) is
begin
RandomSeed := GenRandSeed(S) ;
end procedure InitSeed ;
procedure InitSeed (I : integer ) is
begin
RandomSeed := GenRandSeed(I) ;
end procedure InitSeed ;
procedure InitSeed (IV : integer_vector ) is
begin
RandomSeed := GenRandSeed(IV) ;
end procedure InitSeed ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
impure function GetSeed return RandomSeedType is
begin
return RandomSeed ;
end function GetSeed ;
impure function SeedRandom return RandomSeedType is
begin
return RandomSeed ;
end function SeedRandom ;
--
-- randomization mode
--
variable RandomParm : RandomParmType ; -- left most values ok for init
procedure SetRandomParm (RandomParmIn : RandomParmType) is
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
impure function GetRandomParm return RandomParmType is
begin
return RandomParm ;
end function GetRandomParm ;
impure function GetRandomParm return RandomDistType is
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
-- For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--
-- Base Randomization Distributions
--
--
-- Uniform : Generate a random number with a Uniform distribution
--
impure function Uniform (Min, Max : in real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function Uniform ;
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
impure function FavorSmall (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- real
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- integer
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
impure function FavorBig (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- real
end function FavorBig ;
impure function FavorBig (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- integer
end function FavorBig ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
-- Use polar method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Marsaglia_polar_method
--
impure function Normal (Mean, StdDeviation : real) return real is
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
Uniform (x01, RandomSeed) ;
Uniform (y01, RandomSeed) ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
impure function Poisson (Mean : real) return real is
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
Uniform(UniformRand, RandomSeed) ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--
-- integer randomization with a range
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
--
-- real randomization with a range
-- Distribution determined by RandomParm
--
impure function RandReal(Min, Max : Real) return real is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function RandReal ;
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := RandInt(0, (Max - Min)/Unit) ;
Return Min + Unit*IntVal ;
end function RandTime ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(Min, Max) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(Min, Max, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, Max/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--
-- integer randomization with a range and exclude vector
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
variable IntVal : integer ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, Max, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
begin
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values
-- Distribution determined by RandomParm
--
impure function RandInt ( A : integer_vector ) return integer is
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
impure function RandReal ( A : real_vector ) return real is
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
impure function RandTime ( A : time_vector ) return time is
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Distribution determined by RandomParm
--
impure function RandInt ( A, Exclude : integer_vector ) return integer is
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
impure function RandReal ( A, Exclude : real_vector ) return real is
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
impure function RandTime ( A, Exclude : time_vector ) return time is
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
impure function DistInt ( Weight : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--
-- Large vector handling.
--
impure function RandUnsigned (Size : natural) return unsigned is
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
impure function RandSlv (Size : natural) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
impure function RandSigned (Size : natural) return signed is
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
impure function RandUnsigned (Max : unsigned) return unsigned is
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := find_leftmost(normMax, '1') ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
impure function RandSigned (Max : signed) return signed is
begin
if max'length > 0 then
AlertIf (OSVVM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
impure function RandSigned (Min, Max : signed) return signed is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--
-- Convenience Functions. Resolve into calls into the other functions
--
impure function RandReal return real is
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
impure function RandReal(Max : Real) return real is -- 0.0 to Max
begin
return RandReal(0.0, Max) ;
end function RandReal ;
impure function RandInt (Max : integer) return integer is
begin
return RandInt(0, Max) ;
end function RandInt ;
impure function RandSlv (Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
end protected body RandomPType ;
end RandomPkg ; |
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email : [email protected]
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 12/2006 : 0.1 Initial revision
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
--
-- Copyright (c) 2006 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software ; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation ; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY ; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http ://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- Uncomment the following with VHDL-2008 package generics.
-- For now they are defined in the package RandomBasePkg.vhd
-- package RandomGenericPkg is
-- generic (
-- type RandomSeedType ; -- base type for randomization
-- procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- function GenRandSeed(IV : integer_vector) return RandomSeedType ;
-- function GenRandSeed(I : integer) return RandomSeedType ;
-- function GenRandSeed(S : string) return RandomSeedType ;
-- ) ;
-- make things from SortListPkg_int visible
alias sort is work.SortListPkg_int.sort[integer_vector return integer_vector] ;
alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Parameters for randomization
-- RandomDistType specifies the distribution to use for randomize
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomParmType ) ;
type RandomPType is protected
-- Seed Manipulation
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure InitSeed (IV : integer_vector ) ;
-- SetSeed & GetSeed : Used to save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
-- SeedRandom = SetSeed & GetSeed for SV compatibility
-- replace with aliases when they work in popular simulators
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
-- Setting Randomization Parameters
-- Allows RandInt to have distributions other than uniform
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
-- Base Randomization Distributions
-- Uniform : Generate a random number with a Uniform distribution
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- Normal : Generate a random number with a normal distribution
impure function Normal (Mean, StdDeviation : real) return real ;
-- Normal + RandomVal >= Min and RandomVal < Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- Poisson : Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
impure function Poisson (Mean : real) return real ;
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- randomization with a range
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal(Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
-- randomization with a range and exclude vector
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
-- Randomly select a value within a set of values
impure function RandInt ( A : integer_vector ) return integer ;
impure function RandReal ( A : real_vector ) return real ;
impure function RandTime (A : time_vector) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
impure function RandInt ( A, Exclude : integer_vector ) return integer ;
impure function RandReal ( A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
impure function DistInt ( Weight : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed ;
-- Distribution with just weights and with exclude values
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
-- Distribution with weight and value
impure function DistValInt ( A : DistType ) return integer ;
impure function DistValSlv ( A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Size : natural) return signed ;
-- Distribution with weight and value and with exclude values
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
-- Large vector handling.
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
-- Convenience Functions
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal(Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
-----------------------------------------------------------------
-- Scale -- Scale a value to be within a given range
--
function Scale (A, Min, Max : real) return real is
variable ValRange : Real ;
begin
if Max >= Min then
ValRange := Max - Min ;
return A * ValRange + Min ;
else
return real'left ;
end if ;
end function Scale ;
function Scale (A : real ; Min, Max : integer) return integer is
variable ValRange : real ;
variable rMin, rMax : real ;
begin
if Max >= Min then
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
else
return integer'left ;
end if ;
end function Scale ;
-- create more smaller values
function FavorSmall (A : real) return real is
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-- create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
begin
return sqrt(A) ;
end FavorBig ;
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-- Local. Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- RandomParmType IO
-----------------------------------------------------------------
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-----------------------------------------------------------------
type RandomPType is protected body
--
-- RandomSeed manipulation
--
variable RandomSeed : RandomSeedType := GenRandSeed(integer_vector'(1,7)) ;
procedure InitSeed (S : string ) is
begin
RandomSeed := GenRandSeed(S) ;
end procedure InitSeed ;
procedure InitSeed (I : integer ) is
begin
RandomSeed := GenRandSeed(I) ;
end procedure InitSeed ;
procedure InitSeed (IV : integer_vector ) is
begin
RandomSeed := GenRandSeed(IV) ;
end procedure InitSeed ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
impure function GetSeed return RandomSeedType is
begin
return RandomSeed ;
end function GetSeed ;
impure function SeedRandom return RandomSeedType is
begin
return RandomSeed ;
end function SeedRandom ;
--
-- randomization mode
--
variable RandomParm : RandomParmType ; -- left most values ok for init
procedure SetRandomParm (RandomParmIn : RandomParmType) is
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
impure function GetRandomParm return RandomParmType is
begin
return RandomParm ;
end function GetRandomParm ;
impure function GetRandomParm return RandomDistType is
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
-- For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--
-- Base Randomization Distributions
--
--
-- Uniform : Generate a random number with a Uniform distribution
--
impure function Uniform (Min, Max : in real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function Uniform ;
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
impure function FavorSmall (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- real
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- integer
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
impure function FavorBig (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- real
end function FavorBig ;
impure function FavorBig (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- integer
end function FavorBig ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
-- Use polar method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Marsaglia_polar_method
--
impure function Normal (Mean, StdDeviation : real) return real is
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
Uniform (x01, RandomSeed) ;
Uniform (y01, RandomSeed) ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
impure function Poisson (Mean : real) return real is
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
Uniform(UniformRand, RandomSeed) ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--
-- integer randomization with a range
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
--
-- real randomization with a range
-- Distribution determined by RandomParm
--
impure function RandReal(Min, Max : Real) return real is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function RandReal ;
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := RandInt(0, (Max - Min)/Unit) ;
Return Min + Unit*IntVal ;
end function RandTime ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(Min, Max) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(Min, Max, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, Max/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--
-- integer randomization with a range and exclude vector
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
variable IntVal : integer ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, Max, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
begin
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values
-- Distribution determined by RandomParm
--
impure function RandInt ( A : integer_vector ) return integer is
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
impure function RandReal ( A : real_vector ) return real is
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
impure function RandTime ( A : time_vector ) return time is
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Distribution determined by RandomParm
--
impure function RandInt ( A, Exclude : integer_vector ) return integer is
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
impure function RandReal ( A, Exclude : real_vector ) return real is
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
impure function RandTime ( A, Exclude : time_vector ) return time is
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
impure function DistInt ( Weight : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--
-- Large vector handling.
--
impure function RandUnsigned (Size : natural) return unsigned is
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
impure function RandSlv (Size : natural) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
impure function RandSigned (Size : natural) return signed is
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
impure function RandUnsigned (Max : unsigned) return unsigned is
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := find_leftmost(normMax, '1') ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
impure function RandSigned (Max : signed) return signed is
begin
if max'length > 0 then
AlertIf (OSVVM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
impure function RandSigned (Min, Max : signed) return signed is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--
-- Convenience Functions. Resolve into calls into the other functions
--
impure function RandReal return real is
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
impure function RandReal(Max : Real) return real is -- 0.0 to Max
begin
return RandReal(0.0, Max) ;
end function RandReal ;
impure function RandInt (Max : integer) return integer is
begin
return RandInt(0, Max) ;
end function RandInt ;
impure function RandSlv (Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
end protected body RandomPType ;
end RandomPkg ; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1;
USE axi_dma_v7_1.axi_dma;
ENTITY design_1_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_dma_0_0;
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_1_axi_dma_0_0_arch;
|
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
package pkg is
procedure proc;
alias prog_alias is proc[];
end package;
package body pkg is
procedure proc is
begin
end;
impure function prog_alias return integer is
begin
prog_alias;
return 0;
end;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2606.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02606ent IS
END c13s03b01x00p02n01i02606ent;
ARCHITECTURE c13s03b01x00p02n01i02606arch OF c13s03b01x00p02n01i02606ent IS
BEGIN
TESTING: PROCESS
variable k> : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02606 - Identifier can not end with '>'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02606arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2606.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02606ent IS
END c13s03b01x00p02n01i02606ent;
ARCHITECTURE c13s03b01x00p02n01i02606arch OF c13s03b01x00p02n01i02606ent IS
BEGIN
TESTING: PROCESS
variable k> : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02606 - Identifier can not end with '>'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02606arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2606.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02606ent IS
END c13s03b01x00p02n01i02606ent;
ARCHITECTURE c13s03b01x00p02n01i02606arch OF c13s03b01x00p02n01i02606ent IS
BEGIN
TESTING: PROCESS
variable k> : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02606 - Identifier can not end with '>'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02606arch;
|
library verilog;
use verilog.vl_types.all;
entity my_ROM is
port(
addr : in vl_logic_vector(3 downto 0);
clk : in vl_logic;
\out\ : out vl_logic_vector(7 downto 0)
);
end my_ROM;
|
----------------------------------------------------------------------------------
-- Company: Federal University of Santa Catarina
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
entity deslocadorEsquerda is
generic(largura: natural := 8);
port(
entrada: in std_logic_vector(largura-1 downto 0);
saida: out std_logic_vector(largura-1 downto 0)
);
end entity;
architecture comportamental of deslocadorEsquerda is
begin
saida <= entrada(largura-3 downto 0) & "00";
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02324ent IS
END c07s02b07x00p01n01i02324ent;
ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable INTV1 : INTEGER;
variable INTV2 : INTEGER;
variable INTV3 : INTEGER;
variable INTV4 : INTEGER;
variable INTV5 : INTEGER;
variable INTV6 : INTEGER;
variable INTV7 : INTEGER;
variable INTV8 : INTEGER;
variable REALV1 : REAL;
variable REALV2 : REAL;
variable REALV3 : REAL;
variable REALV4 : REAL;
variable REALV5 : REAL;
variable REALV6 : REAL;
variable REALV7 : REAL;
variable REALV8 : REAL;
BEGIN
-- Test absolute value of integer literals and variables.
INTV1 := abs (-5);
assert (INTV1 = 5)
report "Assertion Violation(1)";
INTV2 := abs 5;
assert (INTV2 = 5)
report "Assertion Violation(2)";
INTV3 := abs 0;
assert (INTV3 = 0)
report "Assertion Violation(3)";
INTV4 := abs INTEGER'HIGH;
assert (INTV4 = INTEGER'HIGH)
report "Assertion Violation(4)";
INTV5 := -5;
INTV5 := abs INTV5;
assert (INTV5 = 5)
report "Assertion Violation(5)";
INTV6 := 5;
INTV6 := abs 5;
assert (INTV6 = 5)
report "Assertion Violation(6)";
INTV7 := 0;
INTV7 := abs 0;
assert (INTV7 = 0)
report "Assertion Violation(7)";
INTV8 := INTEGER'HIGH;
INTV8 := abs INTEGER'HIGH;
assert (INTV8 = INTEGER'HIGH)
report "Assertion Violation(8)";
-- Do the same for the predefined physical type TIME.
assert (abs (-5 ns) = 5 ns)
report "Assertion Violation(9)";
assert (abs 5 ns = 5 ns)
report "Assertion Violation(10)";
assert (abs 0 fs = 0 fs)
report "Assertion Violation(11)";
assert (abs TIME'HIGH = TIME'HIGH)
report "Assertion Violation(12)";
-- Test absolute value of real literals and variables.
REALV1 := abs (-5.0);
assert (REALV1 = 5.0)
report "Assertion Violation(13)";
REALV2 := abs 5.0;
assert (REALV2 = 5.0)
report "Assertion Violation(14)";
REALV3 := abs 0.0;
assert (REALV3 = 0.0)
report "Assertion Violation(15)";
REALV4 := abs REAL'HIGH;
assert (REALV4 = REAL'HIGH)
report "Assertion Violation(16)";
REALV5 := -5.0;
REALV5 := abs REALV5;
assert (REALV5 = 5.0)
report "Assertion Violation(17)";
REALV6 := 5.0;
REALV6 := abs 5.0;
assert (REALV6 = 5.0)
report "Assertion Violation(18)";
REALV7 := 0.0;
REALV7 := abs 0.0;
assert (REALV7 = 0.0)
report "Assertion Violation(19)";
REALV8 := REAL'HIGH;
REALV8 := abs REAL'HIGH;
assert (REALV8 = REAL'HIGH)
report "Assertion Violation(20)";
wait for 5 ns;
assert NOT( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***PASSED TEST: c07s02b07x00p01n01i02324"
severity NOTE;
assert ( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02324ent IS
END c07s02b07x00p01n01i02324ent;
ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable INTV1 : INTEGER;
variable INTV2 : INTEGER;
variable INTV3 : INTEGER;
variable INTV4 : INTEGER;
variable INTV5 : INTEGER;
variable INTV6 : INTEGER;
variable INTV7 : INTEGER;
variable INTV8 : INTEGER;
variable REALV1 : REAL;
variable REALV2 : REAL;
variable REALV3 : REAL;
variable REALV4 : REAL;
variable REALV5 : REAL;
variable REALV6 : REAL;
variable REALV7 : REAL;
variable REALV8 : REAL;
BEGIN
-- Test absolute value of integer literals and variables.
INTV1 := abs (-5);
assert (INTV1 = 5)
report "Assertion Violation(1)";
INTV2 := abs 5;
assert (INTV2 = 5)
report "Assertion Violation(2)";
INTV3 := abs 0;
assert (INTV3 = 0)
report "Assertion Violation(3)";
INTV4 := abs INTEGER'HIGH;
assert (INTV4 = INTEGER'HIGH)
report "Assertion Violation(4)";
INTV5 := -5;
INTV5 := abs INTV5;
assert (INTV5 = 5)
report "Assertion Violation(5)";
INTV6 := 5;
INTV6 := abs 5;
assert (INTV6 = 5)
report "Assertion Violation(6)";
INTV7 := 0;
INTV7 := abs 0;
assert (INTV7 = 0)
report "Assertion Violation(7)";
INTV8 := INTEGER'HIGH;
INTV8 := abs INTEGER'HIGH;
assert (INTV8 = INTEGER'HIGH)
report "Assertion Violation(8)";
-- Do the same for the predefined physical type TIME.
assert (abs (-5 ns) = 5 ns)
report "Assertion Violation(9)";
assert (abs 5 ns = 5 ns)
report "Assertion Violation(10)";
assert (abs 0 fs = 0 fs)
report "Assertion Violation(11)";
assert (abs TIME'HIGH = TIME'HIGH)
report "Assertion Violation(12)";
-- Test absolute value of real literals and variables.
REALV1 := abs (-5.0);
assert (REALV1 = 5.0)
report "Assertion Violation(13)";
REALV2 := abs 5.0;
assert (REALV2 = 5.0)
report "Assertion Violation(14)";
REALV3 := abs 0.0;
assert (REALV3 = 0.0)
report "Assertion Violation(15)";
REALV4 := abs REAL'HIGH;
assert (REALV4 = REAL'HIGH)
report "Assertion Violation(16)";
REALV5 := -5.0;
REALV5 := abs REALV5;
assert (REALV5 = 5.0)
report "Assertion Violation(17)";
REALV6 := 5.0;
REALV6 := abs 5.0;
assert (REALV6 = 5.0)
report "Assertion Violation(18)";
REALV7 := 0.0;
REALV7 := abs 0.0;
assert (REALV7 = 0.0)
report "Assertion Violation(19)";
REALV8 := REAL'HIGH;
REALV8 := abs REAL'HIGH;
assert (REALV8 = REAL'HIGH)
report "Assertion Violation(20)";
wait for 5 ns;
assert NOT( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***PASSED TEST: c07s02b07x00p01n01i02324"
severity NOTE;
assert ( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02324ent IS
END c07s02b07x00p01n01i02324ent;
ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable INTV1 : INTEGER;
variable INTV2 : INTEGER;
variable INTV3 : INTEGER;
variable INTV4 : INTEGER;
variable INTV5 : INTEGER;
variable INTV6 : INTEGER;
variable INTV7 : INTEGER;
variable INTV8 : INTEGER;
variable REALV1 : REAL;
variable REALV2 : REAL;
variable REALV3 : REAL;
variable REALV4 : REAL;
variable REALV5 : REAL;
variable REALV6 : REAL;
variable REALV7 : REAL;
variable REALV8 : REAL;
BEGIN
-- Test absolute value of integer literals and variables.
INTV1 := abs (-5);
assert (INTV1 = 5)
report "Assertion Violation(1)";
INTV2 := abs 5;
assert (INTV2 = 5)
report "Assertion Violation(2)";
INTV3 := abs 0;
assert (INTV3 = 0)
report "Assertion Violation(3)";
INTV4 := abs INTEGER'HIGH;
assert (INTV4 = INTEGER'HIGH)
report "Assertion Violation(4)";
INTV5 := -5;
INTV5 := abs INTV5;
assert (INTV5 = 5)
report "Assertion Violation(5)";
INTV6 := 5;
INTV6 := abs 5;
assert (INTV6 = 5)
report "Assertion Violation(6)";
INTV7 := 0;
INTV7 := abs 0;
assert (INTV7 = 0)
report "Assertion Violation(7)";
INTV8 := INTEGER'HIGH;
INTV8 := abs INTEGER'HIGH;
assert (INTV8 = INTEGER'HIGH)
report "Assertion Violation(8)";
-- Do the same for the predefined physical type TIME.
assert (abs (-5 ns) = 5 ns)
report "Assertion Violation(9)";
assert (abs 5 ns = 5 ns)
report "Assertion Violation(10)";
assert (abs 0 fs = 0 fs)
report "Assertion Violation(11)";
assert (abs TIME'HIGH = TIME'HIGH)
report "Assertion Violation(12)";
-- Test absolute value of real literals and variables.
REALV1 := abs (-5.0);
assert (REALV1 = 5.0)
report "Assertion Violation(13)";
REALV2 := abs 5.0;
assert (REALV2 = 5.0)
report "Assertion Violation(14)";
REALV3 := abs 0.0;
assert (REALV3 = 0.0)
report "Assertion Violation(15)";
REALV4 := abs REAL'HIGH;
assert (REALV4 = REAL'HIGH)
report "Assertion Violation(16)";
REALV5 := -5.0;
REALV5 := abs REALV5;
assert (REALV5 = 5.0)
report "Assertion Violation(17)";
REALV6 := 5.0;
REALV6 := abs 5.0;
assert (REALV6 = 5.0)
report "Assertion Violation(18)";
REALV7 := 0.0;
REALV7 := abs 0.0;
assert (REALV7 = 0.0)
report "Assertion Violation(19)";
REALV8 := REAL'HIGH;
REALV8 := abs REAL'HIGH;
assert (REALV8 = REAL'HIGH)
report "Assertion Violation(20)";
wait for 5 ns;
assert NOT( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***PASSED TEST: c07s02b07x00p01n01i02324"
severity NOTE;
assert ( (INTV1 = 5) and
(INTV2 = 5) and
(INTV3 = 0) and
(INTV4 = INTEGER'HIGH) and
(INTV5 = 5) and
(INTV6 = 5) and
(INTV7 = 0) and
(INTV8 = INTEGER'HIGH) and
(abs (-5 ns) = 5 ns) and
(abs 5 ns = 5 ns) and
(abs 0 fs = 0 fs) and
(abs TIME'HIGH = TIME'HIGH) and
(REALV1 = 5.0) and
(REALV2 = 5.0) and
(REALV3 = 0.0) and
(REALV4 = REAL'HIGH) and
(REALV5 = 5.0) and
(REALV6 = 5.0) and
(REALV7 = 0.0) and
(REALV8 = REAL'HIGH) )
report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02324arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc678.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:00 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:31 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:39 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00678ent IS
END c03s04b01x00p23n01i00678ent;
ARCHITECTURE c03s04b01x00p23n01i00678arch OF c03s04b01x00p23n01i00678ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type WORD is array(0 to 31) of BIT;
type FT is file of WORD;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.50";
-- Declare a variable into which we will read.
constant CON : WORD := B"11111111111111111111111111111111";
variable VAR : WORD;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00678"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00678 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00678arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc678.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:00 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:31 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:39 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00678ent IS
END c03s04b01x00p23n01i00678ent;
ARCHITECTURE c03s04b01x00p23n01i00678arch OF c03s04b01x00p23n01i00678ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type WORD is array(0 to 31) of BIT;
type FT is file of WORD;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.50";
-- Declare a variable into which we will read.
constant CON : WORD := B"11111111111111111111111111111111";
variable VAR : WORD;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00678"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00678 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00678arch;
|
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