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library ieee;
use ieee.std_logic_1164.all;
package ftlbase is
constant ZERO_std_ulogic : std_ulogic := '0';
constant UNDEF_std_ulogic : std_ulogic := 'U';
function to_bool(x: std_ulogic) return boolean;
function to_stdulogic(x: boolean) return std_ulogic;
function zero_std_logic_vector(hi: integer; lo: integer) return std_logic_vector;
function undef_std_logic_vector(hi: integer; lo: integer) return std_logic_vector;
end;
package body ftlbase is
function to_bool(x: std_ulogic) return boolean is
begin
return (x = '1');
end function to_bool;
function to_stdulogic(x: boolean) return std_ulogic is
begin
if x then
return '1';
else
return '0';
end if;
end function;
function zero_std_logic_vector(hi: integer; lo: integer) return std_logic_vector is
variable v : std_logic_vector(hi downto lo) := (others => '0');
begin
return v;
end function zero_std_logic_vector;
function undef_std_logic_vector(hi: integer; lo: integer) return std_logic_vector is
variable v : std_logic_vector(hi downto lo) := (others => 'U');
begin
return v;
end function undef_std_logic_vector;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:03 06/10/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UDP_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
ENTITY UDP_RX_tb IS
END UDP_RX_tb;
ARCHITECTURE behavior OF UDP_RX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rxo : inout udp_rx_type;
udp_rx_start : out std_logic; -- indicates receipt of udp header
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : inout ipv4_rx_type
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ip_rx_start : std_logic := '0';
--BiDirs
signal udp_rxo : udp_rx_type;
signal ip_rx : ipv4_rx_type;
--Outputs
signal udp_rx_start : std_logic;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UDP_RX PORT MAP (
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
clk => clk,
reset => reset,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
ip_rx.hdr.protocol <= (others => '0');
ip_rx.hdr.num_frame_errors <= (others => '0');
ip_rx.hdr.last_error_code <= (others => '0');
ip_rx.hdr.is_broadcast <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
reset <= '0';
-- check reset conditions
assert udp_rx_start = '0' report "udp_rx_start not initialised correctly on reset";
assert udp_rxo.hdr.is_valid = '0' report "udp_rxo.hdr.is_valid not initialised correctly on reset";
assert udp_rxo.data.data_in = x"00" report "udp_rxo.data.data_in not initialised correctly on reset";
assert udp_rxo.data.data_in_valid = '0' report "udp_rxo.data.data_in_valid not initialised correctly on reset";
assert udp_rxo.data.data_in_last = '0' report "udp_rxo.data.data_in_last not initialised correctly on reset";
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T1: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T1: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T1: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T1: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T1: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T1: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T1: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T1: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T1: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T1: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
------------
-- TEST 2 -- ability to receive 2nd ip pkt
------------
report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T2: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"7623" report "T2: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"0365" report "T2: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0005" report "T2: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T2: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T2: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T2: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T2: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T2: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T2: udp_rxo.data.data_in_last not cleared";
------------
-- TEST 3 -- ability to reject non-udp protocols
------------
report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"12"; -- non-UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '0' report "T3: udp_rxo.hdr.is_valid incorrectly set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rx_start = '0' report "T3: udp_rx_start incorrectly set";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last incorrectly set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T3: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
------------
-- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
------------
report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T4: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T4: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T4: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T4: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T4: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T4: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T4: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T4: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T4: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T4: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
report "--- end of tests ---";
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- [email protected]
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- [filter]
-- Length of filters used on SCL and SDA
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if r.transmit and v.scl = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= r.reg.ctrl.en;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
-------------------------------------------------------------------------------
-- $Id: parity.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity negate is
end entity negate;
architecture test of negate is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity negate is
end entity negate;
architecture test of negate is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity negate is
end entity negate;
architecture test of negate is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.types_mem.all;
library riverlib;
use riverlib.types_cache.all;
entity tagmemcoupled is generic (
memtech : integer := 0;
async_reset : boolean := false;
abus : integer := 64; -- system bus address bus (32 or 64 bits)
waybits : integer := 2; -- log2 of number of ways bits (=2 for 4 ways)
ibits : integer := 7; -- lines memory addres width (usually 6..8)
lnbits : integer := 5; -- One line bits: log2(bytes_per_line)
flbits : integer := 1 -- Total flags number saved with address tag
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_direct_access : in std_logic;
i_invalidate : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_addr : in std_logic_vector(abus-1 downto 0);
i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0);
i_wstrb : in std_logic_vector(2**lnbits-1 downto 0);
i_wflags : in std_logic_vector(flbits-1 downto 0);
o_raddr : out std_logic_vector(abus-1 downto 0);
o_rdata : out std_logic_vector(8*(2**lnbits)+15 downto 0);
o_rflags : out std_logic_vector(flbits-1 downto 0);
o_hit : out std_logic;
o_hit_next : out std_logic
);
end;
architecture arch_tagmemcoupled of tagmemcoupled is
constant TAG_START : integer := abus - (ibits + lnbits);
constant EVEN : integer := 0;
constant ODD : integer := 1;
constant MemTotal : integer := 2;
type tagmem_in_type is record
direct_access : std_logic;
invalidate : std_logic;
re : std_logic;
we : std_logic;
addr : std_logic_vector(abus-1 downto 0);
wdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
wstrb : std_logic_vector((2**lnbits)-1 downto 0);
wflags : std_logic_vector(flbits-1 downto 0);
snoop_addr : std_logic_vector(abus-1 downto 0);
end record;
type tagmem_out_type is record
raddr : std_logic_vector(abus-1 downto 0);
rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
rflags : std_logic_vector(flbits-1 downto 0);
hit : std_logic;
snoop_ready : std_logic;
snoop_flags : std_logic_vector(flbits-1 downto 0);
end record;
type tagmem_in_vector is array (0 to MemTotal-1) of tagmem_in_type;
type tagmem_out_vector is array (0 to MemTotal-1) of tagmem_out_type;
signal r_req_addr : std_logic_vector(abus-1 downto 0);
signal linei : tagmem_in_vector;
signal lineo : tagmem_out_vector;
begin
dx : for i in 0 to MemTotal-1 generate
memx : tagmemnway generic map (
async_reset => async_reset,
memtech => memtech,
abus => abus,
waybits => waybits,
ibits => ibits - 1,
lnbits => lnbits,
flbits => flbits,
snoop => false
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_direct_access => linei(i).direct_access,
i_invalidate => linei(i).invalidate,
i_re => linei(i).re,
i_we => linei(i).we,
i_addr => linei(i).addr,
i_wdata => linei(i).wdata,
i_wstrb => linei(i).wstrb,
i_wflags => linei(i).wflags,
o_raddr => lineo(i).raddr,
o_rdata => lineo(i).rdata,
o_rflags => lineo(i).rflags,
o_hit => lineo(i).hit,
i_snoop_addr => linei(i).snoop_addr,
o_snoop_ready => lineo(i).snoop_ready,
o_snoop_flags => lineo(i).snoop_flags
);
end generate;
comb : process(i_nrst, i_direct_access, i_invalidate, i_re, i_we,
i_addr, i_wstrb, i_wdata, i_wflags,
lineo, r_req_addr)
variable v_addr_sel : std_logic;
variable v_addr_sel_r : std_logic;
variable v_use_overlay : std_logic;
variable v_use_overlay_r : std_logic;
variable vb_index : std_logic_vector(ibits-1 downto 0);
variable vb_index_next : std_logic_vector(ibits-1 downto 0);
variable vb_addr_next : std_logic_vector(abus-1 downto 0);
variable vb_addr_tag_direct : std_logic_vector(abus-1 downto 0);
variable vb_addr_tag_next : std_logic_vector(abus-1 downto 0);
variable vb_raddr_tag : std_logic_vector(abus-1 downto 0);
variable vb_o_raddr : std_logic_vector(abus-1 downto 0);
variable vb_o_rdata : std_logic_vector(8*(2**lnbits)+15 downto 0);
variable v_o_hit : std_logic;
variable v_o_hit_next : std_logic;
variable vb_o_rflags : std_logic_vector(flbits-1 downto 0);
begin
v_addr_sel := i_addr(lnbits);
v_addr_sel_r := r_req_addr(lnbits);
vb_addr_next := i_addr + (2**lnbits);
vb_index := i_addr(ibits+lnbits-1 downto lnbits);
vb_index_next := vb_addr_next(ibits+lnbits-1 downto lnbits);
v_use_overlay := and_reduce(i_addr(lnbits-1 downto 1));
v_use_overlay_r := and_reduce(r_req_addr(lnbits-1 downto 1));
-- Change the bit order in the requested address:
-- [tag][line_idx][odd/evenbit][line_bytes] on
-- [tag][1'b0] [line_idx] [line_bytes]
--
-- Example (abus=32; ibits=7; lnbits=5;):
-- [4:0] byte in line [4:0]
-- [11:5] line index {[1'b0],[11:6]}
-- [31:12] tag [31:12]
vb_addr_tag_direct := i_addr;
vb_addr_tag_direct(ibits + lnbits - 1 downto lnbits) := '0' & vb_index(ibits-1 downto 1);
vb_addr_tag_next := vb_addr_next;
vb_addr_tag_next(ibits + lnbits - 1 downto lnbits) := '0' & vb_index_next(ibits-1 downto 1);
if v_addr_sel = '0' then
linei(EVEN).addr <= vb_addr_tag_direct;
linei(EVEN).wstrb <= i_wstrb;
linei(ODD).addr <= vb_addr_tag_next;
linei(ODD).wstrb <= (others => '0');
else
linei(EVEN).addr <= vb_addr_tag_next;
linei(EVEN).wstrb <= (others => '0');
linei(ODD).addr <= vb_addr_tag_direct;
linei(ODD).wstrb <= i_wstrb;
end if;
linei(EVEN).direct_access <= i_direct_access and ((not v_addr_sel) or v_use_overlay);
linei(ODD).direct_access <= i_direct_access and (v_addr_sel or v_use_overlay);
linei(EVEN).invalidate <= i_invalidate and ((not v_addr_sel) or v_use_overlay);
linei(ODD).invalidate <= i_invalidate and (v_addr_sel or v_use_overlay);
linei(EVEN).re <= i_re and ((not v_addr_sel) or v_use_overlay);
linei(ODD).re <= i_re and (v_addr_sel or v_use_overlay);
linei(EVEN).we <= i_we and ((not v_addr_sel) or v_use_overlay);
linei(ODD).we <= i_we and (v_addr_sel or v_use_overlay);
linei(EVEN).wdata <= i_wdata;
linei(ODD).wdata <= i_wdata;
linei(EVEN).wflags <= i_wflags;
linei(ODD).wflags <= i_wflags;
-- Form output:
if v_addr_sel_r = '0' then
vb_o_rdata := lineo(ODD).rdata(15 downto 0) & lineo(EVEN).rdata;
vb_raddr_tag := lineo(EVEN).raddr;
vb_o_rflags := lineo(EVEN).rflags;
v_o_hit := lineo(EVEN).hit;
if v_use_overlay_r = '0' then
v_o_hit_next := lineo(EVEN).hit;
else
v_o_hit_next := lineo(ODD).hit;
end if;
else
vb_o_rdata := lineo(EVEN).rdata(15 downto 0) & lineo(ODD).rdata;
vb_raddr_tag := lineo(ODD).raddr;
vb_o_rflags := lineo(ODD).rflags;
v_o_hit := lineo(ODD).hit;
if v_use_overlay_r = '0' then
v_o_hit_next := lineo(ODD).hit;
else
v_o_hit_next := lineo(EVEN).hit;
end if;
end if;
vb_o_raddr := vb_raddr_tag;
vb_o_raddr(lnbits) := v_addr_sel_r;
vb_o_raddr(ibits + lnbits - 1 downto lnbits + 1) :=
vb_raddr_tag(ibits + lnbits - 2 downto lnbits);
o_raddr <= vb_o_raddr;
o_rdata <= vb_o_rdata;
o_rflags <= vb_o_rflags;
o_hit <= v_o_hit;
o_hit_next <= v_o_hit_next;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r_req_addr <= (others => '0');
elsif rising_edge(i_clk) then
r_req_addr <= i_addr;
end if;
end process;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity amp_lim is
port ( terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical );
end entity amp_lim;
----------------------------------------------------------------
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain * vin;
if v_amplified'above(v_pwr) use
vout == v_pwr;
else
vout == v_amplified;
end use;
break on v_amplified'above(v_pwr);
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity amp_lim is
port ( terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical );
end entity amp_lim;
----------------------------------------------------------------
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain * vin;
if v_amplified'above(v_pwr) use
vout == v_pwr;
else
vout == v_amplified;
end use;
break on v_amplified'above(v_pwr);
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity amp_lim is
port ( terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical );
end entity amp_lim;
----------------------------------------------------------------
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain * vin;
if v_amplified'above(v_pwr) use
vout == v_pwr;
else
vout == v_amplified;
end use;
break on v_amplified'above(v_pwr);
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
|
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
|
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
|
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
|
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_bb
--
-- Generated
-- by: wig
-- on: Wed Nov 30 13:58:36 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_bb-e.vhd,v 1.3 2006/03/17 11:59:29 wig Exp $
-- $Date: 2006/03/17 11:59:29 $
-- $Log: ent_bb-e.vhd,v $
-- Revision 1.3 2006/03/17 11:59:29 wig
-- Testcase updated ( [cut] was wrong!)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_bb
--
entity ent_bb is
-- Generics:
-- No Generated Generics for Entity ent_bb
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_bb
sc_p_3 : in std_ulogic_vector(31 downto 0); -- reverse order
-- multiline comments
sc_p_4 : in std_ulogic_vector(31 downto 0) -- reverse order
-- multiline comments
-- line 3
-- line 4
-- line 5
-- line 6
-- line 7
-- line 8
-- line 9
-- line 10
-- ...[cut]...
-- End of Generated Port for Entity ent_bb
);
end ent_bb;
--
-- End of Generated Entity ent_bb
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- Technology and synthesis options
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
constant CFG_PADTECH : integer := CFG_PAD_TECH;
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
-- NEED RESULT: ARCH00700: Expressions, signal and variable names allowed as actual designator in association list passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00700
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00700
-- ENT00700(ARCH00700)
-- ENT00700_Test_Bench(ARCH00700_Test_Bench)
--
-- REVISION HISTORY:
--
-- 09-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
package PKG00700 is
subtype integer1 is integer range -100 to 100 ;
subtype boolean1 is boolean range false to true ;
subtype st_arr31 is t_arr3 (highb downto lowb, true downto false ) ;
subtype integer2 is integer range 100 downto -100 ;
subtype boolean2 is boolean range true downto false ;
subtype st_arr32 is t_arr3 (lowb to highb, false to true ) ;
subtype integer3 is bf_integer integer range -100 to 100 ;
subtype boolean3 is bf_boolean boolean range true downto false;
subtype st_arr33 is bf_arr3 t_arr3 (lowb + 5 to highb + 5,
true downto false ) ;
--
signal s_integer : integer range 0 to 5 := 5 ;
signal s_boolean : boolean := true ;
signal s_st_arr3 : st_arr3 := c_st_arr3_1 ;
end PKG00700 ;
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00700.all ;
entity ENT00700 is
generic (
g_integer : integer2 ;
g_st_arr3 : st_arr32 ;
g_boolean : boolean2
) ;
port (
p_integer : integer2 ;
p_st_arr3 : st_arr32 ;
p_boolean : boolean2
) ;
end ENT00700 ;
--
architecture ARCH00700 of ENT00700 is
procedure p1 (
pc_boolean : boolean3 ;
pc_integer : integer range -100 to 100 ;
pc_st_arr3 : st_arr33 ;
pv_boolean : inout boolean3 ;
pv_integer : inout integer3 ;
pv_st_arr3 : inout st_arr3 ;
signal ps_boolean : boolean3 ;
signal ps_integer : integer2 ;
signal ps_st_arr3 : st_arr32
) is
variable correct : boolean := true ;
begin
correct := correct and pc_integer = -4 ;
correct := correct and not pc_boolean ;
correct := correct and pc_st_arr3 = c_st_arr3_2 ;
correct := correct and pv_integer = 0 ;
correct := correct and pv_boolean ;
correct := correct and pv_st_arr3 = c_st_arr3_1 ;
correct := correct and ps_integer = 5 ;
correct := correct and ps_boolean ;
correct := correct and ps_st_arr3 = c_st_arr3_1 ;
test_report ( "ARCH00700" ,
"Expressions, signal and variable names allowed as"
& " actual designator in association list" ,
correct ) ;
end p1 ;
begin
process
variable v_integer : integer := 0 ;
variable v_boolean : boolean := true ;
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
begin
p1 (
pc_integer => g_integer + s_integer ,
pc_boolean =>
boolean'val(boolean'pos(g_boolean and v_boolean) - 3 mod 2) ,
pc_st_arr3 => g_st_arr3 ,
pv_integer => v_integer ,
pv_boolean => v_boolean ,
pv_st_arr3 => v_st_arr3 ,
ps_integer => s_integer ,
ps_boolean => s_boolean ,
ps_st_arr3 => s_st_arr3
) ;
wait ;
end process ;
end ARCH00700 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00700.all ;
entity ENT00700_Test_Bench is
end ENT00700_Test_Bench ;
--
architecture ARCH00700_Test_Bench of ENT00700_Test_Bench is
begin
L1:
block
constant c_integer : integer := -6 ;
constant c_boolean : boolean := false ;
constant c_st_arr3 : st_arr3 := c_st_arr3_2 ;
component UUT
generic (
lg_boolean : boolean1 ;
lg_st_arr3 : st_arr31 ;
lg_integer : integer1
) ;
port (
lp_integer : integer1 ;
lp_st_arr3 : st_arr31 ;
lp_boolean : boolean1
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00700 ( ARCH00700 )
generic map (
g_st_arr3 => lg_st_arr3 ,
g_boolean => lg_boolean ,
g_integer => lg_integer
)
port map (
p_boolean => lp_boolean ,
p_integer => lp_integer ,
p_st_arr3 => lp_st_arr3
) ;
begin
CIS1 : UUT
generic map (
lg_st_arr3 => c_st_arr3 ,
lg_boolean => boolean'succ(c_boolean) ,
lg_integer => c_integer - 3
)
port map (
lp_st_arr3 => s_st_arr3 ,
lp_boolean => s_boolean ,
lp_integer => s_integer
) ;
end block L1 ;
end ARCH00700_Test_Bench ;
--
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_3_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_3_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_3_e
--
architecture rtl of inst_shadow_3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clk_gen_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Generic Clockgenerator
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity clk_gen is
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_val_i : in integer; -- max value to count
signal_o : out std_logic);
end clk_gen;
|
library ieee;
use ieee.std_logic_1164.all;
use work.koc_signal_pack.all;
entity koc_signal_axi4_read_cntrl is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_signal_bit_loc : integer := 0;
reg_control_status_bit_loc : integer := 1
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
int : in std_logic);
end koc_signal_axi4_read_cntrl;
architecture Behavioral of koc_signal_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
process (aclk)
variable reg_control_var : std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_arvalid='1' and axi_arready_buff='1' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '1';
axi_araddr_buff <= axi_araddr;
state <= state_read;
else
axi_arready_buff <= '1';
end if;
when state_read=>
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
else
axi_rvalid_buff <= '1';
if axi_araddr_buff=reg_control_offset then
reg_control_var := (others=>'0');
reg_control_var(reg_control_status_bit_loc) := int;
axi_rdata <= reg_control_var;
else
axi_rdata <= (others=>'0');
end if;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: BuzzerMi.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY BuzzerMi IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END BuzzerMi;
ARCHITECTURE SYN OF buzzermi IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 75757,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "75757"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "75757"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BuzzerMi_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:40 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:0][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:16][0:2047]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 4) => addrb(10 downto 0),
ADDRBWRADDR(3 downto 0) => B"1111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 16) => B"0000000000000000",
DIADI(15 downto 0) => dina(15 downto 0),
DIBDI(31 downto 16) => B"0000000000000000",
DIBDI(15 downto 0) => dinb(15 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15 downto 0) => douta(15 downto 0),
DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 16),
DOBDO(15 downto 0) => doutb(15 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88\,
DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 2),
DOPBDOP(1) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 2) => wea(1 downto 0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3 downto 2) => web(1 downto 0),
WEBWE(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 1 downto 0 );
web : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(1 downto 0),
web(1 downto 0) => web(1 downto 0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(31 downto 16),
dinb(15 downto 0) => dinb(31 downto 16),
douta(15 downto 0) => douta(31 downto 16),
doutb(15 downto 0) => doutb(31 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(1 downto 0) => wea(3 downto 2),
web(1 downto 0) => web(3 downto 2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => addrb(10 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
port map (
addra(10 downto 0) => addra(12 downto 2),
addrb(10 downto 0) => addrb(12 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 10.7492 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 2048;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 2048;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 2048;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 2048;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3008.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03008pkg is
constant C : integer;
end c02s06b00x00p07n01i03008pkg;
package body c02s06b00x00p07n01i03008pkg is
subtype S1 is Integer;
constant C : S1 := 0; --Failure_here
end c02s06b00x00p07n01i03008pkg;
ENTITY c02s06b00x00p07n01i03008ent IS
END c02s06b00x00p07n01i03008ent;
ARCHITECTURE c02s06b00x00p07n01i03008arch OF c02s06b00x00p07n01i03008ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03008 - The subtype of deferred constant C does not conform to that given in the full declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03008arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3008.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03008pkg is
constant C : integer;
end c02s06b00x00p07n01i03008pkg;
package body c02s06b00x00p07n01i03008pkg is
subtype S1 is Integer;
constant C : S1 := 0; --Failure_here
end c02s06b00x00p07n01i03008pkg;
ENTITY c02s06b00x00p07n01i03008ent IS
END c02s06b00x00p07n01i03008ent;
ARCHITECTURE c02s06b00x00p07n01i03008arch OF c02s06b00x00p07n01i03008ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03008 - The subtype of deferred constant C does not conform to that given in the full declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03008arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3008.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03008pkg is
constant C : integer;
end c02s06b00x00p07n01i03008pkg;
package body c02s06b00x00p07n01i03008pkg is
subtype S1 is Integer;
constant C : S1 := 0; --Failure_here
end c02s06b00x00p07n01i03008pkg;
ENTITY c02s06b00x00p07n01i03008ent IS
END c02s06b00x00p07n01i03008ent;
ARCHITECTURE c02s06b00x00p07n01i03008arch OF c02s06b00x00p07n01i03008ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03008 - The subtype of deferred constant C does not conform to that given in the full declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03008arch;
|
CONTEXT c1;
CONTEXT c2;
CONTEXT c2;
|
-- NEED RESULT: Assertion statement in architecture body
-- NEED RESULT: ARCH00263: Block statements, process_statements, signal assignment statements, component instantiation statements, concurrent procedure call statements and generate statements in architecture statement part passed
-- NEED RESULT: *** Check simulation log for the following message:
-- NEED RESULT: Assertion statement in architecture body
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00263
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.2.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00263)
-- ENT00263_Test_Bench(ARCH00263_Test_Bench)
--
-- REVISION HISTORY:
--
-- 16-JUL-1987 - initial revision
--
-- NOTES:
--
-- partially self checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00263 of E00000 is
signal s1, s2, s3, s4, s5, s6 : integer := 0 ;
constant c1 : boolean := false ;
procedure p1 ( signal s : inout integer ) is
begin
s <= 5 ;
end p1 ;
begin
Bl1 :
block
begin
s1 <= 5 ;
end block Bl1 ;
P01 :
process
begin
s2 <= 5 ;
wait ;
end process P01 ;
s3 <= 5 ;
with c1 select
s4 <= 5 when false,
0 when true ;
G1 :
if not c1 generate
s5 <= 5 ;
end generate G1 ;
p1 ( s6 ) ;
assert false
report "Assertion statement in architecture body"
severity note ;
process ( s1, s2, s3, s4, s5, s6 )
begin
if s1 = 5 and s2 = 5 and s3 = 5 and s4 = 5 and s5 = 5 and s6 = 5 then
test_report ( "ARCH00263" ,
"Block statements, process_statements, signal"
& " assignment statements, component instantiation"
& " statements, concurrent procedure call statements"
& " and generate statements in architecture"
& " statement part" ,
true ) ;
print ( "*** Check simulation log for the following message:" ) ;
print ( "Assertion statement in architecture body" ) ;
end if ;
end process ;
end ARCH00263 ;
entity ENT00263_Test_Bench is
end ENT00263_Test_Bench ;
architecture ARCH00263_Test_Bench of ENT00263_Test_Bench is
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00263 ) ;
begin
CIS1 : UUT ; -- component instantiation in architecture
end ARCH00263_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_add_preamble - Behavioral
--
-- Description: Add the required 16 nibbles of preamble to the data packet.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_add_preamble is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'));
end tx_add_preamble;
architecture Behavioral of tx_add_preamble is
signal delay_data : std_logic_vector(8*8-1 downto 0) := (others => '0');
signal delay_data_valid : std_logic_vector(8-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
if delay_data_valid(delay_data_valid'high)= '1' then
-- Passing through data
data_out <= delay_data(delay_data'high downto delay_data'high-7);
data_valid_out <= '1';
elsif delay_data_valid(delay_data_valid'high-1)= '1' then
-- Start Frame Delimiter
data_out <= "11010101";
data_valid_out <= '1';
elsif data_valid_in = '1' then
-- Preamble nibbles
data_out <= "01010101";
data_valid_out <= '1';
else
-- Link idle
data_out <= "00000000";
data_valid_out <= '0';
end if;
-- Move the data through the delay line
delay_data <= delay_data(delay_data'high-8 downto 0) & data_in;
delay_data_valid <= delay_data_valid(delay_data_valid'high-1 downto 0) & data_valid_in;
end if;
end process;
end Behavioral; |
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity right_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end right_XLEN_barrel_shifter;
architecture structural of right_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= '0' & i(31 downto 1);
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= "00" & s1(31 downto 2);
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= "0000" & s2(31 downto 4);
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= "00000000" & s3(31 downto 8);
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= "0000000000000000" & s4(31 downto 16);
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_A_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_A_e_rtl_conf / inst_A_e
--
configuration inst_A_e_rtl_conf of inst_A_e is
for rtl
-- Generated Configuration
for inst_aa : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ac : inst_ac_e
use configuration work.inst_ac_e_rtl_conf;
end for;
end for;
end inst_A_e_rtl_conf;
--
-- End of Generated Configuration inst_A_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_cmp_lt_0002
-- VHDL created on Thu Feb 15 17:05:08 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cmp_lt_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end fp_cmp_lt_0002;
architecture normal of fp_cmp_lt_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid6_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid7_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid8_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_x_uid9_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid10_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid11_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid12_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid13_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid14_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid16_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_y_uid23_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_y_uid24_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid25_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid26_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid27_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid28_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid30_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsNaN_uid34_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xNotZero_uid39_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yNotZero_uid40_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXPS_uid41_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXPS_uid41_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expFracX_uid43_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid45_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal efxGTefy_uid47_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal efxLTefy_uid48_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signX_uid52_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid53_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal two_uid54_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal concSXSY_uid55_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal sxLTsy_uid56_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xorSigns_uid57_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsy_uid58_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneNonZero_uid62_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rc2_uid63_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsyExpFracCompMux_uid64_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid65_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- GND(CONSTANT,0)
GND_q <= "0";
-- cstAllZWE_uid8_fpCompareTest(CONSTANT,7)
cstAllZWE_uid8_fpCompareTest_q <= "00000000";
-- exp_y_uid23_fpCompareTest(BITSELECT,22)@0
exp_y_uid23_fpCompareTest_b <= b(30 downto 23);
-- excZ_y_uid25_fpCompareTest(LOGICAL,24)@0
excZ_y_uid25_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- yNotZero_uid40_fpCompareTest(LOGICAL,39)@0
yNotZero_uid40_fpCompareTest_q <= not (excZ_y_uid25_fpCompareTest_q);
-- exp_x_uid9_fpCompareTest(BITSELECT,8)@0
exp_x_uid9_fpCompareTest_b <= a(30 downto 23);
-- excZ_x_uid11_fpCompareTest(LOGICAL,10)@0
excZ_x_uid11_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- xNotZero_uid39_fpCompareTest(LOGICAL,38)@0
xNotZero_uid39_fpCompareTest_q <= not (excZ_x_uid11_fpCompareTest_q);
-- oneNonZero_uid62_fpCompareTest(LOGICAL,61)@0
oneNonZero_uid62_fpCompareTest_q <= xNotZero_uid39_fpCompareTest_q or yNotZero_uid40_fpCompareTest_q;
-- two_uid54_fpCompareTest(CONSTANT,53)
two_uid54_fpCompareTest_q <= "10";
-- signX_uid52_fpCompareTest(BITSELECT,51)@0
signX_uid52_fpCompareTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signY_uid53_fpCompareTest(BITSELECT,52)@0
signY_uid53_fpCompareTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- concSXSY_uid55_fpCompareTest(BITJOIN,54)@0
concSXSY_uid55_fpCompareTest_q <= signX_uid52_fpCompareTest_b & signY_uid53_fpCompareTest_b;
-- sxLTsy_uid56_fpCompareTest(LOGICAL,55)@0
sxLTsy_uid56_fpCompareTest_q <= "1" WHEN concSXSY_uid55_fpCompareTest_q = two_uid54_fpCompareTest_q ELSE "0";
-- rc2_uid63_fpCompareTest(LOGICAL,62)@0
rc2_uid63_fpCompareTest_q <= sxLTsy_uid56_fpCompareTest_q and oneNonZero_uid62_fpCompareTest_q;
-- frac_x_uid10_fpCompareTest(BITSELECT,9)@0
frac_x_uid10_fpCompareTest_b <= a(22 downto 0);
-- fracXPS_uid41_fpCompareTest(LOGICAL,40)@0
fracXPS_uid41_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => xNotZero_uid39_fpCompareTest_q(0)) & xNotZero_uid39_fpCompareTest_q));
fracXPS_uid41_fpCompareTest_q <= frac_x_uid10_fpCompareTest_b and fracXPS_uid41_fpCompareTest_b;
-- expFracX_uid43_fpCompareTest(BITJOIN,42)@0
expFracX_uid43_fpCompareTest_q <= exp_x_uid9_fpCompareTest_b & fracXPS_uid41_fpCompareTest_q;
-- frac_y_uid24_fpCompareTest(BITSELECT,23)@0
frac_y_uid24_fpCompareTest_b <= b(22 downto 0);
-- fracYPS_uid42_fpCompareTest(LOGICAL,41)@0
fracYPS_uid42_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => yNotZero_uid40_fpCompareTest_q(0)) & yNotZero_uid40_fpCompareTest_q));
fracYPS_uid42_fpCompareTest_q <= frac_y_uid24_fpCompareTest_b and fracYPS_uid42_fpCompareTest_b;
-- expFracY_uid45_fpCompareTest(BITJOIN,44)@0
expFracY_uid45_fpCompareTest_q <= exp_y_uid23_fpCompareTest_b & fracYPS_uid42_fpCompareTest_q;
-- efxGTefy_uid47_fpCompareTest(COMPARE,46)@0
efxGTefy_uid47_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxGTefy_uid47_fpCompareTest_a) - UNSIGNED(efxGTefy_uid47_fpCompareTest_b));
efxGTefy_uid47_fpCompareTest_c(0) <= efxGTefy_uid47_fpCompareTest_o(32);
-- efxLTefy_uid48_fpCompareTest(COMPARE,47)@0
efxLTefy_uid48_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxLTefy_uid48_fpCompareTest_a) - UNSIGNED(efxLTefy_uid48_fpCompareTest_b));
efxLTefy_uid48_fpCompareTest_c(0) <= efxLTefy_uid48_fpCompareTest_o(32);
-- expFracCompMux_uid59_fpCompareTest(MUX,58)@0
expFracCompMux_uid59_fpCompareTest_s <= signX_uid52_fpCompareTest_b;
expFracCompMux_uid59_fpCompareTest_combproc: PROCESS (expFracCompMux_uid59_fpCompareTest_s, efxLTefy_uid48_fpCompareTest_c, efxGTefy_uid47_fpCompareTest_c)
BEGIN
CASE (expFracCompMux_uid59_fpCompareTest_s) IS
WHEN "0" => expFracCompMux_uid59_fpCompareTest_q <= efxLTefy_uid48_fpCompareTest_c;
WHEN "1" => expFracCompMux_uid59_fpCompareTest_q <= efxGTefy_uid47_fpCompareTest_c;
WHEN OTHERS => expFracCompMux_uid59_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xorSigns_uid57_fpCompareTest(LOGICAL,56)@0
xorSigns_uid57_fpCompareTest_q <= signX_uid52_fpCompareTest_b xor signY_uid53_fpCompareTest_b;
-- sxEQsy_uid58_fpCompareTest(LOGICAL,57)@0
sxEQsy_uid58_fpCompareTest_q <= not (xorSigns_uid57_fpCompareTest_q);
-- sxEQsyExpFracCompMux_uid64_fpCompareTest(LOGICAL,63)@0
sxEQsyExpFracCompMux_uid64_fpCompareTest_q <= sxEQsy_uid58_fpCompareTest_q and expFracCompMux_uid59_fpCompareTest_q;
-- r_uid65_fpCompareTest(LOGICAL,64)@0
r_uid65_fpCompareTest_q <= sxEQsyExpFracCompMux_uid64_fpCompareTest_q or rc2_uid63_fpCompareTest_q;
-- cstZeroWF_uid7_fpCompareTest(CONSTANT,6)
cstZeroWF_uid7_fpCompareTest_q <= "00000000000000000000000";
-- fracXIsZero_uid27_fpCompareTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_y_uid24_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid28_fpCompareTest(LOGICAL,27)@0
fracXIsNotZero_uid28_fpCompareTest_q <= not (fracXIsZero_uid27_fpCompareTest_q);
-- cstAllOWE_uid6_fpCompareTest(CONSTANT,5)
cstAllOWE_uid6_fpCompareTest_q <= "11111111";
-- expXIsMax_uid26_fpCompareTest(LOGICAL,25)@0
expXIsMax_uid26_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_y_uid30_fpCompareTest(LOGICAL,29)@0
excN_y_uid30_fpCompareTest_q <= expXIsMax_uid26_fpCompareTest_q and fracXIsNotZero_uid28_fpCompareTest_q;
-- fracXIsZero_uid13_fpCompareTest(LOGICAL,12)@0
fracXIsZero_uid13_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_x_uid10_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid14_fpCompareTest(LOGICAL,13)@0
fracXIsNotZero_uid14_fpCompareTest_q <= not (fracXIsZero_uid13_fpCompareTest_q);
-- expXIsMax_uid12_fpCompareTest(LOGICAL,11)@0
expXIsMax_uid12_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_x_uid16_fpCompareTest(LOGICAL,15)@0
excN_x_uid16_fpCompareTest_q <= expXIsMax_uid12_fpCompareTest_q and fracXIsNotZero_uid14_fpCompareTest_q;
-- oneIsNaN_uid34_fpCompareTest(LOGICAL,33)@0
oneIsNaN_uid34_fpCompareTest_q <= excN_x_uid16_fpCompareTest_q or excN_y_uid30_fpCompareTest_q;
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- rPostExc_uid66_fpCompareTest(MUX,65)@0
rPostExc_uid66_fpCompareTest_s <= oneIsNaN_uid34_fpCompareTest_q;
rPostExc_uid66_fpCompareTest_combproc: PROCESS (rPostExc_uid66_fpCompareTest_s, r_uid65_fpCompareTest_q, GND_q)
BEGIN
CASE (rPostExc_uid66_fpCompareTest_s) IS
WHEN "0" => rPostExc_uid66_fpCompareTest_q <= r_uid65_fpCompareTest_q;
WHEN "1" => rPostExc_uid66_fpCompareTest_q <= GND_q;
WHEN OTHERS => rPostExc_uid66_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xOut(GPOUT,4)@0
q <= rPostExc_uid66_fpCompareTest_q;
END normal;
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4D2A8PTxDzyjA4qKtl+X9A01Y5h3fzBZsnZWOXNkV5+Imqr3EwOqYYIGZ3cNGWUSwVVovtN8DgW+
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I6O9k6cNcFTldkJm4uX7afFE3JPWDhyC+Lm4Bvu1o0bDAQeFE7WHRcmOH2ao6ScD3aBN3UatqZO/
RhAq8wYLuIHaKBSjV2lmmaCsCrgeT2x7gioT7A9I8cgApPYn+PFAPHdiC3+PrrQuKWxMuLPR48Xp
3hshvNJ3dUglpNXOmxo43mFsVVBliRaQqAAyC3QJVLEk0JVpaiKXhnTgWxgj38gUSgnbFGlILliU
Q2DSdOunyDFj2ezy5AP2vNUCxJBgwHvpp/zErzn6nTnq8Ywtg1DJBZ/D4olK/CB4nffK3Nsf+dEH
l9Mpt+TgVe4b3UyAtQaKQP4+uGVIJxgcLsrLLhbfc0dSuB/al++XDUnqA9D8X60RqxMBQ8qmZq1l
6E0cO1e61wSqej6BbrxKyKKOUb6dWPki5SKE72An2Rf42Hal5+rvyQnkFvjbEw+I92s0Sf0ninsL
vuoPJNN2nEcOeK31Ki9zJJ5mkjbsXRaw0ZxyT+dkX9gJNJEZkanLDKTgTEvsD7/hzy5lmQgm1aXz
T/4Ys2NWEHM9z1li5qvr7NBS+Df0PiwpLs9Gc9MmCWR4XpGkVsArOsQkq+U70Bk4YTKMoPwkQ3jh
hmzYiyCGNJ8Xh9lEFadI+MKCeclaNi+Fjk7ef95QHvcDiqkGE6loQBKICfB2OwCocaEGwNp1xoNi
X2dnEgO22z+ymMKW6dmA1b/E/sXynZZ1zVok+B/mwZGnowqthveAFGiYO7zfFaI4WFeX8gO8Dgv1
THEwCeXIU5e/LVhdYhI/xGOVEU8FJ74+emqateqBL0V4nmgd0zTVSIY2quMy4IUvrZZGb1XTvBt3
thrmVk8+A7IYDLE8ot7+XFq66LfLfXC+SlBl+HcdAs+57UqFlJrBCUih7un+viJHRkIOoNxJuGhD
MF5zeOuK2kjN4npfZULfv1YakMyQkKGfTLEzApvkMsZ0/ItujRPDMF8/XqDy31IkcxJHfg==
`protect end_protected
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex6;
constant CFG_MEMTECH : integer := virtex6;
constant CFG_PADTECH : integer := virtex6;
constant CFG_JTAGTECH : integer := virtex6;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/gnss_fw/makefiles/bin/gnssfw.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20191125";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := true;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
apply : in STD_LOGIC;
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 );
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
trigger : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
trigger : in STD_LOGIC;
apply : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC;
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system;
begin
system_i: component system
port map (
apply => apply,
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
state(1 downto 0) => state(1 downto 0),
transform => transform,
transform_led => transform_led,
trigger => trigger,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser is
generic (
BITPATTERN_WIDTH : positive := 32
);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic
);
end serialiser;
-------------------------------------------------------------------------------
architecture behavioural of serialiser is
type serialiser_type is record
counter : integer range 0 to BITPATTERN_WIDTH;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : serialiser_type := (counter => 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
bitstream_out_p <= pattern_in_p(r.counter);
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clk_bit, r)
variable v : serialiser_type;
begin
v := r;
if clk_bit = '1' then
v.counter := v.counter + 1;
if v.counter = BITPATTERN_WIDTH then
v.counter := 0;
end if;
end if;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser is
generic (
BITPATTERN_WIDTH : positive := 32
);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic
);
end serialiser;
-------------------------------------------------------------------------------
architecture behavioural of serialiser is
type serialiser_type is record
counter : integer range 0 to BITPATTERN_WIDTH;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : serialiser_type := (counter => 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
bitstream_out_p <= pattern_in_p(r.counter);
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clk_bit, r)
variable v : serialiser_type;
begin
v := r;
if clk_bit = '1' then
v.counter := v.counter + 1;
if v.counter = BITPATTERN_WIDTH then
v.counter := 0;
end if;
end if;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library verilog;
use verilog.vl_types.all;
entity drive_analog_io is
port(
parallel_in : in vl_logic_vector(63 downto 0);
serial_out : out vl_logic
);
end drive_analog_io;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity FloatAdder is
port (
fltIn1 : in std_logic_vector(31 downto 0);
fltIn2 : in std_logic_vector(31 downto 0);
fltOut : out std_logic_vector(31 downto 0));
end FloatAdder;
architecture FAddImp of FloatAdder is
component FractionLeftPadding
port (
frcIn : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0));
end component;
component FractionRightShifter is
port (
frcIn : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frcOut : out std_logic_vector(23 downto 0);
fstOverOut : out std_logic;
sndOverOut : out std_logic;
tailAnyOut : out std_logic);
end component;
signal sgn1, sgn2 : std_logic;
signal exp1, exp2 : std_logic_vector( 7 downto 0);
signal frc1, frc2 : std_logic_vector(23 downto 0);
signal isAdd : boolean;
signal lenRawSft : std_logic_vector(8 downto 0);
signal lenSft : std_logic_vector(4 downto 0);
signal validPosSft, validNegSft : boolean;
signal zeroSft, posSft : boolean;
signal sgnSup, sgnInf : std_logic;
signal expUnif : std_logic_vector(7 downto 0);
signal frcInf : std_logic_vector(23 downto 0);
signal frcUnifSup, frcUnifInf : std_logic_vector(23 downto 0);
signal fstOver, sndOver, tailAny : std_logic;
signal roundFurther, roundFurtherDbl, roundFurtherHlf : std_logic;
signal frcOutAdder1, frcOutAdder2 : std_logic_vector(24 downto 0);
signal noFlow, noDown : boolean;
signal frcIreg : std_logic_vector(23 downto 0);
signal nlz : std_logic_vector(4 downto 0);
signal downFrc : std_logic;
signal expOutSubRaw : std_logic_vector(8 downto 0);
signal expOutAdd, expOutSub : std_logic_vector( 7 downto 0);
signal frcOutAdd, frcOutSub : std_logic_vector(23 downto 0);
signal sgnOutSub: std_logic;
begin
sgn1 <= fltIn1(31);
exp1 <= fltIn1(30 downto 23);
frc1 <= '1' & fltIn1(22 downto 0);
sgn2 <= fltIn2(31);
exp2 <= fltIn2(30 downto 23);
frc2 <= '1' & fltIn2(22 downto 0);
lenRawSft <= ('0' & exp1) - ('0' & exp2);
validPosSft <= lenRawSft(8 downto 5) = "0000";
zeroSft <= validPosSft and lenRawSft(4 downto 0) = "00000";
validNegSft <= lenRawSft(8 downto 5) = "1111" and lenRawSft(4 downto 0) /= "00000";
posSft <= lenRawSft(8) = '0';
lenSft <= lenRawSft(4 downto 0) when validPosSft else
"00000"-(lenRawSft(4 downto 0)) when validNegSft else
"11111";
sgnSup <= sgn1 when posSft else sgn2;
sgnInf <= sgn2 when posSft else sgn1;
expUnif <= exp1 when posSft else exp2;
frcUnifSup <= frc1 when posSft else frc2;
frcInf <= frc2 when posSft else frc1;
sftUnifFrc: FractionRightShifter port map (
frcIn => frcInf,
len => lenSft,
frcOut => frcUnifInf,
fstOverOut => fstOver,
sndOverOut => sndOver,
tailAnyOut => tailAny);
roundFurtherHlf <= sndOver and (tailAny or fstOver);
roundFurther <= fstOver and ((sndOver or tailAny) or (frcUnifSup(0) xor frcUnifInf(0)));
roundFurtherDbl <= (frcUnifSup(0) and frcUnifInf(0)) or
( (frcUnifSup(0) or frcUnifInf(0)) and
(((fstOver or sndOver) or tailAny) or (frcUnifSup(1) xor frcUnifInf(1))));
isAdd <= sgn1 = sgn2;
frcOutAdder1 <= ('0' & frcUnifSup) + ('0' & frcUnifInf) + roundFurther when isAdd else
('0' & frcUnifSup) - ('0' & frcUnifInf) - roundFurther;
frcOutAdder2 <= ("00" & (frcUnifSup(23 downto 1))) + ("00" & (frcUnifInf(23 downto 1))) + roundFurtherDbl when isAdd else
('0' & frcUnifInf) - ('0' & frcUnifSup) - roundFurther when zeroSft else
('0' & (frcUnifSup(22 downto 0)) & '0') - ('0' & (frcUnifInf(22 downto 0) & fstOver)) - roundFurtherHlf;
noFlow <= frcOutAdder1(24) = '0';
noDown <= frcOutAdder1(23) = '1';
expOutAdd <= expUnif when noFlow else expUnif+1;
frcOutAdd <= (others => '0') when expOutAdd = "11111111" else
frcOutAdder1(23 downto 0) when noFlow else
frcOutAdder2(23 downto 0);
sgnOutSub <= sgnSup when not zeroSft or noFlow else sgnInf;
frcIreg <= frcOutAdder1(23 downto 0) when zeroSft and noFlow else
frcOutAdder2(23 downto 0) when zeroSft and not noFlow else
frcOutAdder1(23 downto 0) when noDown else
frcOutAdder2(23 downto 0);
padFrcIreg: FractionLeftPadding port map (
frcIn => frcIreg,
nlz => nlz,
frcOut => frcOutSub);
downFrc <= '0' when zeroSft or noDown else '1';
expOutSubRaw <= ('0' & expUnif) - ("0000" & nlz) - downFrc;
expOutSub <= expOutSubRaw(7 downto 0) when expOutSubRaw(8) = '0' else "00000000";
fltOut <= sgnSup & expOutAdd & frcOutAdd(22 downto 0) when isAdd else
sgnOutSub & expOutSub & frcOutSub(22 downto 0);
end FAddImp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package mem_pkg is
type mem_in is record
alu_out : word;
rf_we : std_logic;
insn_type : insn_type_t;
rd_addr : std_logic_vector(4 downto 0);
end record mem_in;
type mem_out is record
data_addr : word;
we : std_logic;
re : std_logic;
data_out : word;
end record mem_out;
end package mem_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package mem_pkg is
type mem_in is record
alu_out : word;
rf_we : std_logic;
insn_type : insn_type_t;
rd_addr : std_logic_vector(4 downto 0);
end record mem_in;
type mem_out is record
data_addr : word;
we : std_logic;
re : std_logic;
data_out : word;
end record mem_out;
end package mem_pkg;
|
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_16 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 12.288 -fclkop 196.608 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -rst -fb_mode 1
-- Sat Jun 2 11:04:49 2018
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO3L;
use MACHXO3L.components.all;
-- synopsys translate_on
entity pll_16 is
port (
CLKI: in std_logic;
RST: in std_logic;
CLKOP: out std_logic);
end pll_16;
architecture Structure of pll_16 is
-- internal signal declarations
signal LOCK: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VLO
port (Z: out std_logic);
end component;
component EHXPLLJ
generic (INTFB_WAKE : in String; DDRST_ENA : in String;
DCRST_ENA : in String; MRST_ENA : in String;
PLLRST_ENA : in String; DPHASE_SOURCE : in String;
STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
OUTDIVIDER_MUXC2 : in String;
OUTDIVIDER_MUXB2 : in String;
OUTDIVIDER_MUXA2 : in String;
PREDIVIDER_MUXD1 : in Integer;
PREDIVIDER_MUXC1 : in Integer;
PREDIVIDER_MUXB1 : in Integer;
PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
PLL_LOCK_MODE : in Integer;
CLKOS_TRIM_DELAY : in Integer;
CLKOS_TRIM_POL : in String;
CLKOP_TRIM_DELAY : in Integer;
CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
FRACN_ENABLE : in String; FEEDBK_PATH : in String;
CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
port (CLKI: in std_logic; CLKFB: in std_logic;
PHASESEL1: in std_logic; PHASESEL0: in std_logic;
PHASEDIR: in std_logic; PHASESTEP: in std_logic;
LOADREG: in std_logic; STDBY: in std_logic;
PLLWAKESYNC: in std_logic; RST: in std_logic;
RESETM: in std_logic; RESETC: in std_logic;
RESETD: in std_logic; ENCLKOP: in std_logic;
ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
ENCLKOS3: in std_logic; PLLCLK: in std_logic;
PLLRST: in std_logic; PLLSTB: in std_logic;
PLLWE: in std_logic; PLLADDR4: in std_logic;
PLLADDR3: in std_logic; PLLADDR2: in std_logic;
PLLADDR1: in std_logic; PLLADDR0: in std_logic;
PLLDATI7: in std_logic; PLLDATI6: in std_logic;
PLLDATI5: in std_logic; PLLDATI4: in std_logic;
PLLDATI3: in std_logic; PLLDATI2: in std_logic;
PLLDATI1: in std_logic; PLLDATI0: in std_logic;
CLKOP: out std_logic; CLKOS: out std_logic;
CLKOS2: out std_logic; CLKOS3: out std_logic;
LOCK: out std_logic; INTLOCK: out std_logic;
REFCLK: out std_logic; CLKINTFB: out std_logic;
DPHSRC: out std_logic; PLLACK: out std_logic;
PLLDATO7: out std_logic; PLLDATO6: out std_logic;
PLLDATO5: out std_logic; PLLDATO4: out std_logic;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic);
end component;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "196.608000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "12.288000";
attribute ICP_CURRENT of PLLInst_0 : label is "9";
attribute LPF_RESISTOR of PLLInst_0 : label is "8";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLJ
generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
MRST_ENA=> "DISABLED", PLLRST_ENA=> "ENABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 2,
PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
CLKOS_DIV=> 1, CLKOP_DIV=> 3, CLKFB_DIV=> 16, CLKI_DIV=> 1,
FEEDBK_PATH=> "CLKOP")
port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
PLLWAKESYNC=>scuba_vlo, RST=>RST, RESETM=>scuba_vlo,
RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
PLLDATO1=>open, PLLDATO0=>open);
CLKOP <= CLKOP_t;
end Structure;
-- synopsys translate_off
library MACHXO3L;
configuration Structure_CON of pll_16 is
for Structure
for all:VLO use entity MACHXO3L.VLO(V); end for;
for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for;
end for;
end Structure_CON;
-- synopsys translate_on
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: KeyToFreqROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY KeyToFreqROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (28 DOWNTO 0)
);
END KeyToFreqROM;
ARCHITECTURE SYN OF keytofreqrom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (28 DOWNTO 0);
BEGIN
q <= sub_wire0(28 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 29,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "29"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../GITROOT/MusicBoxNano/matlab/KeyToFreqMidi.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "29"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 29 0 OUTPUT NODEFVAL "q[28..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 29 0 @q_a 0 0 29 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL KeyToFreqROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
----------------------------------------------------------------------------------
--
-- Generate a single SID voice
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sid_voice is port (
clk1M : in std_logic;
freq : in unsigned (15 downto 0);
pw : in unsigned (11 downto 0);
wvfm : in std_logic_vector (3 downto 0);
test : in std_logic;
rmod : in std_logic;
sync : in std_logic;
gate : in std_logic;
enva : in unsigned (3 downto 0);
envd : in unsigned (3 downto 0);
envs : in unsigned (3 downto 0);
envr : in unsigned (3 downto 0);
envo : out unsigned (7 downto 0);
osco : out unsigned (7 downto 0);
uout : out unsigned (7 downto 0)
);
end sid_voice;
architecture sid_voice_impl of sid_voice is
subtype u8 is unsigned (7 downto 0);
subtype byte is std_logic_vector (7 downto 0);
subtype u9 is unsigned (8 downto 0);
subtype u12 is unsigned (11 downto 0);
subtype word is std_logic_vector (15 downto 0);
subtype u17 is unsigned (16 downto 0);
subtype u23 is unsigned (22 downto 0);
subtype u24 is unsigned (23 downto 0);
subtype word24 is std_logic_vector (23 downto 0);
subtype dword is std_logic_vector (31 downto 0);
signal count24 : u24 := x"000000";
signal lfsr : word := x"1337";
signal chg_ph : std_logic;
signal taps : std_logic;
signal wv_tri : u8;
signal wv_saw : u8;
signal wv_pul : u8;
signal wv_wht : u8;
signal wv_raw : u8;
signal env : u9;
signal wv_mul : u17;
-- pipelining
signal wv_raw_reg : u8;
signal env_reg : u9;
begin
NCO: process(clk1M, freq, test, count24) is
variable cur : u24;
begin
if (test='1') then
count24 <= x"000000";
--count24 <= "000" & x"00000";
chg_ph <= '0';
else
if (rising_edge(clk1M)) then
cur := count24;
cur := cur + freq;
chg_ph <= cur(23) xor count24(23);
--chg_ph <= cur(22) xor count24(22);
count24 <= cur;
end if;
end if;
end process NCO;
taps <= ((lfsr(0) xor lfsr(2)) xor lfsr(3)) xor lfsr(5);
noise: process(clk1M,test,chg_ph,taps,lfsr(15 downto 0)) is
begin
if (test='1') then
lfsr <= x"1337";
else
if (rising_edge(clk1M) and chg_ph='1') then
lfsr <= taps & lfsr(15 downto 1);
end if;
end if;
end process noise;
gen_tri: process(count24) is
variable calc : byte;
begin
for i in 0 to 6 loop
calc(i+1) := count24(16+i) xor count24(23);
--calc(i+1) := count24(15+i) xor count24(22);
end loop;
calc(0) := count24(23);
--calc(0) := count24(22);
wv_tri <= u8(calc);
end process gen_tri;
gen_saw: process(count24(22 downto 15)) is
begin
wv_saw <= count24(23 downto 16);
--wv_saw <= count24(22 downto 15);
end process gen_saw;
gen_pul: process(count24(22 downto 11),pw) is
variable sample : u12;
begin
sample := count24(23 downto 12);
--sample := count24(22 downto 11);
if ((pw = x"fff") or (sample < pw)) then
wv_pul <= x"ff";
else
wv_pul <= x"00";
end if;
end process gen_pul;
gen_wht: process(lfsr) is
begin
wv_wht <= lfsr(15) & lfsr(14) & lfsr(10) & lfsr( 9) &
lfsr( 5) & lfsr( 4) & lfsr( 3) & lfsr( 0);
end process gen_wht;
-- Handling of waveform selection signals
--
-- The ANDing of multiple waveforms when
-- multiple signals are on is supported
-- (excluding noise).
--
-- We are not replicating the noise-lock bug
-- when noise is combined with other waveforms
-- and c64 programs don't combine noise due to
-- this bug so it's not worthwhile to do so.
with wvfm select wv_raw <=
x"80" when "0000",
wv_tri when "0001",
wv_saw when "0010",
wv_tri and wv_saw when "0011",
wv_pul when "0100",
wv_pul and wv_tri when "0101",
wv_pul and wv_saw when "0110",
wv_pul and wv_tri and wv_saw when "0111",
wv_wht when others;
hold_wvraw: process(clk1M,wv_raw) is
begin
if (rising_edge(clk1M)) then
wv_raw_reg <= wv_raw;
end if;
end process hold_wvraw;
-- TODO: envelope generation
env <= '0' & x"ff";
hold_env: process(clk1M,env) is
begin
if (rising_edge(clk1M)) then
env_reg <= env+1;
end if;
end process hold_env;
hold_vmult: process(clk1M, env_reg, wv_raw_reg) is
begin
if (rising_edge(clk1M)) then
wv_mul <= env_reg * wv_raw_reg;
end if;
end process hold_vmult;
uout <= wv_mul(15 downto 8);
envo <= env_reg(7 downto 0);
osco <= wv_raw_reg;
end sid_voice_impl;
|
----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer:
-- -------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ControlUnit is
Port (
CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_RESET : out STD_LOGIC;
PC_OE : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_LD : out STD_LOGIC;
SP_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SP_RESET : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
REG_IMMED_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OPY_SEL : out STD_LOGIC; -- DOESN'T DO ANYTHING RIGHT NOW!! CHECK ME!!
SCR_WR : out STD_LOGIC;
SCR_OE : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
C_FLAG_SEL : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
SHAD_C_LD : out STD_LOGIC;
Z_FLAG_SEL : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC;
Z_FLAG_SET : out STD_LOGIC;
Z_FLAG_CLR : out STD_LOGIC;
SHAD_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
IO_OE : out STD_LOGIC);
end ControlUnit;
architecture Behavioral of ControlUnit is
-- State machine signals
type state_type is (ST_init, ST_fet, ST_exec, ST_int);
signal PS,NS : state_type;
-- Opcode
signal sig_OPCODE_7: std_logic_vector (6 downto 0);
begin
-- Assign next state
sync_p: process (CLK, NS, RST)
begin
if (RST = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
-- Translate instruction to signals
comb_p: process (OPCODE_HI_5, OPCODE_LO_2, sig_OPCODE_7, C, Z, PS, NS, INT) begin
sig_OPCODE_7 <= OPCODE_HI_5 & OPCODE_LO_2;
case PS is
-- STATE: the init cycle ------------------------------------
when ST_init =>
NS <= ST_fet;
-- Initialize all control outputs to non-active states and reset the PC and SP to all zeros.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '1'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '1';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the fetch cycle -----------------------------------
when ST_fet =>
NS <= ST_exec;
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '1';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if (INT = '1') then
NS <= ST_int;
else
NS <= ST_fet;
end if;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
if (sig_OPCODE_7 = "0000100") then -- ADD reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10100" ) then -- ADD reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0000";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000101") then -- ADDC reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10101" ) then -- ADDC reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000000") then -- AND reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10000" ) then -- AND reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0101";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100100") then -- ASR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1101";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0010101") then -- BRCC
if (c = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010100") then -- BRCS
if (c = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010010") then -- BREQ
if (Z = '1') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010000") then -- BRN
PC_LD <= '1';
elsif (sig_OPCODE_7 = "0010011") then -- BRNE
if (Z = '0') then
PC_LD <= '1';
end if;
elsif (sig_OPCODE_7 = "0010001") then -- CALL
PC_LD <= '1';
PC_OE <= '1';
SP_LD <= '1';
SP_MUX_SEL <= "10";
SCR_ADDR_SEL <= "11";
SCR_WR <= '1';
elsif (sig_OPCODE_7 = "0110000") then -- CLC
C_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110101") then -- CLI (INT)
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0001000") then -- CMP reg-reg
RF_OE <= '1';
ALU_SEL <= "0100";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11000" ) then -- CMP reg-immed
RF_OE <= '1';
ALU_SEL <= "0100";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000010") then -- EXOR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10010" ) then -- EXOR reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0111";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11001" ) then -- IN
RF_WR <= '1';
RF_WR_SEL <= "11";
elsif (sig_OPCODE_7 = "0001010") then -- LD reg-reg
SCR_OE <= '1';
SCR_ADDR_SEL <= "00";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (OPCODE_HI_5 = "11100" ) then -- LD reg-immed
SCR_OE <= '1';
SCR_ADDR_SEL <= "01";
RF_WR <= '1';
RF_WR_SEL <= "01";
elsif (sig_OPCODE_7 = "0100000") then -- LSL
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1001";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100001") then -- LSR
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0001001") then -- MOV reg-reg
RF_WR <= '1';
RF_OE <= '0';
ALU_SEL <= "1110";
elsif (OPCODE_HI_5 = "11011" ) then -- MOV reg-immed
RF_WR <= '1';
ALU_SEL <= "1110";
REG_IMMED_SEL <= '1';
elsif (sig_OPCODE_7 = "0000001") then -- OR reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0110";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10001" ) then -- OR reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0110";
REG_IMMED_SEL <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "11010" ) then -- OUT
RF_OE <= '1';
IO_OE <= '1';
elsif (sig_OPCODE_7 = "0100110") then -- POP
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
RF_WR <= '1';
RF_WR_SEL <= "01";
SP_MUX_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0100101") then -- PUSH
RF_OE <= '1';
SCR_WR <= '1';
SCR_ADDR_SEL <= "11";
SP_MUX_SEL <= "10";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110010") then -- RET
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
elsif (sig_OPCODE_7 = "0110110") then -- RETID (INT)
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
I_FLAG_CLR <= '1';
elsif (sig_OPCODE_7 = "0110111") then -- RETIE (INT)
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
PC_MUX_SEL <= "01";
PC_LD <= '1';
SP_MUX_SEL <= "11";
SP_LD <= '1';
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0100010") then -- ROL
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1011";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0100011") then -- ROR
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "1100";
Z_FLAG_LD <= '1';
C_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0110001") then -- SEC
C_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0110100") then -- SEI (INT)
I_FLAG_SET <= '1';
elsif (sig_OPCODE_7 = "0001011") then -- ST reg-reg
RF_OE <= '1';
SCR_WR <= '1';
elsif (OPCODE_HI_5 = "11101" ) then -- ST reg-immed
RF_OE <= '1';
SCR_WR <= '1';
SCR_ADDR_SEL <= "01";
elsif (sig_OPCODE_7 = "0000110") then -- SUB reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0010";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10110" ) then -- SUB reg-immed
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0010";
REG_IMMED_SEL <= '1';
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000111") then -- SUBC reg-reg
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10111" ) then -- SUBC reg-immed
REG_IMMED_SEL <= '1';
RF_WR <= '1';
RF_OE <= '1';
ALU_SEL <= "0011";
C_FLAG_LD <= '1';
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0000011") then -- TEST reg-reg
RF_OE <= '1';
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (OPCODE_HI_5 = "10011" ) then -- TEST reg-immed
REG_IMMED_SEL <= '1';
RF_OE <= '1';
ALU_SEL <= "1000";
Z_FLAG_LD <= '1';
elsif (sig_OPCODE_7 = "0101000") then -- WSP
RF_OE <= '1';
SP_MUX_SEL <= "00";
SP_LD <= '1';
else
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end if;
when ST_int =>
NS <= ST_fet;
-- Repeat the default block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
PC_LD <= '1'; PC_MUX_SEL <= "10"; PC_RESET <= '0'; PC_OE <= '1'; PC_INC <= '0';
SP_LD <= '1'; SP_MUX_SEL <= "10"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '1'; SCR_OE <= '0'; SCR_ADDR_SEL <= "11";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '1'; IO_OE <= '0';
when others =>
NS <= ST_fet;
-- repeat the default block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_RESET <= '0'; PC_OE <= '0'; PC_INC <= '0';
SP_LD <= '0'; SP_MUX_SEL <= "00"; SP_RESET <= '0';
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
REG_IMMED_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00";
C_FLAG_SEL <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; SHAD_C_LD <= '0';
Z_FLAG_SEL <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; SHAD_Z_LD <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; IO_OE <= '0';
--WRITE_STROBE <= '0'; READ_STROBE <= '0';
end case;
end process comb_p;
end Behavioral; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_2pole is
port ( terminal in_pos, in_neg, output : electrical );
end entity opamp_2pole;
----------------------------------------------------------------
architecture dot of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole
constant fp2 : real := 9.0e5; -- second pole
constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant
constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_in == (tp1 * tp2) * v_out'dot'dot / A
+ (tp1 + tp2) * v_out'dot / A + v_out / A;
end architecture dot;
----------------------------------------------------------------
architecture ltf of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole (Hz)
constant fp2 : real := 9.0e5; -- second pole (Hz)
constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s)
constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s)
constant num : real_vector := (0 => wp1 * wp2 * A);
constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_out == v_in'ltf(num, den);
end architecture ltf;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_2pole is
port ( terminal in_pos, in_neg, output : electrical );
end entity opamp_2pole;
----------------------------------------------------------------
architecture dot of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole
constant fp2 : real := 9.0e5; -- second pole
constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant
constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_in == (tp1 * tp2) * v_out'dot'dot / A
+ (tp1 + tp2) * v_out'dot / A + v_out / A;
end architecture dot;
----------------------------------------------------------------
architecture ltf of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole (Hz)
constant fp2 : real := 9.0e5; -- second pole (Hz)
constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s)
constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s)
constant num : real_vector := (0 => wp1 * wp2 * A);
constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_out == v_in'ltf(num, den);
end architecture ltf;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_2pole is
port ( terminal in_pos, in_neg, output : electrical );
end entity opamp_2pole;
----------------------------------------------------------------
architecture dot of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole
constant fp2 : real := 9.0e5; -- second pole
constant tp1 : real := 1.0 / (fp1 * math_2_pi); -- first time constant
constant tp2 : real := 1.0 / (fp2 * math_2_pi); -- second time constant
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_in == (tp1 * tp2) * v_out'dot'dot / A
+ (tp1 + tp2) * v_out'dot / A + v_out / A;
end architecture dot;
----------------------------------------------------------------
architecture ltf of opamp_2pole is
constant A : real := 1.0e6; -- open loop gain
constant fp1 : real := 5.0; -- first pole (Hz)
constant fp2 : real := 9.0e5; -- second pole (Hz)
constant wp1 : real := fp1 * math_2_pi; -- first pole (rad/s)
constant wp2 : real := fp2 * math_2_pi; -- second pole (rad/s)
constant num : real_vector := (0 => wp1 * wp2 * A);
constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
quantity v_in across in_pos to in_neg;
quantity v_out across i_out through output;
begin
v_out == v_in'ltf(num, den);
end architecture ltf;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s03b00x00p02n01i03024pkg is
type T is (one,two);
end c11s03b00x00p02n01i03024pkg;
ENTITY c11s03b00x00p02n01i03024ent IS
END c11s03b00x00p02n01i03024ent;
ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
signal S : boolean;
BEGIN
TESTING: PROCESS
BEGIN
S <= TRUE;
wait for 3 ns;
assert NOT( S = TRUE )
report "***PASSED TEST: c11s03b00x00p02n01i03024"
severity NOTE;
assert ( S = TRUE )
report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s03b00x00p02n01i03024arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s03b00x00p02n01i03024pkg is
type T is (one,two);
end c11s03b00x00p02n01i03024pkg;
ENTITY c11s03b00x00p02n01i03024ent IS
END c11s03b00x00p02n01i03024ent;
ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
signal S : boolean;
BEGIN
TESTING: PROCESS
BEGIN
S <= TRUE;
wait for 3 ns;
assert NOT( S = TRUE )
report "***PASSED TEST: c11s03b00x00p02n01i03024"
severity NOTE;
assert ( S = TRUE )
report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s03b00x00p02n01i03024arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c11s03b00x00p02n01i03024pkg is
type T is (one,two);
end c11s03b00x00p02n01i03024pkg;
ENTITY c11s03b00x00p02n01i03024ent IS
END c11s03b00x00p02n01i03024ent;
ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
signal S : boolean;
BEGIN
TESTING: PROCESS
BEGIN
S <= TRUE;
wait for 3 ns;
assert NOT( S = TRUE )
report "***PASSED TEST: c11s03b00x00p02n01i03024"
severity NOTE;
assert ( S = TRUE )
report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s03b00x00p02n01i03024arch;
|
-----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "A007601FA0066041A0056049A0046099A003600DA0026025A001609FA0006003";
attribute INIT_01 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000008100A0096009A0086001";
attribute INIT_02 of ram_1024_x_18 : label is "4B834E824E12818A020050407001A0006F006E006D006B0B6A07630062006100";
attribute INIT_03 of ram_1024_x_18 : label is "810181F0A00343698D0A81B88201A1D8CD0A4D09620081584A834E824E1A8229";
attribute INIT_04 of ram_1024_x_18 : label is "82333D0082433C008253DB017B0FDC017C0FDD017DFF81A86100822301324140";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000008002";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of ram_1024_x_18 : label is "81F8000000000000000000000000000000000000000000000000000000000000";
attribute INITP_00 of ram_1024_x_18 : label is "000000000000000000000001222EECCF84888CF0F0FDFFFF000000FFFFFFFFFF";
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"A007601FA0066041A0056049A0046099A003600DA0026025A001609FA0006003",
INIT_01 => X"000000000000000000000000000000000000000000008100A0096009A0086001",
INIT_02 => X"4B834E824E12818A020050407001A0006F006E006D006B0B6A07630062006100",
INIT_03 => X"810181F0A00343698D0A81B88201A1D8CD0A4D09620081584A834E824E1A8229",
INIT_04 => X"82333D0082433C008253DB017B0FDC017C0FDD017DFF81A86100822301324140",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000008002",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"81F8000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"000000000000000000000001222EECCF84888CF0F0FDFFFF000000FFFFFFFFFF",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:04 wig Exp $
-- $Date: 2006/04/10 15:42:04 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:04 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ebb_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ebc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
;
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
;
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
;
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TxSample is
Port ( Txck : in STD_LOGIC;
Txen : out STD_LOGIC;
Tx0 : out STD_LOGIC;
Tx1 : out STD_LOGIC;
Tx2 : out STD_LOGIC;
Tx3 : out STD_LOGIC;
Rx0 : in STD_LOGIC;
Rx1 : in STD_LOGIC;
Rx2 : in STD_LOGIC;
Rx3 : in STD_LOGIC;
Rxdv : in STD_LOGIC;
Rxer: in STD_LOGIC;
Phynrst : out STD_LOGIC;
Mainck: in STD_LOGIC;
Button: in STD_LOGIC;
Main_rst: in STD_LOGIC;
Led0: out STD_LOGIC;
Led1: out STD_LOGIC);
end TxSample;
architecture Behavioral of TxSample is
signal phy_ok: std_logic;
signal txrq: std_logic;
signal s_txrq: std_logic;
signal s1_txrq: std_logic;
signal tx_run: std_logic;
signal s1_tx_run: std_logic;
signal s_tx_run: std_logic;
signal s1_button: std_logic;
signal s_button: std_logic;
signal reset_counter: std_logic_vector (24 downto 0);
signal state: std_logic_vector (7 downto 0);
signal debounced_button: std_logic;
signal prev_button: std_logic;
signal stable_counter: std_logic_vector (24 downto 0);
signal prev_debounced_button: std_logic;
signal Main_nrst: std_logic;
begin
Main_nrst <= not Main_rst;
Led1 <= Main_nrst;
resetwait: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
reset_counter <= (others => '0');
elsif (Mainck'event AND Mainck = '1') then
reset_counter <= std_logic_vector(unsigned(reset_counter) + 1);
end if;
end process;
resetphy: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
Phynrst <= '0';
phy_ok <= '0';
elsif (Mainck'event AND Mainck = '1') then
if (unsigned(reset_counter) = 100000) then
Phynrst <= '1';
end if;
if (unsigned(reset_counter) = 110000) then
phy_ok <= '1';
end if;
end if;
end process;
debouncer: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
debounced_button <= '0';
stable_counter <= (others => '0');
prev_button <= '0';
elsif (Mainck'event AND Mainck = '1') then
if (s_button = prev_button) then
-- stable for 80mS
if (unsigned(stable_counter) = x"3fffff") then
stable_counter <= (others => '0');
debounced_button <= s_button;
else
stable_counter <= std_logic_vector(unsigned(stable_counter) + 1);
end if;
else
stable_counter <= (others => '0');
end if;
prev_button <= s_button;
end if;
end process;
trigger: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
txrq <= '0';
prev_debounced_button <= '0';
elsif (Mainck'event and Mainck = '1') then
if (phy_ok = '1' and debounced_button = '1' and prev_debounced_button = '0' and s_tx_run = '0') then
txrq <= '1';
elsif (s_tx_run = '1') then
txrq <= '0';
end if;
prev_debounced_button <= debounced_button;
end if;
end process;
sync_Mainck: process(Mainck, Main_nrst)
begin
if (Main_nrst = '0') then
s_button <= '0';
s_tx_run <= '0';
s1_button <= '0';
s1_tx_run <= '0';
elsif (Mainck'event AND Mainck = '1') then
-- s1_txrq <= txrq;
-- s_txrq <= s1_txrq;
s1_button <= Button;
s_button <= s1_button;
s1_tx_run <= tx_run;
s_tx_run <= s1_tx_run;
end if;
end process;
sync_Txck: process(Txck, Main_nrst)
begin
if (Main_nrst = '0') then
s_txrq <= '0';
s1_txrq <= '0';
elsif (Txck'event and Txck = '1') then
s1_txrq <= txrq;
s_txrq <= s1_txrq;
end if;
end process;
ethtransmitter: process(Txck, Main_nrst)
begin
if (Main_nrst = '0') then
state <= (others => '0');
tx_run <= '0' ;
Led0 <= '0';
Txen <= '0';
Tx0 <= '0';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0';
elsif(Txck'event AND Txck = '0') then
if(s_txrq = '1' and tx_run = '0') then
tx_run <= '1';
state <= (others => '0');
Led0 <= '1';
end if;
if(tx_run = '1') then
if(unsigned(state) < 15) then --15
Txen <= '1';
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '1';
Tx3 <= '0';
elsif (unsigned(state) = 15 ) then --16
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '1';
Tx3 <= '1';
elsif (unsigned(state) > 15 AND unsigned(state) < (15+13)) then --12
Tx0 <= '1';
Tx1 <= '1';
Tx2 <= '1';
Tx3 <= '1';
elsif (unsigned(state) = (15+13)) then --7
Tx0 <= '1';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0'; --12+129 orig --12+4 -- 5 is discarded by atl1e
elsif (unsigned(state) > (15+12) AND unsigned(state) < (15 + 13 + 10)) then
Tx0 <= '0';
Tx1 <= '0';
Tx2 <= '0';
Tx3 <= '0';
elsif (unsigned(state) < (15 + 13 + 10 + 10)) then -- IFS
Txen <= '0';
else
Led0 <= '0';
tx_run <= '0';
end if;
state <= std_logic_vector(unsigned(state) + 1);
end if; -- tx_run
end if; -- ck
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2911.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02911ent IS
END c02s01b01x02p03n01i02911ent;
ARCHITECTURE c02s01b01x02p03n01i02911arch OF c02s01b01x02p03n01i02911ent IS
procedure proc1 (signal S1: inout bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02911 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02911arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2911.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02911ent IS
END c02s01b01x02p03n01i02911ent;
ARCHITECTURE c02s01b01x02p03n01i02911arch OF c02s01b01x02p03n01i02911ent IS
procedure proc1 (signal S1: inout bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02911 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02911arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2911.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02911ent IS
END c02s01b01x02p03n01i02911ent;
ARCHITECTURE c02s01b01x02p03n01i02911arch OF c02s01b01x02p03n01i02911ent IS
procedure proc1 (signal S1: inout bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02911 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02911arch;
|
use work.testtest_pkg.all; -- Missing
package test2_pkg is
type t_test is protected
procedure test_proc;
end protected;
end package;
package body test2_pkg is
type t_test is protected body
procedure test_proc is
alias a_test_val is test_val.rec_val;
begin
a_test_val := 1;
end procedure;
end protected body;
end package body;
|
component logo is
port (
a,b,c : in bit_vector(1 downto 0);
x,y : out bit_vector(1 downto 0)
);
end component;
|
component logo is
port (
a,b,c : in bit_vector(1 downto 0);
x,y : out bit_vector(1 downto 0)
);
end component;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04800_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Finite State Machine two processes based: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_04800_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_04800_good;
--CODE
architecture Behavioral of CNE_04800_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
signal sm_Next_State : t_state; -- Next state
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
Counter:pkg_Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
-- Process registration
P_FSM_State_Reg:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
sm_State <= init;
elsif (rising_edge(i_Clock)) then
sm_State <= sm_Next_State;
end if;
end process;
-- Outputs assertion
P_FSM_Output:process(sm_State, i_Start, i_Stop, End_Count)
begin
Raz <= '0';
Enable <= '0';
Length <= c_Length; -- Set the length value
case sm_State is
when init =>
sm_Next_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_Next_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
sm_Next_State <= enabled;
else
sm_Next_State <= finished;
end if;
when others =>
sm_Next_State <= init;
end case;
end process;
end Behavioral;
--CODE |
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic := '0';
duty_count_out : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
reset : in std_logic := '0' -- reset
);
end entity pwm_decoder;
architecture decode of pwm_decoder is
begin
inc: process(clock, reset)
variable period : std_logic_vector(31 downto 0) := "00000000000000011000111010011000";
variable duty_count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
if(reset = '1') then
duty_count := "00000000000000000000000000000000";
count := "00000000000000000000000000000000";
elsif(rising_edge(clock)) then
if(unsigned(count) = unsigned(period) - 1) then
duty_count_out <= duty_count;
count := "00000000000000000000000000000000";
duty_count := "00000000000000000000000000000000";
else
if(pwm_in = '1') then
duty_count := std_logic_vector(unsigned(duty_count) + 1);
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
end architecture decode; -- of pwm_decoder
|
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic := '0';
duty_count_out : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
reset : in std_logic := '0' -- reset
);
end entity pwm_decoder;
architecture decode of pwm_decoder is
begin
inc: process(clock, reset)
variable period : std_logic_vector(31 downto 0) := "00000000000000011000111010011000";
variable duty_count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
if(reset = '1') then
duty_count := "00000000000000000000000000000000";
count := "00000000000000000000000000000000";
elsif(rising_edge(clock)) then
if(unsigned(count) = unsigned(period) - 1) then
duty_count_out <= duty_count;
count := "00000000000000000000000000000000";
duty_count := "00000000000000000000000000000000";
else
if(pwm_in = '1') then
duty_count := std_logic_vector(unsigned(duty_count) + 1);
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
end architecture decode; -- of pwm_decoder
|
-- pwm_decoder.vhd
-- Author: Fred
-- Status: Tested and passed
-- Works with 490Hz Arduino PWM
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pwm_decoder is
port (
clock : in std_logic := '0'; -- clock
pwm_in : in std_logic := '0';
duty_count_out : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
reset : in std_logic := '0' -- reset
);
end entity pwm_decoder;
architecture decode of pwm_decoder is
begin
inc: process(clock, reset)
variable period : std_logic_vector(31 downto 0) := "00000000000000011000111010011000";
variable duty_count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
variable count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
if(reset = '1') then
duty_count := "00000000000000000000000000000000";
count := "00000000000000000000000000000000";
elsif(rising_edge(clock)) then
if(unsigned(count) = unsigned(period) - 1) then
duty_count_out <= duty_count;
count := "00000000000000000000000000000000";
duty_count := "00000000000000000000000000000000";
else
if(pwm_in = '1') then
duty_count := std_logic_vector(unsigned(duty_count) + 1);
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
end architecture decode; -- of pwm_decoder
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:55 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_stub.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_0_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_0_0;
architecture stub of system_ov7670_controller_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02464ent IS
END c07s03b02x02p03n02i02464ent;
ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := (1 => '0', others => '1');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02464"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02464arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02464ent IS
END c07s03b02x02p03n02i02464ent;
ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := (1 => '0', others => '1');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02464"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02464arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02464ent IS
END c07s03b02x02p03n02i02464ent;
ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := (1 => '0', others => '1');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02464"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02464arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity hello is
generic (constant l : natural := 8);
port (a : in std_logic_vector (l - 1 downto 0));
end hello;
architecture behav of hello is
signal clk : std_logic;
signal q : std_logic_vector (l - 1 downto 0);
begin
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process (clk)
begin
if rising_edge(clk) then
q <= a;
end if;
end process;
assert false report "Hello world" severity note;
end behav;% |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02224ent IS
END c07s02b06x00p01n01i02224ent;
ARCHITECTURE c07s02b06x00p01n01i02224arch OF c07s02b06x00p01n01i02224ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod TRUE;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02224 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02224arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02224ent IS
END c07s02b06x00p01n01i02224ent;
ARCHITECTURE c07s02b06x00p01n01i02224arch OF c07s02b06x00p01n01i02224ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod TRUE;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02224 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02224arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02224ent IS
END c07s02b06x00p01n01i02224ent;
ARCHITECTURE c07s02b06x00p01n01i02224arch OF c07s02b06x00p01n01i02224ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod TRUE;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02224 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02224arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/select1/select1_stub.vhdl
-- Design : select1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity select1 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end select1;
architecture stub of select1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/select1/select1_stub.vhdl
-- Design : select1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity select1 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end select1;
architecture stub of select1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[11:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_send is
port(
clk_in : in std_logic;
-- Serial I/O
serClkRE_in : in std_logic;
serData_out : out std_logic;
-- Parallel in
sendData_in : in std_logic_vector(7 downto 0);
sendValid_in : in std_logic;
sendReady_out : out std_logic
);
end entity;
architecture rtl of sync_send is
type StateType is (
S_IDLE,
S_WAIT,
S_SEND_BITS
);
signal state : StateType := S_IDLE;
signal state_next : StateType;
signal sendCount : unsigned(3 downto 0) := (others => '0');
signal sendCount_next : unsigned(3 downto 0);
signal sendData : std_logic_vector(8 downto 0) := (others => '0');
signal sendData_next : std_logic_vector(8 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
sendCount <= sendCount_next;
sendData <= sendData_next;
end if;
end process;
-- Next state logic
process(
state, serClkRE_in, sendData_in, sendValid_in, sendCount, sendData)
begin
state_next <= state;
sendCount_next <= sendCount;
sendData_next <= sendData;
sendReady_out <= '0';
serData_out <= '1';
case state is
-- Sending bits
when S_SEND_BITS =>
serData_out <= sendData(0);
if ( serClkRE_in = '1' ) then
sendData_next <= "1" & sendData(8 downto 1);
sendCount_next <= sendCount - 1;
if ( sendCount = 1 ) then
state_next <= S_IDLE;
end if;
end if;
-- Got a byte to send, waiting for rising_edge(serClk)
when S_WAIT =>
if ( serClkRE_in = '1' ) then
state_next <= S_SEND_BITS;
end if;
-- S_IDLE and others
when others =>
sendReady_out <= '1';
if ( sendValid_in = '1' ) then
-- There's a byte ready to be sent
sendCount_next <= x"9";
sendData_next <= sendData_in & "0";
if ( serClkRE_in = '1' ) then
state_next <= S_SEND_BITS;
else
state_next <= S_WAIT;
end if;
end if;
end case;
end process;
end architecture;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use IEEE.numeric_std.ALL;
use work.TG68K_Pack.ALL;
entity TG68K_ALU is
generic (
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port (
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic := '1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_width : in std_logic_vector(4 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
bf_offset : in std_logic_vector(31 downto 0);
set_V_Flag_out : out bit;
Flags_out : out std_logic_vector(7 downto 0);
c_out_out : out std_logic_vector(2 downto 0);
addsub_q_out : out std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU IS
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : BIT;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal pack_out : std_logic_vector(15 downto 0);
signal pack_a : std_logic_vector(15 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : BIT;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_loff_dir : std_logic_vector(4 downto 0);
signal bf_set2 : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_extu : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal index : std_logic_vector(4 downto 0);
signal bf_flag_z : std_logic;
signal bf_flag_n : std_logic;
signal set_V_Flag : BIT;
signal Flags : std_logic_vector(7 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
process (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
pack_out, bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_offset, bf_width,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
begin
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
if exec(opcBFwb) = '1' then
ALUout <= result(31 downto 0);
if bf_fffo = '1' then
ALUout <= bf_offset + bf_width + 1 - bf_firstbit;
end if;
end if;
OP1in <= addsub_q;
if exec(opcABCD) = '1' then
OP1in(7 downto 0) <= bcd_a(7 downto 0);
elsif exec(opcSBCD) = '1' then
OP1in(7 downto 0) <= bcd_s(7 downto 0);
elsif exec(opcMULU) = '1' and MUL_Mode /= 3 then
if exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then
OP1in <= result_mulu(31 downto 0);
else
OP1in <= result_mulu(63 downto 32);
end if;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
-- if exe_opcode(15)='1' then
OP1in <= result_div(47 downto 32) & result_div(15 downto 0);
else --64bit
if exec(write_reminder) = '1' then
OP1in <= result_div(63 downto 32);
else
OP1in <= result_div(31 downto 0);
end if;
end if;
elsif exec(opcOR) = '1' then
OP1in <= OP2out OR OP1out;
elsif exec(opcand) = '1' then
OP1in <= OP2out and OP1out;
elsif exec(opcScc) = '1' then
OP1in(7 downto 0) <= (others => exe_condition);
elsif exec(opcEOR) = '1' then
OP1in <= OP2out xor OP1out;
elsif exec(opcMOVE) = '1' OR exec(exg) = '1' then
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
elsif exec(opcROT) = '1' then
OP1in <= rot_out;
elsif exec(opcSWAP) = '1' then
OP1in <= OP1out(15 downto 0) & OP1out(31 downto 16);
elsif exec(opcBITS) = '1' then
OP1in <= bits_out;
elsif exec(opcBF) = '1' then
OP1in <= bf_datareg;
elsif exec(opcMOVECCR) = '1' then
OP1in(15 downto 8) <= "00000000";
OP1in( 7 downto 0) <= Flags;
elsif exec(opcMOVESR) = '1' then
OP1in(15 downto 8) <= FlagsSR;
OP1in( 7 downto 0) <= Flags;
elsif exec(opcPACK) = '1' then
OP1in(15 downto 0) <= pack_out;
end if;
end process;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
process (OP1out, OP2out, execOPC, datatype, Flags, long_start, non_aligned, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
begin
addsub_a <= OP1out;
if exec(get_bfoffset) = '1' then
if sndOPC(11) = '1' then
addsub_a <= OP1out(31) & OP1out(31) & OP1out(31) & OP1out(31 downto 3);
else
addsub_a <= "000000000000000000000000000000" & sndOPC(10 downto 9);
end if;
end if;
if exec(subidx) = '1' then
opaddsub <= '1';
else
opaddsub <= '0';
end if;
c_in(0) <= '0';
addsub_b <= OP2out;
if execOPC = '0' and exec(OP2out_one) = '0' and exec(get_bfoffset) = '0' then
if long_start = '0' and datatype = "00" and exec(use_SP) = '0' then
addsub_b <= "00000000000000000000000000000001";
elsif long_start = '0' and exe_datatype = "10" and (exec(presub) OR exec(postadd) OR movem_presub) = '1' then
if exec(movem_action) = '1' then -- used for initial offset / aligned case
addsub_b <= "00000000000000000000000000000110";
else
addsub_b <= "00000000000000000000000000000100";
end if;
else
addsub_b <= "00000000000000000000000000000010";
end if;
else
if (exec(use_XZFlag) = '1' and Flags(4) = '1') OR exec(opcCHK) = '1' then
c_in(0) <= '1';
end if;
opaddsub <= exec(addsub);
end if;
-- patch for un-aligned movem
if (exec(movem_action) = '1') then
if (movem_presub = '0') then -- up
if (non_aligned = '1') and (long_start = '0') then -- hold
addsub_b <= (others => '0');
end if;
else
if (non_aligned = '1') and (long_start = '0') then
if (exe_datatype = "10") then
addsub_b <= "00000000000000000000000000001000";
else
addsub_b <= "00000000000000000000000000000100";
end if;
end if;
end if;
end if;
if opaddsub = '0' OR long_start = '1' then --ADD
notaddsub_b <= '0' & addsub_b & c_in(0);
else --SUB
notaddsub_b <= not ('0' & addsub_b & c_in(0));
end if;
add_result <= (('0' & addsub_a & notaddsub_b(0)) + notaddsub_b);
c_in(1) <= add_result(9) xor addsub_a(8) xor addsub_b(8);
c_in(2) <= add_result(17) xor addsub_a(16) xor addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) xor add_result(8) xor addsub_a(7) xor addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) xor add_result(16) xor addsub_a(15) xor addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) xor add_result(32) xor addsub_a(31) xor addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
end process;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
process (OP1out, OP2out, pack_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
begin
if exe_opcode(7 downto 6) = "01" then
-- PACK
pack_a <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(OP2out(15 downto 0)));
pack_out <= "00000000" & pack_a(11 downto 8) & pack_a(3 downto 0);
else
-- UNPK
pack_a <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
pack_out <= std_logic_vector(unsigned(OP1out(15 downto 0)) + unsigned(pack_a));
end if;
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc & (niba_h(4 downto 1) + ('0', niba_hc, niba_hc, '0')) & (niba_l(4 downto 1) + ('0', niba_lc, niba_lc, '0'));
niba_l <= ('0' & OP1out(3 downto 0) & '1') + ('0' & OP2out(3 downto 0) & Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) and niba_l(3)) OR (niba_l(4) and niba_l(2));
niba_h <= ('0' & OP1out(7 downto 4) & '1') + ('0' & OP2out(7 downto 4) & niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) and niba_h(3)) OR (niba_h(4) and niba_h(2));
--SBC
bcd_s <= nibs_hc & (nibs_h(4 downto 1) - ('0', nibs_hc, nibs_hc, '0')) & (nibs_l(4 downto 1) - ('0', nibs_lc, nibs_lc, '0'));
nibs_l <= ('0' & OP1out(3 downto 0) & '0') - ('0' & OP2out(3 downto 0) & Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0' & OP1out(7 downto 4) & '0') - ('0' & OP2out(7 downto 4) & nibs_lc);
nibs_hc <= nibs_h(5);
end process;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
process (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC, reg_QB)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bchg <= '0';
bset <= '0';
case opcode(7 downto 6) IS
when "01" => --bchg
bchg <= '1';
when "11" => --bset
bset <= '1';
when others => NULL;
end case;
end if;
end if;
if exe_opcode(8) = '0' then
if exe_opcode(5 downto 4) = "00" then
bit_number <= sndOPC(4 downto 0);
else
bit_number <= "00" & sndOPC(2 downto 0);
end if;
else
if exe_opcode(5 downto 4) = "00" then
bit_number <= reg_QB(4 downto 0);
else
bit_number <= "00" & reg_QB(2 downto 0);
end if;
end if;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg and not one_bit_in) OR bset;
end process;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
-- Bitfields can have up to four (register) operands, e.g. bfins d0,d1{d2,d3}
-- the width an offset operands are evaluated while the second opcode word is
-- evaluated. These values are latched, so the two other registers can be read
-- in the next cycle while the ALU is working since the tg68k can only read
-- from two registers at once.
--
-- All bitfield operations can operate on registers or memory. There are
-- two fundamental differences which make the shifters quite complex:
-- 1. Memory content is delivered byte aligned to the ALU. Thus all shifting
-- is 7 bits far at most. Registers are 32 bit in size and may require
-- shifting of up to 31 bit positions
-- 2. Memory operations can affect 5 bytes. Thus all shifting is 40 bit in that
-- case. Registers are 32 bit in size and bitfield operations wrap. Shifts
-- are actually rotations for that reason
--
-- The destination operand is transfered via op1out and bf_ext into the ALU.
--
-- bftst, bfset, bfclr and bfchg
--------------------------------
-- bftst, bfset, bfclr and bfchg work very similar. A "sign" vector is generated
-- having "width" right aligned 0-bits and the rest ones.
-- A "copy" vector is generated from this by shifting through copymux so
-- this contains a 1 for all bits in bf_ext_in & op1out that will not be
-- affected by the operation.
-- The result vector is either all 1's (bfset), all 0's(bfclr) or the inverse
-- of bf_ext_in & op1out. Those bits in result that have a 1 in the copy
-- vector are overwritten with the original value from bf_ext_in & op1out
-- The result is returned through bf_ext_out and ALUout
--
-- These instructions only calculate the Z and N flags. Both are derived
-- directly from bf_ext_in & op1out with the help of the copy vector and
-- the offset/width fields. Thus Z and N are set from the previous contents
-- of the bitfield.
--
-- bfins
--------
-- bfins reuses most of the functionality of bfset, bfclr and bfchg. But it
-- has another 32 bit parameter that's being used for the source. This is passed
-- to the ALU via op2out. This is moved to the shift register and shifted
-- bf_shift bits to the right.
-- The input valus is also store in datareg and the lowest "width" bits
-- are masked. This is then forwarded to op1in which in turn uses the normal
-- mechanisms to generate the flags. A special bf_NFlag is also generated
-- from this. Z and N are set from these and not from the previous bitfield
-- contents as with bfset, bfclr or bfchg
--
-- bfextu/bfexts
----------------
-- bfexts and bfextu use the same shifter that is used by bfins to shift the
-- data to be inserted. It's using that same shifter to shift data in the
-- opposite direction. Flags are set from the extraced data
--
-- bfffo
--------
-- bfffo uses the same data path as bfext. But instead of directly returning
-- the extracted data it determines the highest bit setin the result
process (clk, bf_ins, bf_bchg, bf_bset, bf_exts, bf_extu, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
datareg, bf_NFlag, result, reg_QB, sign, bf_d32, copy, bf_loffset, bf_width)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_extu <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
case opcode(10 downto 8) IS
when "010" => bf_bchg <= '1'; --BFCHG
when "011" => bf_exts <= '1'; --BFEXTS
when "001" => bf_extu <= '1'; --BFEXTU
-- when "100" => insert <= (others =>'0'); --BFCLR
when "101" => bf_fffo <= '1'; --BFFFO
when "110" => bf_bset <= '1'; --BFSET
when "111" => bf_ins <= '1'; --BFinS
when others => NULL;
end case;
-- ea is a register
if opcode(4 downto 3) = "00" then
bf_d32 <= '1';
end if;
bf_ext_out <= result(39 downto 32);
end if;
end if;
------------- BF_SET2 --------------
if bf_ins = '1' then
bf_loff_dir <= 32 - bf_loffset;
else
bf_loff_dir <= bf_loffset;
end if;
if bf_d32 = '1' then
-- 32bit: rotate 0..31 bits left or right, don't care for upper 8 bits
bf_set2 <= "--------" & std_logic_vector(unsigned(OP2out) ror to_integer(unsigned(bf_loff_dir)));
else
if bf_ins = '1' then
-- 40 bit: shift 0..7 bits left
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) sll to_integer(unsigned(bf_loffset(2 downto 0))));
else
-- 40 bit: shift 0..7 bits right
bf_set2 <= std_logic_vector(unsigned(bf_ext_in & OP2out) srl to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
end if;
------------- COPY --------------
if bf_d32 = '1' then
-- 32bit: rotate 32 bits 0..31 bits left, don't care for upper 8 bits
copy <= "--------" & std_logic_vector(unsigned(sign) rol to_integer(unsigned(bf_loffset)));
else
-- 40 bit: shift 40 bits 0..7 bits left, fill with '1's (hence the two not's)
copy <= not std_logic_vector(unsigned(x"00" & (not sign)) sll to_integer(unsigned(bf_loffset(2 downto 0))));
end if;
if bf_ins = '1' then
datareg <= reg_QB;
else
datareg <= bf_set2(31 downto 0);
end if;
-- do the bitfield operation itself
if bf_ins = '1' then
result <= bf_set2;
elsif bf_bchg = '1' then
result <= not (bf_ext_in & OP1out);
elsif bf_bset = '1' then
result <= (others => '1');
else
result <= (others => '0');
end if;
sign <= (others => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
for i in 0 TO 31 loop
if i > bf_width then
datareg(i) <= '0';
sign(i) <= '1';
end if;
end loop;
-- Set bits 32..39 to 0 if operating on register to make sure
-- zero flag calculation over all 40 bits works correctly
result_tmp(31 downto 0) <= OP1out;
if bf_d32 = '1' then
result_tmp(39 downto 32) <= "00000000";
else
result_tmp(39 downto 32) <= bf_ext_in;
end if;
bf_flag_z <= '1';
if bf_d32 = '0' then
-- The test for this overflow shouldn't be needed. But GHDL complains
-- otherwise.
if(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)) > 39) then
bf_flag_n <= result_tmp(39);
else
bf_flag_n <= result_tmp(to_integer(unsigned('0' & bf_loffset)+unsigned(bf_width)));
end if;
else
--TH: TODO: check if this really does what it's supposed to
bf_flag_n <= result_tmp(to_integer(unsigned(bf_loffset)+unsigned(bf_width)));
end if;
for i in 0 TO 39 loop
if copy(i) = '1' then
result(i) <= result_tmp(i);
elsif result_tmp(i) = '1' then
bf_flag_z <= '0';
end if;
end loop;
if bf_exts = '1' and bf_NFlag = '1' then
bf_datareg <= datareg OR sign;
else
bf_datareg <= datareg;
end if;
--BFFFO
if datareg(31) = '1' then bf_firstbit <= "100000";
elsif datareg(30) = '1' then bf_firstbit <= "011111";
elsif datareg(29) = '1' then bf_firstbit <= "011110";
elsif datareg(28) = '1' then bf_firstbit <= "011101";
elsif datareg(27) = '1' then bf_firstbit <= "011100";
elsif datareg(26) = '1' then bf_firstbit <= "011011";
elsif datareg(25) = '1' then bf_firstbit <= "011010";
elsif datareg(24) = '1' then bf_firstbit <= "011001";
elsif datareg(23) = '1' then bf_firstbit <= "011000";
elsif datareg(22) = '1' then bf_firstbit <= "010111";
elsif datareg(21) = '1' then bf_firstbit <= "010110";
elsif datareg(20) = '1' then bf_firstbit <= "010101";
elsif datareg(19) = '1' then bf_firstbit <= "010100";
elsif datareg(18) = '1' then bf_firstbit <= "010011";
elsif datareg(17) = '1' then bf_firstbit <= "010010";
elsif datareg(16) = '1' then bf_firstbit <= "010001";
elsif datareg(15) = '1' then bf_firstbit <= "010000";
elsif datareg(14) = '1' then bf_firstbit <= "001111";
elsif datareg(13) = '1' then bf_firstbit <= "001110";
elsif datareg(12) = '1' then bf_firstbit <= "001101";
elsif datareg(11) = '1' then bf_firstbit <= "001100";
elsif datareg(10) = '1' then bf_firstbit <= "001011";
elsif datareg(9) = '1' then bf_firstbit <= "001010";
elsif datareg(8) = '1' then bf_firstbit <= "001001";
elsif datareg(7) = '1' then bf_firstbit <= "001000";
elsif datareg(6) = '1' then bf_firstbit <= "000111";
elsif datareg(5) = '1' then bf_firstbit <= "000110";
elsif datareg(4) = '1' then bf_firstbit <= "000101";
elsif datareg(3) = '1' then bf_firstbit <= "000100";
elsif datareg(2) = '1' then bf_firstbit <= "000011";
elsif datareg(1) = '1' then bf_firstbit <= "000010";
elsif datareg(0) = '1' then bf_firstbit <= "000001";
else bf_firstbit <= "000000";
end if;
end process;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
process (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
begin
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_rot <= OP1out(7);
when "01" | "11" => --Word
rot_rot <= OP1out(15);
when "10" => --Long
rot_rot <= OP1out(31);
when others => NULL;
end case;
case rot_bits IS
when "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
when "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
when "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
when "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
when others => NULL;
end case;
if exec(rot_nop) = '1' then
rot_out <= OP1out;
rot_X <= Flags(4);
if rot_bits = "10" then --ROXL, ROXR
rot_C <= Flags(4);
else
rot_C <= '0';
end if;
else
if exe_opcode(8) = '1' then --left
rot_out <= OP1out(30 downto 0) & rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
else --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb & OP1out(31 downto 1);
case exe_opcode(7 downto 6) IS
when "00" => --Byte
rot_out(7) <= rot_msb;
when "01" | "11" => --Word
rot_out(15) <= rot_msb;
when others => NULL;
end case;
end if;
end if;
end process;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
process (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1in, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
begin
if exec(andiSR) = '1' then
CCRin <= Flags and last_data_read(7 downto 0);
elsif exec(eoriSR) = '1' then
CCRin <= Flags xor last_data_read(7 downto 0);
elsif exec(oriSR) = '1' then
CCRin <= Flags OR last_data_read(7 downto 0);
else
CCRin <= OP2out(7 downto 0);
end if;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
if exec(use_XZFlag) = '1' and flags(2) = '0' then
flag_z <= "000";
elsif OP1in(7 downto 0) = "00000000" then
flag_z(0) <= '1';
if OP1in(15 downto 8) = "00000000" then
flag_z(1) <= '1';
if OP1in(31 downto 16) = "0000000000000000" then
flag_z(2) <= '1';
end if;
end if;
end if;
-- --Flags NZVC
if exe_datatype = "00" then --Byte
set_flags <= OP1in(7) & flag_z(0) & addsub_ofl(0) & c_out(0);
if exec(opcABCD) = '1' then
set_flags(0) <= bcd_a(8);
elsif exec(opcSBCD) = '1' then
set_flags(0) <= bcd_s(8);
end if;
elsif exe_datatype = "10" OR exec(opcCPMAW) = '1' then --Long
set_flags <= OP1in(31) & flag_z(2) & addsub_ofl(2) & c_out(2);
else --Word
set_flags <= OP1in(15) & flag_z(1) & addsub_ofl(1) & c_out(1);
end if;
if rising_edge(clk) then
if clkena_lw = '1' then
if exec(directSR) = '1' OR set_stop = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(directCCR) = '1' then
Flags(7 downto 0) <= data_read(7 downto 0);
end if;
if exec(opcROT) = '1' then
asl_VFlag <= ((set_flags(3) xor rot_rot) OR asl_VFlag);
else
asl_VFlag <= '0';
end if;
if exec(to_CCR) = '1' then
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
elsif Z_error = '1' then
if exe_opcode(8) = '0' then
Flags(3 downto 0) <= reg_QA(31) & "000";
else
Flags(3 downto 0) <= "0100";
end if;
elsif exec(no_Flags) = '0' then
if exec(opcADD) = '1' then
Flags(4) <= set_flags(0);
elsif exec(opcROT) = '1' and rot_bits /= "11" and exec(rot_nop) = '0' then
Flags(4) <= rot_X;
end if;
if (exec(opcADD) OR exec(opcCMP)) = '1' then
Flags(3 downto 0) <= set_flags;
elsif exec(opcDIVU) = '1' and DIV_Mode /= 3 then
if V_Flag = '1' then
Flags(3 downto 0) <= "1010";
else
Flags(3 downto 0) <= OP1in(15) & flag_z(1) & "00";
end if;
elsif exec(write_reminder) = '1' and MUL_Mode /= 3 then -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) and Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
elsif exec(write_lowlong) = '1' and (MUL_Mode = 1 OR MUL_Mode = 2) then -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
elsif exec(opcOR) = '1' OR exec(opcand) = '1' OR exec(opcEOR) = '1' OR exec(opcMOVE) = '1' OR exec(opcMOVEQ) = '1' OR exec(opcSWAP) = '1' OR exec(opcBF) = '1' OR (exec(opcMULU) = '1' and MUL_Mode /= 3) then
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
if exec(opcBF) = '1' then
-- flags(2) has correctly been set from set_flags
Flags(3) <= bf_NFlag;
--TH TODO: check flag handling of fffo
-- "normal" flags are taken from op2in
if bf_fffo = '0' and bf_extu='0' and bf_exts='0' and bf_ins='0' then
Flags(2) <= bf_flag_z;
Flags(3) <= bf_flag_n;
end if;
end if;
elsif exec(opcROT) = '1' then
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
if rot_bits = "00" and ((set_flags(3) xor rot_rot) OR asl_VFlag) = '1' then --ASL/ASR
Flags(1) <= '1';
else
Flags(1) <= '0';
end if;
elsif exec(opcBITS) = '1' then
Flags(2) <= not one_bit_in;
elsif exec(opcCHK) = '1' then
if exe_datatype = "01" then --Word
Flags(3) <= OP1out(15);
else
Flags(3) <= OP1out(31);
end if;
if OP1out(15 downto 0) = X"0000" and (exe_datatype = "01" OR OP1out(31 downto 16) = X"0000") then
Flags(2) <= '1';
else
Flags(2) <= '0';
end if;
Flags(1 downto 0) <= "00";
end if;
end if;
end if;
Flags(7 downto 5) <= "000";
end if;
end process;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
process (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
begin
if (signedOP = '1' and faktorB(31) = '1') OR FAsign = '1' then
muls_msb <= mulu_reg(63);
else
muls_msb <= '0';
end if;
if signedOP = '1' and faktorB(31) = '1' then
mulu_sign <= '1';
else
mulu_sign <= '0';
end if;
if MUL_Mode = 0 then -- 16 Bit
result_mulu(63 downto 32) <= muls_msb & mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X' & mulu_reg(15 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) - (mulu_sign & faktorB(31 downto 16)));
else
result_mulu(63 downto 47) <= (muls_msb & mulu_reg(63 downto 48) + (mulu_sign & faktorB(31 downto 16)));
end if;
end if;
else -- 32 Bit
result_mulu <= muls_msb & mulu_reg(63 downto 1);
if mulu_reg(0) = '1' then
if FAsign = '1' then
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) - (mulu_sign & faktorB));
else
result_mulu(63 downto 31) <= (muls_msb & mulu_reg(63 downto 32) + (mulu_sign & faktorB));
end if;
end if;
end if;
if exe_opcode(15) = '1' OR MUL_Mode = 0 then
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (others => '0');
else
faktorB <= OP2out;
end if;
if (result_mulu(63 downto 32) = X"00000000" and (signedOP = '0' OR result_mulu(31) = '0')) OR
(result_mulu(63 downto 32) = X"FFFFFFFF" and signedOP = '1' and result_mulu(31) = '1') then
set_mV_Flag <= '0';
else
set_mV_Flag <= '1';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
if micro_state = mul1 then
mulu_reg(63 downto 32) <= (others => '0');
if divs = '1' and ((exe_opcode(15) = '1' and reg_QA(15) = '1') OR (exe_opcode(15) = '0' and reg_QA(31) = '1')) then --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0 - reg_QA;
else
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
end if;
elsif exec(opcMULU) = '0' then
mulu_reg <= result_mulu;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
process (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
begin
divs <= (opcode(15) and opcode(8)) OR (not opcode(15) and sndOPC(11));
divisor(15 downto 0) <= (others => '0');
divisor(63 downto 32) <= (others => divs and reg_QA(31));
if exe_opcode(15) = '1' OR DIV_Mode = 0 then
divisor(47 downto 16) <= reg_QA;
else
divisor(31 downto 0) <= reg_QA;
if exe_opcode(14) = '1' and sndOPC(10) = '1' then
divisor(63 downto 32) <= reg_QB;
end if;
end if;
if signedOP = '1' OR opcode(15) = '0' then
OP2outext <= OP2out(31 downto 16);
else
OP2outext <= (others => '0');
end if;
if signedOP = '1' and OP2out(31) = '1' then
div_sub <= (div_reg(63 downto 31)) + ('1' & OP2out(31 downto 0));
else
div_sub <= (div_reg(63 downto 31)) - ('0' & OP2outext(15 downto 0) & OP2out(15 downto 0));
end if;
if DIV_Mode = 0 then
div_bit <= div_sub(16);
else
div_bit <= div_sub(32);
end if;
if div_bit = '1' then
div_quot(63 downto 32) <= div_reg(62 downto 31);
else
div_quot(63 downto 32) <= div_sub(31 downto 0);
end if;
div_quot(31 downto 0) <= div_reg(30 downto 0) & not div_bit;
if ((nozero = '1' and signedOP = '1' and (OP2out(31) xor OP1_sign xor div_neg xor div_qsign) = '1' ) --Overflow DIVS
OR (signedOP = '0' and div_over(32) = '0')) and DIV_Mode /= 3 then --Overflow DIVU
set_V_Flag <= '1';
else
set_V_Flag <= '0';
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
V_Flag <= set_V_Flag;
signedOP <= divs;
if micro_state = div1 then
nozero <= '0';
if divs = '1' and divisor(63) = '1' then -- Neg divisor
OP1_sign <= '1';
div_reg <= 0 - divisor;
else
OP1_sign <= '0';
div_reg <= divisor;
end if;
else
div_reg <= div_quot;
nozero <= not div_bit OR nozero;
end if;
if micro_state = div2 then
div_qsign <= not div_bit;
div_neg <= signedOP and (OP2out(31) xor OP1_sign);
if DIV_Mode = 0 then
div_over(32 downto 16) <= ('0' & div_reg(47 downto 32)) - ('0' & OP2out(15 downto 0));
else
div_over <= ('0' & div_reg(63 downto 32)) - ('0' & OP2out);
end if;
end if;
if exec(write_reminder) = '0' then
-- if exec_DIVU='0' then
if div_neg = '1' then
result_div(31 downto 0) <= 0 - div_quot(31 downto 0);
else
result_div(31 downto 0) <= div_quot(31 downto 0);
end if;
if OP1_sign = '1' then
result_div(63 downto 32) <= 0 - div_quot(63 downto 32);
else
result_div(63 downto 32) <= div_quot(63 downto 32);
end if;
end if;
end if;
end if;
end process;
set_V_Flag_out <= set_V_Flag;
Flags_out <= Flags;
c_out_out <= c_out;
addsub_q_out <= addsub_q;
end;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 11:50:14 11/30/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Top of ultrasonic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity Ultrasonic is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Rx : in STD_LOGIC;
Tx : out STD_LOGIC;
out_ultrasonic : out STD_LOGIC);
end Ultrasonic;
architecture Behavioral of Ultrasonic is
-- State definition
type state_values is (StartPulse,WaitForResponse,UltrasonicResponse,WaitForNewStart);
signal pres_state, next_state : state_values;
-- Define the State duration times for the variable time duration FSM
-- All times are expressed in micro-seconds
constant tStartPulse : integer := 5;
constant tWaitForNewStart : integer := 1_000_000;
-- Define signals used by frequency divider
constant Fosc : integer := 100_000_000; --Frecuencia del oscilador de Nexys3
constant Fdiv : integer := 1_000_000; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
signal Cont : integer range 0 to CtaMax;
signal TimeBase : STD_LOGIC;
-- Define a second counter, used to determine how much
-- time has been spent in a State
signal SecondCount : integer range 0 to tWaitForNewStart;
-- Define a signal that gives the amount of time
-- to be spent in a State
signal StateDuration : integer range 0 to tWaitForNewStart;
-- signals to obtain distance, duration response of the ultrasonic sensor and then convert into distance
signal tIN : integer range 0 to 20_000; -- should be 18500 but we are givin some room
signal Measurement: integer range 0 to 300; -- centimeters
begin
--Regla calcular distancia
-- x = tin * 300 / 18500
-- Generate a TimeBase of one second
freqdiv: process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
TimeBase <= '1';
else
Cont <= Cont + 1;
TimeBase <= '0';
end if;
end if;
end process freqdiv;
-- measurement equations
Measurement <= (tIN * 300) / 18500;
--process that count to obtain T_in
tIn_Counter: process(Clk, TimeBase, tIN, Rst)
begin
if(rising_edge(Clk) and TimeBase = '1') then
if(pres_state = WaitForResponse) then
tIN <= 0;
elsif (pres_state = UltrasonicResponse) then
tIN <= tIN + 1;
elsif (pres_state = WaitForNewStart) then
end if;
end if;
end process tIn_Counter;
statereg : process(Clk,TimeBase,Rst)
begin
if Rst = '1' then
pres_state <= StartPulse;
SecondCount <= 0;
elsif (rising_edge(Clk) and TimeBase = '1') then
if SecondCount = StateDuration-1 then
pres_state <= next_state;
SecondCount <= 0;
else
SecondCount <= SecondCount + 1;
end if;
end if;
end process statereg;
fsm : process (pres_state, Rx)
begin
case (pres_state) is
-- ST0
when StartPulse =>
next_state <= WaitForResponse;
StateDuration <= tStartPulse;
-- ST1
when WaitForResponse =>
if Rx = '1' then
next_state <= UltraSonicResponse;
else
next_state <= WaitForResponse;
end if;
StateDuration <= 1;
-- ST2
when UltraSonicResponse =>
if Rx = '0' then
next_state <= WaitForNewStart;
else
next_state <= UltraSonicResponse;
end if;
StateDuration <= 1;
-- ST3
when WaitForNewStart =>
next_state <= StartPulse;
StateDuration <= tWaitForNewStart;
when others =>
next_state <= WaitForResponse;
StateDuration <= tStartPulse;
end case;
end process fsm;
output : process (pres_state,Measurement)
begin
case (pres_state) is
when StartPulse => Tx <= '1';
when WaitForResponse => Tx <= '0';
when UltraSonicResponse => Tx <= '0';
when WaitForNewStart => Tx <= '0';
when others => Tx <= '1';
end case;
if(Measurement < 30) then
out_ultrasonic <= '1'; -- enemy
else
out_ultrasonic <= '0'; -- no detect
end if;
end process output;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum_medio is
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component eXor
port(
entrada1_xor: in std_logic;
entrada2_xor: in std_logic;
salida_xor: out std_logic);
end component;
end pack_sum_medio;
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum_medio is
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component eXor
port(
entrada1_xor: in std_logic;
entrada2_xor: in std_logic;
salida_xor: out std_logic);
end component;
end pack_sum_medio;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MISC_RDET12;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MISC_RDET12;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_RDET12 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic_vector(11 downto 0);
RISE : out vl_logic_vector(11 downto 0)
);
end F2DSS_ACE_MISC_RDET12;
|
package pkg is
procedure say_hello;
end pkg;
package body pkg is
procedure say_hello is
begin
report "Hello";
end say_hello;
end pkg;
|
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_recv is
port(
clk_in : in std_logic;
-- Serial in
serClkFE_in : in std_logic; -- serClk falling edge
serData_in : in std_logic;
-- Parallel out
recvData_out : out std_logic_vector(7 downto 0);
recvValid_out : out std_logic
);
end entity;
architecture rtl of sync_recv is
type StateType is (
S_IDLE,
S_RECV_BITS
);
signal state : StateType := S_IDLE;
signal state_next : StateType;
signal recvCount : unsigned(2 downto 0) := (others => '0');
signal recvCount_next : unsigned(2 downto 0);
signal recvData : std_logic_vector(6 downto 0) := (others => '0');
signal recvData_next : std_logic_vector(6 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
recvCount <= recvCount_next;
recvData <= recvData_next;
end if;
end process;
-- Next state logic
process(
state, serClkFE_in, serData_in, recvCount, recvData)
begin
state_next <= state;
recvCount_next <= recvCount;
recvData_next <= recvData;
recvData_out <= (others => 'X');
recvValid_out <= '0';
case state is
-- Receiving bits
when S_RECV_BITS =>
if ( serClkFE_in = '1' ) then
recvData_next <= serData_in & recvData(6 downto 1);
recvCount_next <= recvCount - 1;
if ( recvCount = 0 ) then
recvData_out <= serData_in & recvData;
recvValid_out <= '1';
state_next <= S_IDLE;
end if;
end if;
-- S_IDLE and others
when others =>
if ( serClkFE_in = '1' ) then
if ( serData_in = '0' ) then
-- This is a start bit; next bit will be data bit zero
recvCount_next <= "111";
state_next <= S_RECV_BITS;
end if;
end if;
end case;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Jiri Gaisler, Aeroflex Gaisler
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
-- Aeroflex Gaisler device id's
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_SERIES7 : amba_device_type := 16#090#;
constant GAISLER_SPWBIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- European Space Agency device id's
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip ID's
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device id's
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- Orbita device id's
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library ID's
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device id's
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_NEXTREME1 : system_device_type := 16#0101#;
constant LEON4_NEXTREME1 : system_device_type := 16#0102#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID6RSNETH: system_device_type := 16#0196#;
constant LEON3_RTAX_KARI : system_device_type := 16#0197#;
constant LEON3_RTAX_IAA : system_device_type := 16#0198#;
constant LEON3_RTAX_TECNOBIT : system_device_type := 16#0199#;
constant LEON3_RTAX_TDP8 : system_device_type := 16#0200#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_IHP25RH1 : system_device_type := 16#0251#;
constant NGMP_PROTOTYPE : system_device_type := 16#0281#;
constant NGMP_PROTOTYPE2 : system_device_type := 16#0282#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
constant ORBITA_1 : system_device_type := 16#0631#;
constant ORBITA_OBTMP : system_device_type := 16#0632#;
constant AEROFLEX_UT699 : system_device_type := 16#0699#;
constant AEROFLEX_UT700 : system_device_type := 16#0700#;
constant GAISLER_GR701 : system_device_type := 16#0701#;
constant GAISLER_GR702 : system_device_type := 16#0702#;
constant GAISLER_GR703 : system_device_type := 16#0703#;
constant GAISLER_DARE1 : system_device_type := 16#0704#;
constant GAISLER_GR712RC : system_device_type := 16#0712#;
constant GAISLER_SPWRTRASIC : system_device_type := 16#0718#;
constant AEROFLEX_UT840 : system_device_type := 16#0840#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Aeroflex Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_SERIES7 => "Xilinx MIG DDR3 Controller ",
GAISLER_SPWBIST => "GRSPW Router BIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "DMA Controller with APB bridge ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_NEXTREME1 => "LEON3 eASIC Nextreme controller",
LEON4_NEXTREME1 => "LEON4 eASIC Nextreme SoC ",
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
ALTERA_DE2 => "Altera DE2 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
AEROFLEX_UT699 => "Aeroflex UT699 Rad-Hard CPU ",
AEROFLEX_UT700 => "Aeroflex UT700 Rad-Hard CPU ",
GAISLER_DARE1 => "Gaisler DARE1 Rad-Hard CPU ",
GAISLER_GR712RC => "Gaisler GR712RC Rad-Hard CPU ",
NGMP_PROTOTYPE => "NGMP Prototype System-on-Chip ",
NGMP_PROTOTYPE2 => "NGMP Prototype System-on-Chip ",
ORBITA_OBTMP => "Orbita LEON4 prototype system ",
GAISLER_SPWRTRASIC => "Gaisler SpaceWire Router ASIC ",
others => "Unknown system ");
-- pragma translate_on
end;
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