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entity repro4 is
end entity;
architecture tb of repro4 is
type channel is record
data : bit_vector;
ack : bit;
end record;
type my_bus is record
rd : channel;
wr : channel;
end record;
function init_channel (width : natural) return channel is
begin
return (data => (width - 1 downto 0 => '0'),
ack => '0');
end init_channel;
function init_bus (width : natural) return my_bus is
begin
return (rd => init_channel (width),
wr => init_channel (width));
end init_bus;
constant b : my_bus := init_bus (12);
begin
assert b.rd.data(2) = '0';
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_169;
architecture augh of add_169 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_169 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_169;
architecture augh of add_169 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
-------------------------------------------------------------------------------
-- leds_4bit_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_gpio_v2_00_a;
use xps_gpio_v2_00_a.all;
entity leds_4bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 3);
GPIO_IO_O : out std_logic_vector(0 to 3);
GPIO_IO_T : out std_logic_vector(0 to 3);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute x_core_info of leds_4bit_wrapper : entity is "xps_gpio_v2_00_a";
end leds_4bit_wrapper;
architecture STRUCTURE of leds_4bit_wrapper is
component xps_gpio is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_FAMILY : STRING;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector;
C_TRI_DEFAULT : std_logic_vector;
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector;
C_TRI_DEFAULT_2 : std_logic_vector
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1))
);
end component;
begin
LEDS_4BIT : xps_gpio
generic map (
C_BASEADDR => X"81400000",
C_HIGHADDR => X"8140ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_FAMILY => "spartan3a",
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (8 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (8 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (8 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (8 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1: INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_diff_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential output transmitter for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_diff_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout_p, dataout_n : out std_logic_vector(7 downto 0) ; -- differential data outputs
clkout_p, clkout_n : out std_logic ) ; -- differential clock output
end top_nto1_ddr_diff_tx ;
architecture arch_top_nto1_ddr_diff_tx of top_nto1_ddr_diff_tx is
component clock_generator_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclkap : out std_logic ; -- A P ioclock from BUFIO2
ioclkan : out std_logic ; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end component ;
component serdes_n_to_1_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal txd : std_logic_vector(DS downto 0) ; -- Registered Data to serdeses
signal txioclkp : std_logic ;
signal txioclkn : std_logic ;
signal tx_serdesstrobe : std_logic ;
signal tx_bufg_x1 : std_logic ;
signal clkoutp : std_logic_vector(0 downto 0) ;
signal clkoutn : std_logic_vector(0 downto 0) ;
-- Parameters for clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := X"AA" ; -- Transmit a constant to make a clock
begin
rst <= reset ;
-- Reference Clock Input genertaes IO clocks via 2 x BUFIO2
inst_clkgen : clock_generator_ddr_s8_diff generic map(
S => S)
port map(
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclkap => txioclkp,
ioclkan => txioclkn,
serdesstrobea => tx_serdesstrobe,
ioclkbp => open,
ioclkbn => open,
serdesstrobeb => open,
gclk => tx_bufg_x1) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= X"3000000000000001" ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(63 downto 60) & txd(58 downto 0) & txd(59) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
inst_clkout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => 1)
port map (
dataout_p => clkoutp,
dataout_n => clkoutn,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= clkoutp(0) ;
clkout_n <= clkoutn(0) ;
-- Instantiate Outputs and output serialisers for output data lines
inst_dataout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_ddr_diff_tx ;
|
-- This module is intended for power-on resetting, while accepting force reset
-- (i.e. from a button push) to reset both clock generator (DCM) and other
-- components in the design. It sets CLK_RST high for (CNT_RANGE_HIGH -
-- CLK_RESET_DELAY_CNT) cycles, Then wait for the DCM_LOCKED signal. It waits
-- for another (CNT_RANGE_HIGH - GBL_RESET_DELAY_CNT) cycles before setting
-- GLOBAL_RST low. This module will monitor both FORCE_RST and DCM_LOCKED,
-- and go through proper resetting sequence if either condition is triggered.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
-- Entity Declaration
ENTITY GlobalResetter IS
GENERIC (
CLK_RESET_DELAY_CNT : integer := 10000;
GBL_RESET_DELAY_CNT : integer := 100;
CNT_RANGE_HIGH : integer := 16383
);
PORT (
FORCE_RST : IN std_logic;
CLK : IN std_logic; -- system clock
DCM_LOCKED : IN std_logic;
CLK_RST : OUT std_logic;
GLOBAL_RST : OUT std_logic
);
END GlobalResetter;
-- Architecture body
ARCHITECTURE Behavioral OF GlobalResetter IS
TYPE rstState_type IS (R0, R1, R2, R3, R4);
SIGNAL rstState : rstState_type;
BEGIN
rst_sm: PROCESS (CLK, FORCE_RST) IS
VARIABLE rstCtr : integer RANGE 0 TO CNT_RANGE_HIGH := 0;
BEGIN -- PROCESS rst_sm
IF FORCE_RST = '1' THEN -- asynchronous reset (active high)
rstState <= R0;
rstCtr := 0;
ELSIF rising_edge(CLK) THEN -- rising clock edge
CLK_RST <= '0';
GLOBAL_RST <= '1';
CASE rstState IS
WHEN R0 =>
CLK_RST <= '1';
rstCtr := CLK_RESET_DELAY_CNT;
rstState <= R1;
WHEN R1 =>
CLK_RST <= '1';
IF rstCtr = 0 THEN
rstState <= R2;
ELSE
rstCtr := rstCtr + 1;
END IF;
WHEN R2 =>
rstCtr := GBL_RESET_DELAY_CNT;
IF DCM_LOCKED = '1' THEN
rstState <= R3;
END IF;
WHEN R3 =>
IF rstCtr = 0 THEN
rstState <= R4;
ELSE
rstCtr := rstCtr + 1;
END IF;
WHEN R4 =>
GLOBAL_RST <= '0';
IF DCM_LOCKED = '0' THEN
rstState <= R0;
END IF;
WHEN OTHERS =>
rstState <= R0;
END CASE;
END IF;
END PROCESS rst_sm;
END Behavioral;
|
-- This module is intended for power-on resetting, while accepting force reset
-- (i.e. from a button push) to reset both clock generator (DCM) and other
-- components in the design. It sets CLK_RST high for (CNT_RANGE_HIGH -
-- CLK_RESET_DELAY_CNT) cycles, Then wait for the DCM_LOCKED signal. It waits
-- for another (CNT_RANGE_HIGH - GBL_RESET_DELAY_CNT) cycles before setting
-- GLOBAL_RST low. This module will monitor both FORCE_RST and DCM_LOCKED,
-- and go through proper resetting sequence if either condition is triggered.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
-- Entity Declaration
ENTITY GlobalResetter IS
GENERIC (
CLK_RESET_DELAY_CNT : integer := 10000;
GBL_RESET_DELAY_CNT : integer := 100;
CNT_RANGE_HIGH : integer := 16383
);
PORT (
FORCE_RST : IN std_logic;
CLK : IN std_logic; -- system clock
DCM_LOCKED : IN std_logic;
CLK_RST : OUT std_logic;
GLOBAL_RST : OUT std_logic
);
END GlobalResetter;
-- Architecture body
ARCHITECTURE Behavioral OF GlobalResetter IS
TYPE rstState_type IS (R0, R1, R2, R3, R4);
SIGNAL rstState : rstState_type;
BEGIN
rst_sm: PROCESS (CLK, FORCE_RST) IS
VARIABLE rstCtr : integer RANGE 0 TO CNT_RANGE_HIGH := 0;
BEGIN -- PROCESS rst_sm
IF FORCE_RST = '1' THEN -- asynchronous reset (active high)
rstState <= R0;
rstCtr := 0;
ELSIF rising_edge(CLK) THEN -- rising clock edge
CLK_RST <= '0';
GLOBAL_RST <= '1';
CASE rstState IS
WHEN R0 =>
CLK_RST <= '1';
rstCtr := CLK_RESET_DELAY_CNT;
rstState <= R1;
WHEN R1 =>
CLK_RST <= '1';
IF rstCtr = 0 THEN
rstState <= R2;
ELSE
rstCtr := rstCtr + 1;
END IF;
WHEN R2 =>
rstCtr := GBL_RESET_DELAY_CNT;
IF DCM_LOCKED = '1' THEN
rstState <= R3;
END IF;
WHEN R3 =>
IF rstCtr = 0 THEN
rstState <= R4;
ELSE
rstCtr := rstCtr + 1;
END IF;
WHEN R4 =>
GLOBAL_RST <= '0';
IF DCM_LOCKED = '0' THEN
rstState <= R0;
END IF;
WHEN OTHERS =>
rstState <= R0;
END CASE;
END IF;
END PROCESS rst_sm;
END Behavioral;
|
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- prescaler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Shared prescaler for transmitter and receiver timings.
-- Used to control the transfer speed.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prescaler is
generic (
SCALE : integer
);
Port ( clock : in STD_LOGIC;
reset : in std_logic;
div : in std_logic_vector(1 downto 0);
scaled : out std_logic
);
end prescaler;
architecture Behavioral of prescaler is
signal counter : integer range 0 to (6 * SCALE) - 1;
begin
process(clock, reset)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clock) then
if
(counter = SCALE - 1 and div = "00") -- 115200
or (counter = 2 * SCALE - 1 and div = "01") -- 57600
or (counter = 3 * SCALE - 1 and div = "10") -- 38400
or (counter = 6 * SCALE - 1 and div = "11") -- 19200
then
counter <= 0;
scaled <= '1';
else
counter <= counter + 1;
scaled <= '0';
end if;
end if;
end process;
end Behavioral;
|
-- ring_counter - ring counter logic written in vhdl
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity ring_counter is
generic (
SIZE : positive := 5;
START : natural := 2
);
port (
reset : in std_logic := '0';
direction : in std_logic;
clock : in std_logic;
output : out std_logic_vector (SIZE-1 downto 0) := (START => '1', others => '0')
);
end ring_counter;
architecture rtl of ring_counter is
signal cnt : std_logic_vector (SIZE-1 downto 0) := (START => '1', others => '0');
begin
output <= cnt;
process (reset, clock)
begin
if reset = '1' then
cnt <= (START => '1', others => '0');
elsif rising_edge(clock) then
if direction = '0' then
cnt <= cnt(0) & cnt(SIZE-1 downto 1);
else
cnt <= cnt(SIZE-2 downto 0) & cnt(SIZE-1);
end if;
end if;
end process;
end rtl;
|
entity tb_iassoc03 is
end tb_iassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc03 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc03
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
assert res = 6 severity failure;
a <= 197;
b <= 203;
wait for 1 ns;
assert res = 400 severity failure;
wait;
end process;
end behav;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top is
end entity;
architecture test of elab2_top is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top is
end entity;
architecture test of elab2_top is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top is
end entity;
architecture test of elab2_top is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top is
end entity;
architecture test of elab2_top is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
end architecture;
|
entity elab2_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab2_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab2_top is
end entity;
architecture test of elab2_top is
signal a, b, c : integer;
begin
bot1: entity work.elab2_bot
port map ( a, b );
bot2: entity work.elab2_bot
port map ( b, c );
end architecture;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: standard_cc_module_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- STANDARD_CC_MODULE
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engeneering Group
--
-- Description: This module drives the Aurora module's Clock Compensation
-- interface. Clock Compensation sequences are generated according
-- to the requirements in the Aurora Protocol specification.
--
-- This module supports Aurora Modules with any number of
-- 2-byte lanes and no User Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity STANDARD_CC_MODULE is
port
(
-- Clock Compensation Control Interface
WARN_CC : out std_logic;
DO_CC : out std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
CHANNEL_UP : in std_logic
);
end STANDARD_CC_MODULE;
architecture RTL of STANDARD_CC_MODULE is
--******************************Parameter Declarations*******************************
constant DLY : time := 1 ns;
--************************** Internal Register Declarations **************************
signal prepare_count_r : std_logic_vector(0 to 9) := "0000000000";
signal cc_count_r : std_logic_vector(0 to 5) := "000000";
signal reset_r : std_logic;
signal count_13d_srl_r : std_logic_vector(0 to 11);
signal count_13d_flop_r : std_logic;
signal count_16d_srl_r : std_logic_vector(0 to 14);
signal count_16d_flop_r : std_logic;
signal count_24d_srl_r : std_logic_vector(0 to 22);
signal count_24d_flop_r : std_logic;
--*********************************Wire Declarations**********************************
signal start_cc_c : std_logic;
signal inner_count_done_r : std_logic;
signal middle_count_done_c : std_logic;
signal cc_idle_count_done_c : std_logic;
--*********************************Main Body of Code**********************************
begin
--________________________Clock Correction State Machine__________________________
-- The clock correction state machine is a counter with three sections. The first
-- section counts out the idle period before a clock correction occurs. The second
-- section counts out a period when NFC and UFC operations should not be attempted
-- because they will not be completed. The last section counts out the cycles of
-- the clock correction sequence.
-- The inner count for the CC counter counts to 13. It is implemented using
-- an SRL16 and a flop
-- The SRL counts 12 bits of the count
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
count_13d_srl_r <= (count_13d_flop_r & count_13d_srl_r(0 to 10)) after DLY;
end if;
end process;
-- The inner count is done when a 1 reaches the end of the SRL
inner_count_done_r <= count_13d_srl_r(11);
-- The flop extends the shift register to 13 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_13d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r)= '1') then
count_13d_flop_r <= '1' after DLY;
else
count_13d_flop_r <= inner_count_done_r after DLY;
end if;
end if;
end process;
-- The middle count for the CC counter counts to 16. Its count increments only
-- when the inner count is done. It is implemented using an SRL16 and a flop
-- The SRL counts 15 bits of the count. It is enabled only when the inner count
-- is done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((inner_count_done_r or not CHANNEL_UP) = '1') then
count_16d_srl_r <= ( count_16d_flop_r & count_16d_srl_r(0 to 13) ) after DLY;
end if;
end if;
end process;
-- The middle count is done when a 1 reaches the end of the SRL and the inner
-- count finishes
middle_count_done_c <= inner_count_done_r and count_16d_srl_r(14);
-- The flop extends the shift register to 16 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_16d_flop_r <= '0' after DLY;
elsif((CHANNEL_UP and reset_r)='1') then
count_16d_flop_r <= '1' after DLY;
elsif(inner_count_done_r = '1') then
count_16d_flop_r <= middle_count_done_c after DLY;
end if;
end if;
end process;
-- The outer count (aka the cc idle count) is done when it reaches 24. Its count
-- increments only when the middle count is done. It is implemented with 2
-- SRL16Es.
-- The SRL counts 23 bits of the count. It is enabled only when the middle count is
-- done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((middle_count_done_c or not CHANNEL_UP) = '1') then
count_24d_srl_r <= (count_24d_flop_r & count_24d_srl_r(0 to 21)) after DLY;
end if;
end if;
end process;
-- The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
cc_idle_count_done_c <= middle_count_done_c and count_24d_srl_r(22);
-- The flop extends the shift register to 24 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a single
-- 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_24d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r) = '1') then
count_24d_flop_r <= '1' after DLY;
elsif( middle_count_done_c = '1') then
count_24d_flop_r <= cc_idle_count_done_c after DLY;
end if;
end if;
end process;
-- Because UFC and CC sequences are not allowed to preempt one another, there
-- there is a warning signal to indicate an impending CC sequence. This signal
-- is used to prevent UFC messages from starting.
-- For 1 lane, we need an 10-cycle count.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
prepare_count_r <= (cc_idle_count_done_c & prepare_count_r(0 to 8)) after DLY;
end if;
end process;
-- The state machine stays in the prepare_cc state from when the cc idle
-- count finishes, to when the prepare count has finished. While in this
-- state, UFC operations cannot start, which prevents them from having to
-- be pre-empted by CC sequences.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
WARN_CC <= '0' after DLY;
elsif(cc_idle_count_done_c = '1') then
WARN_CC <= '1' after DLY;
elsif(prepare_count_r(9) = '1') then
WARN_CC <= '0' after DLY;
end if;
end if;
end process;
-- Track the state of channel up on the previous cycle. We use this signal to determine
-- when to seed the shift register counters with ones
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
reset_r <= not CHANNEL_UP after DLY;
end if;
end process;
--Do a CC after CHANNEL_UP is asserted or CC_warning is complete.
start_cc_c <= prepare_count_r(9) or (CHANNEL_UP and reset_r);
-- This SRL counter keeps track of the number of cycles spent in the CC
-- sequence. It starts counting when the prepare_cc state ends, and
-- finishes counting after 6 cycles have passed.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
cc_count_r <= ( (not CHANNEL_UP or prepare_count_r(9)) & cc_count_r(0 to 4) ) after DLY;
end if;
end process;
-- The TX_LL module stays in the do_cc state for 6 cycles. It starts
-- when the prepare_cc state ends.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
DO_CC <= '0' after DLY;
elsif(start_cc_c = '1') then
DO_CC <= '1' after DLY;
elsif(cc_count_r(5) = '1') then
DO_CC <= '0' after DLY;
end if;
end if;
end process;
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:55 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: standard_cc_module_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- STANDARD_CC_MODULE
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engeneering Group
--
-- Description: This module drives the Aurora module's Clock Compensation
-- interface. Clock Compensation sequences are generated according
-- to the requirements in the Aurora Protocol specification.
--
-- This module supports Aurora Modules with any number of
-- 2-byte lanes and no User Flow Control.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.all;
-- synthesis translate_on
entity STANDARD_CC_MODULE is
port
(
-- Clock Compensation Control Interface
WARN_CC : out std_logic;
DO_CC : out std_logic;
-- System Interface
DCM_NOT_LOCKED : in std_logic;
USER_CLK : in std_logic;
CHANNEL_UP : in std_logic
);
end STANDARD_CC_MODULE;
architecture RTL of STANDARD_CC_MODULE is
--******************************Parameter Declarations*******************************
constant DLY : time := 1 ns;
--************************** Internal Register Declarations **************************
signal prepare_count_r : std_logic_vector(0 to 9) := "0000000000";
signal cc_count_r : std_logic_vector(0 to 5) := "000000";
signal reset_r : std_logic;
signal count_13d_srl_r : std_logic_vector(0 to 11);
signal count_13d_flop_r : std_logic;
signal count_16d_srl_r : std_logic_vector(0 to 14);
signal count_16d_flop_r : std_logic;
signal count_24d_srl_r : std_logic_vector(0 to 22);
signal count_24d_flop_r : std_logic;
--*********************************Wire Declarations**********************************
signal start_cc_c : std_logic;
signal inner_count_done_r : std_logic;
signal middle_count_done_c : std_logic;
signal cc_idle_count_done_c : std_logic;
--*********************************Main Body of Code**********************************
begin
--________________________Clock Correction State Machine__________________________
-- The clock correction state machine is a counter with three sections. The first
-- section counts out the idle period before a clock correction occurs. The second
-- section counts out a period when NFC and UFC operations should not be attempted
-- because they will not be completed. The last section counts out the cycles of
-- the clock correction sequence.
-- The inner count for the CC counter counts to 13. It is implemented using
-- an SRL16 and a flop
-- The SRL counts 12 bits of the count
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
count_13d_srl_r <= (count_13d_flop_r & count_13d_srl_r(0 to 10)) after DLY;
end if;
end process;
-- The inner count is done when a 1 reaches the end of the SRL
inner_count_done_r <= count_13d_srl_r(11);
-- The flop extends the shift register to 13 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_13d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r)= '1') then
count_13d_flop_r <= '1' after DLY;
else
count_13d_flop_r <= inner_count_done_r after DLY;
end if;
end if;
end process;
-- The middle count for the CC counter counts to 16. Its count increments only
-- when the inner count is done. It is implemented using an SRL16 and a flop
-- The SRL counts 15 bits of the count. It is enabled only when the inner count
-- is done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((inner_count_done_r or not CHANNEL_UP) = '1') then
count_16d_srl_r <= ( count_16d_flop_r & count_16d_srl_r(0 to 13) ) after DLY;
end if;
end if;
end process;
-- The middle count is done when a 1 reaches the end of the SRL and the inner
-- count finishes
middle_count_done_c <= inner_count_done_r and count_16d_srl_r(14);
-- The flop extends the shift register to 16 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a
-- single 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_16d_flop_r <= '0' after DLY;
elsif((CHANNEL_UP and reset_r)='1') then
count_16d_flop_r <= '1' after DLY;
elsif(inner_count_done_r = '1') then
count_16d_flop_r <= middle_count_done_c after DLY;
end if;
end if;
end process;
-- The outer count (aka the cc idle count) is done when it reaches 24. Its count
-- increments only when the middle count is done. It is implemented with 2
-- SRL16Es.
-- The SRL counts 23 bits of the count. It is enabled only when the middle count is
-- done
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if((middle_count_done_c or not CHANNEL_UP) = '1') then
count_24d_srl_r <= (count_24d_flop_r & count_24d_srl_r(0 to 21)) after DLY;
end if;
end if;
end process;
-- The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
cc_idle_count_done_c <= middle_count_done_c and count_24d_srl_r(22);
-- The flop extends the shift register to 24 bits for counting. It is held at
-- zero while channel up is low to clear the register, and is seeded with a single
-- 1 when channel up transitions from 0 to 1
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
count_24d_flop_r <= '0' after DLY;
elsif( (CHANNEL_UP and reset_r) = '1') then
count_24d_flop_r <= '1' after DLY;
elsif( middle_count_done_c = '1') then
count_24d_flop_r <= cc_idle_count_done_c after DLY;
end if;
end if;
end process;
-- Because UFC and CC sequences are not allowed to preempt one another, there
-- there is a warning signal to indicate an impending CC sequence. This signal
-- is used to prevent UFC messages from starting.
-- For 1 lane, we need an 10-cycle count.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
prepare_count_r <= (cc_idle_count_done_c & prepare_count_r(0 to 8)) after DLY;
end if;
end process;
-- The state machine stays in the prepare_cc state from when the cc idle
-- count finishes, to when the prepare count has finished. While in this
-- state, UFC operations cannot start, which prevents them from having to
-- be pre-empted by CC sequences.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
WARN_CC <= '0' after DLY;
elsif(cc_idle_count_done_c = '1') then
WARN_CC <= '1' after DLY;
elsif(prepare_count_r(9) = '1') then
WARN_CC <= '0' after DLY;
end if;
end if;
end process;
-- Track the state of channel up on the previous cycle. We use this signal to determine
-- when to seed the shift register counters with ones
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
reset_r <= not CHANNEL_UP after DLY;
end if;
end process;
--Do a CC after CHANNEL_UP is asserted or CC_warning is complete.
start_cc_c <= prepare_count_r(9) or (CHANNEL_UP and reset_r);
-- This SRL counter keeps track of the number of cycles spent in the CC
-- sequence. It starts counting when the prepare_cc state ends, and
-- finishes counting after 6 cycles have passed.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
cc_count_r <= ( (not CHANNEL_UP or prepare_count_r(9)) & cc_count_r(0 to 4) ) after DLY;
end if;
end process;
-- The TX_LL module stays in the do_cc state for 6 cycles. It starts
-- when the prepare_cc state ends.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
DO_CC <= '0' after DLY;
elsif(start_cc_c = '1') then
DO_CC <= '1' after DLY;
elsif(cc_count_r(5) = '1') then
DO_CC <= '0' after DLY;
end if;
end if;
end process;
end RTL;
|
Library ieee;
use ieee.std_logic_1164.all;
entity segment_decoder is
port(
hexIn: in std_logic_vector(3 downto 0);
segmentMux: out std_logic_vector(6 downto 0)
);
end segment_decoder;
architecture primary of segment_decoder is
begin
process(hexIn) begin
case hexIn is
when "0000" => segmentMux <= "0000001";
when "0001" => segmentMux <= "1111001";
when "0010" => segmentMux <= "0100100";
when "0011" => segmentMux <= "0110000";
when "0100" => segmentMux <= "0011001";
when "0101" => segmentMux <= "0010010";
when "0110" => segmentMux <= "0000010";
when "0111" => segmentMux <= "1111000";
when "1000" => segmentMux <= "0000000";
when "1001" => segmentMux <= "0010000";
when "1010" => segmentMux <= "0001000";
when "1011" => segmentMux <= "0000011";
when "1100" => segmentMux <= "1000110";
when "1101" => segmentMux <= "0100001";
when "1110" => segmentMux <= "0000110";
when "1111" => segmentMux <= "0001110";
end case;
end process;
end primary; |
--
-- Test Bench for Link interface.
--
-- Unfortunately rather incomplete.
-- The following items are verified:
-- * reset;
-- * link start, NULL exchange, FCT exchange;
-- * link autostart on first NULL;
-- * send/receive time codes, data characters, EOP/EEP;
-- * detection of timeout, disconnection, parity error, escape error.
--
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use std.textio.all;
use work.spwpkg.all;
entity spwlink_tb is
-- Tests should be done with several different combinations
-- of values for the generics.
generic (
-- System clock frequency
sys_clock_freq: real := 20.0e6 ;
-- Receiver sample clock frequency
rx_clock_freq: real := 20.0e6 ;
-- Transmitter clock frequency
tx_clock_freq: real := 20.0e6 ;
-- Input bit rate
input_rate: real := 10.0e6 ;
-- TX clock division factor (actual factor is one tx_clock_div+1)
tx_clock_div: integer := 1 ;
-- Receiver implementation
rximpl: spw_implementation_type := impl_generic ;
-- Bits per sysclk for fast receiver
rxchunk: integer := 1 ;
-- Transmitter implementation
tximpl: spw_implementation_type := impl_generic ;
-- Wait before starting test bench
startwait: time := 0 sec
);
end spwlink_tb;
architecture tb_arch of spwlink_tb is
-- Bit periods for incoming / outgoing signal
constant inbit_period: time := (1 sec) / input_rate ;
constant outbit_period: time := (1 sec) * real(tx_clock_div + 1) / tx_clock_freq ;
constant txclk_period: time := (1 sec) / tx_clock_freq ;
-- clock generation
signal sys_clock_enable: std_logic := '0';
signal sysclk: std_logic;
signal rxclk: std_logic;
signal txclk: std_logic;
-- output monitoring
type t_output_chars is array(natural range <>) of std_logic_vector(9 downto 0);
signal output_collect: std_logic;
signal output_ptr: integer;
signal output_bits: std_logic_vector(0 to 4095);
signal output_nchars: integer;
signal output_chars: t_output_chars(0 to 4095);
-- input generation
signal input_par: std_logic;
signal input_idle: std_logic;
signal input_pattern: integer := 0;
signal input_strobeflip: std_logic := '0';
-- interconnect signals
signal s_linki: spw_link_in_type;
signal s_linko: spw_link_out_type;
signal s_rxen: std_logic;
signal s_recvo: spw_recv_out_type;
signal s_xmiti: spw_xmit_in_type;
signal s_xmito: spw_xmit_out_type;
signal s_inact: std_logic;
signal s_inbvalid: std_logic;
signal s_inbits: std_logic_vector(rxchunk-1 downto 0);
-- interface signals
signal rst: std_logic := '1';
signal autostart: std_logic;
signal linkstart: std_logic;
signal linkdis: std_logic;
signal divcnt: std_logic_vector(7 downto 0) := (others => '0');
signal tick_in: std_logic;
signal ctrl_in: std_logic_vector(1 downto 0);
signal time_in: std_logic_vector(5 downto 0);
signal rxroom: std_logic_vector(5 downto 0);
signal txwrite: std_logic;
signal txflag: std_logic;
signal txdata: std_logic_vector(7 downto 0);
signal txrdy: std_logic;
signal tick_out: std_logic;
signal ctrl_out: std_logic_vector(1 downto 0);
signal time_out: std_logic_vector(5 downto 0);
signal rxchar: std_logic;
signal rxflag: std_logic;
signal rxdata: std_logic_vector(7 downto 0);
signal started: std_logic;
signal connecting:std_logic;
signal running: std_logic;
signal errdisc: std_logic;
signal errpar: std_logic;
signal erresc: std_logic;
signal errcred: std_logic;
signal spw_di: std_logic;
signal spw_si: std_logic;
signal spw_do: std_logic;
signal spw_so: std_logic;
-- misc
signal errany: std_logic;
procedure print(i: integer) is
variable v: LINE;
begin
write(v, i);
writeline(output, v);
end procedure;
procedure print(x: std_logic_vector) is
variable v: LINE;
begin
write(v, to_bitvector(x));
writeline(output, v);
end procedure;
procedure prints(s: string) is
variable v: LINE;
begin
write(v, s);
writeline(output, v);
end procedure;
procedure print(lbl: string; x: integer) is
variable v: LINE;
begin
write(v, lbl & " = ");
write(v, x);
writeline(output, v);
end procedure;
procedure print(lbl: string; x: real) is
variable v: LINE;
begin
write(v, lbl & " = ");
write(v, x);
writeline(output, v);
end procedure;
begin
-- Instantiate components.
spwlink_inst: spwlink
generic map (
reset_time => integer(sys_clock_freq * 0.0000064) ) -- 6.4 us
port map (
clk => sysclk,
rst => rst,
linki => s_linki,
linko => s_linko,
rxen => s_rxen,
recvo => s_recvo,
xmiti => s_xmiti,
xmito => s_xmito );
spwrecv_inst: spwrecv
generic map (
disconnect_time => integer(sys_clock_freq * 0.00000085), -- 850 ns
rxchunk => rxchunk )
port map (
clk => sysclk,
rxen => s_rxen,
recvo => s_recvo,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits );
spwxmit_if: if tximpl = impl_generic generate
spwxmit_inst: spwxmit
port map (
clk => sysclk,
rst => rst,
divcnt => divcnt,
xmiti => s_xmiti,
xmito => s_xmito,
spw_so => spw_so,
spw_do => spw_do );
end generate;
spwxmit_fast_if: if tximpl = impl_fast generate
spwxmit_fast_inst: spwxmit_fast
port map (
clk => sysclk,
txclk => txclk,
rst => rst,
divcnt => divcnt,
xmiti => s_xmiti,
xmito => s_xmito,
spw_so => spw_so,
spw_do => spw_do );
end generate;
spwrecvfront_generic_if: if rximpl = impl_generic generate
spwrecvfront_generic_inst: spwrecvfront_generic
port map (
clk => sysclk,
rxen => s_rxen,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
spwrecvfront_fast_if: if rximpl = impl_fast generate
spwrecvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => sysclk,
rxclk => rxclk,
rxen => s_rxen,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
s_linki <= ( autostart => autostart,
linkstart => linkstart,
linkdis => linkdis,
rxroom => rxroom,
tick_in => tick_in,
ctrl_in => ctrl_in,
time_in => time_in,
txwrite => txwrite,
txflag => txflag,
txdata => txdata );
started <= s_linko.started;
connecting <= s_linko.connecting;
running <= s_linko.running;
errdisc <= s_linko.errdisc;
errpar <= s_linko.errpar;
erresc <= s_linko.erresc;
errcred <= s_linko.errcred;
txrdy <= s_linko.txack;
tick_out <= s_linko.tick_out;
ctrl_out <= s_linko.ctrl_out;
time_out <= s_linko.time_out;
rxchar <= s_linko.rxchar;
rxflag <= s_linko.rxflag;
rxdata <= s_linko.rxdata;
-- Logic OR of all error signals.
errany <= errdisc or errpar or erresc or errcred;
-- Generate system clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
sysclk <= '1';
wait for (0.5 sec) / sys_clock_freq;
sysclk <= '0';
wait for (0.5 sec) / sys_clock_freq;
end process;
-- Generate rx sample clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
rxclk <= '1';
wait for (0.5 sec) / rx_clock_freq;
rxclk <= '0';
wait for (0.5 sec) / rx_clock_freq;
end process;
-- Generate tx clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
txclk <= '1';
wait for (0.5 sec) / tx_clock_freq;
txclk <= '0';
wait for (0.5 sec) / tx_clock_freq;
end process;
-- Collect output bits on SPW_DO and SPW_SO.
process is
variable t_last: time;
variable output_last_do: std_logic;
variable output_last_so: std_logic;
begin
if output_collect = '1' then
-- wait for next bit
if output_ptr <= output_bits'high then
output_bits(output_ptr) <= spw_do;
output_ptr <= output_ptr + 1;
end if;
output_last_do := spw_do;
output_last_so := spw_so;
t_last := now;
wait until (output_collect = '0') or (output_last_do /= spw_do) or (output_last_so /= spw_so);
if output_collect = '1' and output_ptr > 1 then
assert now > t_last + outbit_period - 1 ns
report "output bit period too short";
assert now < t_last + outbit_period + 1 ns
report "output bit period too long";
end if;
else
-- reset
output_ptr <= 0;
output_last_do := '0';
output_last_so := '0';
wait until output_collect = '1';
end if;
end process;
-- Collect received data on rxdata and tick_out.
process is
begin
wait until ((output_collect = '1') and rising_edge(sysclk)) or
((output_collect = '0') and (output_nchars /= 0));
if output_collect = '0' then
output_nchars <= 0;
elsif rising_edge(sysclk) and (output_nchars <= output_chars'high) then
assert (rxchar = '0') or (tick_out = '0');
if tick_out = '1' then
output_chars(output_nchars) <= "10" & ctrl_out & time_out;
output_nchars <= output_nchars + 1;
elsif rxchar = '1' then
output_chars(output_nchars) <= "0" & (rxflag) & rxdata;
output_nchars <= output_nchars + 1;
end if;
end if;
end process;
-- Generate input data.
process is
procedure input_reset is
begin
spw_di <= '0';
spw_si <= input_strobeflip;
input_par <= '0';
end procedure;
procedure genbit(b: std_logic) is
begin
spw_si <= not (spw_si xor spw_di xor b);
spw_di <= b;
wait for inbit_period;
end procedure;
procedure genfct is
begin
genbit(input_par);
genbit('1');
genbit('0');
input_par <= '0';
genbit('0');
end procedure;
procedure genesc is
begin
genbit(input_par);
genbit('1');
genbit('1');
input_par <= '0';
genbit('1');
end procedure;
procedure geneop(e: std_logic) is
begin
genbit(input_par);
genbit('1');
genbit(e);
input_par <= '1';
genbit(not e);
end procedure;
procedure gendat(dat: std_logic_vector(7 downto 0)) is
begin
genbit(not input_par);
genbit('0');
genbit(dat(0)); genbit(dat(1)); genbit(dat(2)); genbit(dat(3));
genbit(dat(4)); genbit(dat(5)); genbit(dat(6));
input_par <= dat(0) xor dat(1) xor dat(2) xor dat(3) xor
dat(4) xor dat(5) xor dat(6) xor dat(7);
genbit(dat(7));
end procedure;
begin
input_idle <= '1';
input_reset;
wait until input_pattern /= 0;
input_idle <= '0';
while input_pattern /= 0 loop
if input_pattern = 1 then
-- NULL tokens
genesc; genfct;
elsif input_pattern = 2 then
-- FCT tokens
genfct;
elsif input_pattern = 3 then
-- invalid bit pattern
genbit('0');
genbit('1');
elsif input_pattern = 4 then
-- EOP token
geneop('0');
elsif input_pattern = 5 then
-- FCT, TIME, 8 chars, NULLs
genfct;
genesc; gendat("00111000");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
while input_pattern = 5 loop
genesc; genfct;
end loop;
elsif input_pattern = 6 then
-- ESC tokens
genesc;
elsif input_pattern = 7 then
-- FCT, NULL, NULL, EOP, EEP, NULLs
genfct;
genesc; genfct;
genesc; genfct;
geneop('0');
geneop('1');
while input_pattern = 7 loop
genesc; genfct;
end loop;
elsif input_pattern = 8 then
-- FCT, NULL, NULL, NULL, NULL, NULL, char, parity error
genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
gendat("01010101");
genbit(not input_par);
genbit('0');
genbit('1'); genbit('0'); genbit('1'); genbit('0');
genbit('1'); genbit('0'); genbit('1');
input_par <= '1'; -- wrong parity !!
genbit('0');
while input_pattern = 8 loop
genesc; genfct;
end loop;
elsif input_pattern = 9 then
-- FCT, FCT, NULLs
genfct;
genfct;
while input_pattern = 9 loop
genesc; genfct;
end loop;
elsif input_pattern = 10 then
-- data and strobe both high
spw_di <= '1';
spw_si <= not input_strobeflip;
wait until input_pattern /= 10;
else
assert false;
end if;
end loop;
end process;
-- Main process.
process is
-- Skip NULL tokens and return position of first non-NULL.
function skip_null(data: in std_logic_vector; start: in integer; len: in integer) return integer is
variable i: integer;
begin
i := start;
if (i + 7 < len) and (data((i+1) to (i+7)) = "1110100") then
i := i + 8;
end if;
while (i + 7 < len) and (data(i to (i+7)) = "01110100") loop
i := i + 8;
end loop;
return i;
end function;
function check_parity(data: in std_logic_vector; start: in integer; len: in integer) return boolean is
variable i: integer;
variable p: std_logic;
begin
i := start;
p := data(start);
while i + 3 < len loop
if data(i+1) = '1' then
if data(0) /= p then return false; end if;
p := data(2) xor data(3);
i := i + 4;
else
if i + 9 < len then return true; end if;
if data(0) /= not p then return false; end if;
p := not (data(2) xor data(3) xor data(4) xor data(5) xor
data(6) xor data(7) xor data(8) xor data(9));
i := i + 10;
end if;
end loop;
return true;
end function;
variable i: integer;
begin
-- Wait for start of test.
wait for startwait;
-- Initialize.
rst <= '1';
input_pattern <= 0;
input_strobeflip <= '0';
sys_clock_enable <= '1';
output_collect <= '0';
-- Say hello
report "Starting spwlink test bench";
print(" sys_clock_freq", sys_clock_freq);
print(" rx_clock_freq ", rx_clock_freq);
print(" tx_clock_freq ", tx_clock_freq);
print(" input_rate ", input_rate);
print(" tx_clock_div ", tx_clock_div);
case rximpl is
when impl_generic => prints(" rximpl = impl_generic");
when impl_fast => prints(" rximpl = impl_fast");
end case;
print(" rxchunk ", rxchunk);
case tximpl is
when impl_generic => prints(" tximpl = impl_generic");
when impl_fast => prints(" tximpl = impl_fast");
end case;
-- Test 1: Reset.
autostart <= '0'; linkstart <= '0'; linkdis <= '0';
divcnt <= std_logic_vector(to_unsigned(tx_clock_div, divcnt'length));
tick_in <= '0'; ctrl_in <= "00"; time_in <= "000000"; rxroom <= "000000";
txwrite <= '0'; txflag <= '0'; txdata <= "00000000";
wait until rising_edge(sysclk);
wait until rising_edge(sysclk);
wait for 1 ns;
rst <= '0';
assert (txrdy = '0') report " 1. reset (txrdy = 0)";
assert (tick_out = '0') report " 1. reset (tick_out = 0)";
assert (rxchar = '0') report " 1. reset (rxchar = 0)";
assert (started = '0') report " 1. reset (started = 0)";
assert (connecting = '0') report " 1. reset (connecting = 0)";
assert (running = '0') report " 1. reset (running = 0)";
assert (errdisc = '0') report " 1. reset (errdisc = 0)";
assert (errpar = '0') report " 1. reset (errpar = 0)";
assert (erresc = '0') report " 1. reset (erresc = 0)";
assert (errcred = '0') report " 1. reset (errcred = 0)";
assert (spw_do = '0') report " 1. reset (spw_do = 0)";
assert (spw_so = '0') report " 1. reset (spw_so = 0)";
-- Test 2: Remain idle after one clock cycle.
wait until rising_edge(sysclk);
wait until falling_edge(sysclk);
assert (started = '0') and (running = '0')
report " 2. init (state)";
assert (spw_do = '0') and (spw_so = '0')
report " 2. init (SPW idle)";
-- Test 3: Move to Ready state.
wait on started, running, spw_do, spw_so for 50 us;
assert (started = '0') and (running = '0')
report " 3. ready (state)";
assert (spw_do = '0') and (spw_so = '0')
report " 3. ready (SPW idle)";
-- Test 4: Start link; wait for NULL patterns.
linkstart <= '1';
rxroom <= "001111";
wait on started, connecting, running, spw_do, spw_so for 1 us;
assert (started = '1') and (running = '0')
report " 4. nullgen (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (started = '1') and (connecting = '0') and (running = '0') and
(spw_do = '0') and (spw_so = '1')
report " 4. nullgen (SPW strobe)";
output_collect <= '1';
wait on started, connecting, running for (7.1 * outbit_period);
assert (started = '1') and (running = '0')
report " 4. nullgen (state 2)";
assert (output_ptr = 8) and (output_bits(0 to 7) = "01110100")
report " 4. nullgen (NULL 1)";
-- got the first NULL, wait for the second one ...
wait on started, connecting, running for (8.0 * outbit_period);
assert (started = '1') and (running = '0')
report " 4. nullgen (state 3)";
assert (output_ptr = 16) and (output_bits(8 to 15) = "01110100")
report " 4. nullgen (NULL 2)";
output_collect <= '0';
-- Test 5: Timeout in Started state.
wait on started, connecting, running, errany for 9.5 us - (15.0 * outbit_period);
assert (started = '1') and (running = '0') and (errany = '0')
report " 5. started_timeout (wait)";
wait on started, connecting, running, errany for 4 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 5. started_timeout (trigger)";
wait for (3.1 * outbit_period + 20 * txclk_period);
assert (spw_do = '0') and (spw_so = '0')
report " 5. started_timeout (SPW to zero)";
-- Test 6: Start link; simulate NULL pattern; wait for FCT pattern.
wait on started, connecting, running, spw_so for 18 us - (3.1 * outbit_period + 20 * txclk_period);
assert (started = '0') and (connecting = '0') and (running = '0') and (spw_so = '0')
report " 6. fctgen (SPW idle)";
wait on started, connecting, running, spw_so for 2 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 6. fctgen (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (spw_do = '0') and (spw_so = '1')
report " 6. fctgen (SPW strobe)";
output_collect <= '1';
input_pattern <= 1;
wait on started, connecting, running for 8 us;
assert (started = '0') and (connecting = '1') and (running = '0')
report " 6. fctgen (detect NULL)";
wait for (1.1 sec) / sys_clock_freq;
wait on started, connecting, running, errany for 12 us;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 6. fctgen (connecting failed early)";
assert (output_ptr > 7) and (output_bits(0 to 7) = "01110100")
report " 6. fctgen (gen NULL)";
i := skip_null(output_bits, 0, output_ptr);
assert (i > 0) and (i + 11 < output_ptr) and (output_bits(i to (i+11)) = "010001110100")
report " 6. fctgen (gen FCT NULL)";
output_collect <= '0';
-- Test 7: Timeout in Connecting state.
wait on started, connecting, running, errany for 4 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 7. connecting_timeout";
input_pattern <= 0;
wait until rising_edge(sysclk);
-- Test 8: Autostart link; simulate NULL and FCT; move to Run state; disconnect.
linkstart <= '0';
autostart <= '1';
rxroom <= "010000";
wait on started, connecting, running, errany for 50 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 8. autostart (wait)";
output_collect <= '1';
input_pattern <= 1;
wait on started, connecting, running for 200 ns + 24 * inbit_period;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 8. autostart (Started)";
input_pattern <= 9;
wait on started, connecting, running for 1 us;
assert (started = '0') and (connecting = '1') and (running = '0')
report " 8. autostart (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 8. autostart (Run)";
input_pattern <= 1;
txwrite <= '1';
if txrdy = '0' then
wait on running, errany, txrdy for (20 * outbit_period);
end if;
assert (running = '1') and (errany = '0') and (txrdy = '1')
report " 8. running (txrdy = 1)";
txwrite <= '0';
wait on running, errany for 50 us;
assert (running = '1') and (errany = '0')
report " 8. running stable";
assert output_bits(1 to 24) = "011101000100010001110100"
report " 8. NULL FCT FCT NULL";
output_collect <= '0';
linkdis <= '1';
wait on started, running, errany for (2.1 sec) / sys_clock_freq;
assert (started = '0') and (running = '0') and (errany = '0')
report " 8. link disable";
autostart <= '0';
linkdis <= '0';
input_pattern <= 0;
wait until rising_edge(sysclk);
-- Test 9: Start link until Run state; disconnect.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on started, connecting, running for 20 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 9. running_disconnect (Started)";
linkstart <= '0';
wait until rising_edge(sysclk);
input_pattern <= 9;
wait on started, connecting, running, errany for 20 * inbit_period;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 9. running_disconnect (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 9. running_disconnect (Run)";
input_pattern <= 0;
wait until input_idle = '1';
wait on started, connecting, running, errany for 1500 ns;
assert errdisc = '1'
report " 9. running_disconnect (errdisc = 1)";
if running = '1' then
wait on started, connecting, running for (1.1 sec) / sys_clock_freq;
end if;
assert (started = '0') and (connecting = '0') and (running = '0')
report " 9. running_disconnect (running = 0)";
wait until rising_edge(sysclk);
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 9. running_disconnect (reset)";
wait until rising_edge(sysclk);
-- Test 10: Junk signal before starting link.
autostart <= '1';
input_pattern <= 3;
wait on started, errany for 6 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (ignore noise)";
input_pattern <= 2;
wait on started, errany for 4 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (ignore FCT)";
input_pattern <= 0;
wait until input_idle = '1';
input_pattern <= 1; -- send NULL
wait until input_idle = '0';
input_pattern <= 3; -- send invalid pattern; spw should now reset
wait on started, errany for 8 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (hidden reset)";
input_pattern <= 1; -- send NULL
wait on started, errany for 10 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (waiting)";
wait on started, errany for 10 us;
assert (started = '1') and (errany = '0')
report "10. junk signal (Started)";
autostart <= '0';
rst <= '1';
wait until rising_edge(sysclk);
rst <= '0';
wait until rising_edge(sysclk);
assert (started = '0') and (errany = '0')
report "10. junk signal (rst)";
wait until rising_edge(sysclk);
-- Test 11: Incoming EOP before first FCT.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "11. unexpected EOP (Connecting)";
input_pattern <= 4;
linkstart <= '0';
wait on connecting, running, errany for 200 ns + 24 * inbit_period;
assert (connecting = '0') and (running = '0') and (errany = '0')
report "11. unexpected EOP (reset on EOP)";
input_pattern <= 0;
wait for (10 * outbit_period);
-- Test 12: Send and receive characters, time codes, abort on double ESC.
wait until falling_edge(sysclk);
linkstart <= '1';
wait on started, errany for 21 us;
assert (started = '1') and (errany = '0')
report "12. characters (Started)";
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
tick_in <= '1';
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "12. characters (Connecting)";
wait until output_ptr > 9 for 2 us;
input_pattern <= 5; -- FCT, TIME, 8 chars, NULLs
time_in <= "000111";
txwrite <= '1';
txflag <= '0';
txdata <= "01101100";
wait on connecting, running, errany for 200 ns + (24 * inbit_period);
assert (running = '1') and (errany = '0')
report "12. characters (Run)";
wait until rising_edge(sysclk);
assert (running = '1') and (errany = '0')
report "12. characters (running = 1)";
tick_in <= '0';
wait for 4 * outbit_period; -- wait until first FCT sent
rxroom <= "000111";
wait until txrdy = '1' for 200 ns + (20 * outbit_period);
assert (running = '1') and (txrdy = '1')
report "12. characters (txrdy = 1)";
wait on running, errany for 50 us + (80 * outbit_period);
assert (running = '1') and (errany = '0')
report "12. characters (stable)";
input_pattern <= 6; -- just ESC tokens
wait on running, errany for 200 ns + (32 * inbit_period);
assert erresc = '1'
report "12. characters (erresc = 1)";
wait until rising_edge(sysclk);
wait for 1 ns;
assert (started = '0') and (connecting = '0') and (running = '0')
report "12. characters (reset)";
assert (output_ptr > 8) and (output_bits(1 to 8) = "01110100")
report "12. characters (gen NULL 1)";
i := skip_null(output_bits, 1, output_ptr);
assert (i > 0) and (output_bits(i to (i+3)) = "0100")
report "12. characters (gen FCT)";
i := skip_null(output_bits, i + 4, output_ptr);
assert (i + 13 < output_ptr) and (output_bits(i to (i+13)) = "01111011100000")
report "12. characters (gen TimeCode)";
i := i + 14;
assert (i + 79 < output_ptr) and (output_bits(i to (i+79)) = "00001101101000110110100011011010001101101000110110100011011010001101101000110110")
report "12. characters (gen Data)";
i := i + 80;
assert (i + 7 < output_ptr) and (output_bits(i to (i+7)) = "01110100")
report "12. characters (gen NULL 2)";
assert (output_nchars > 0) and (output_chars(0) = "1000111000")
report "12. characters (got TimeCode)";
assert (output_nchars > 1) and (output_chars(1) = "0001010101")
report "12. characters (got byte 1)";
assert (output_nchars > 2) and (output_chars(2) = "0010101010")
report "12. characters (got byte 2)";
assert (output_nchars > 3) and (output_chars(3) = "0001010101")
report "12. characters (got byte 3)";
assert (output_nchars > 4) and (output_chars(4) = "0010101010")
report "12. characters (got byte 4)";
assert check_parity(output_bits, 1, output_ptr)
report "12. parity of output bits";
output_collect <= '0';
input_pattern <= 0;
txwrite <= '0';
linkstart <= '0';
wait for (20 * outbit_period);
-- Test 13: Send and receive EOP, EEP, abort on credit error.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "13. eop, eep (Connecting)";
wait until output_ptr > 9 for 2 us;
input_pattern <= 7; -- FCT, NULL, NULL, EOP, EEP, NULLs
wait for (1.1 sec) / sys_clock_freq;
wait on connecting, running, errany for 12 us;
assert (running = '1') and (errany = '0')
report "13. eop, eep (Run)";
wait for 1 ns;
txwrite <= '1';
txflag <= '1';
txdata <= "01101100";
wait until rising_edge(sysclk) and txrdy = '1' for 1 us + (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 1)";
rxroom <= "000111" after 1 ns;
txdata <= "00000001" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for 1 us + (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 2)";
txdata <= "00000000" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 3)";
txdata <= "11111111" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 4)";
txdata <= "11111110" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 5)";
txdata <= "01010101" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 6)";
txdata <= "10101010" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 7)";
txdata <= "01010101" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 8)";
txdata <= "10101010" after 1 ns;
wait until rising_edge(sysclk) and (txrdy = '1') for (14 * outbit_period);
assert (txrdy = '0') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 9)";
txwrite <= '0';
txflag <= '0';
wait on running, errany for (10 * outbit_period);
assert (running = '1') and (errany = '0')
report "13. eop, eep (flush out)";
input_pattern <= 2; -- FCT tokens
wait on running, errany for (80 * inbit_period);
assert errcred = '1'
report "13. eop, eep (errcred = 1)";
wait until running = '0';
assert (output_ptr > 8) and (output_bits(1 to 8) = "01110100")
report "13. eop, eep (gen NULL 1)";
i := skip_null(output_bits, 1, output_ptr);
assert (i > 0) and (output_bits(i to (i+3)) = "0100")
report "13. eop, eep (gen FCT)";
i := i + 4;
for j in 0 to 3 loop
i := skip_null(output_bits, i, output_ptr);
assert (i + 3 < output_ptr) and (output_bits(i+1 to (i+3)) = "101")
report "13. eop, eep (eop)";
i := skip_null(output_bits, i + 4, output_ptr);
assert (i + 3 < output_ptr) and (output_bits(i+1 to (i+3)) = "110")
report "13. eop, eep (eep)";
i := i + 4;
end loop;
assert (i + 8 < output_ptr) and (output_bits(i to (i+8)) = "111101000")
report "13. eop, eep (gen NULL 2)";
assert check_parity(output_bits, 1, output_ptr)
report "12. parity of output bits";
assert (output_nchars > 0) and (output_chars(0) = "0100000000")
report "13. eop, eep (got EOP)";
assert (output_nchars = 2) and (output_chars(1) = "0100000001")
report "13. eop, eep (got EEP)";
output_collect <= '0';
input_pattern <= 0;
linkstart <= '0';
wait until rising_edge(sysclk);
-- Test 14: Abort on parity error.
wait for 10 us;
assert spw_do = '0' and spw_so = '0'
report "14. output still babbling";
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
wait for 1 ns; -- ghdl is totally fucked up
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "14. partity (Connecting)";
input_pattern <= 8; -- FCT, NULL, NULL, NULL, NULL, NULL, char, error
wait for (1.1 sec) / sys_clock_freq;
wait on running, errany for 12 us;
assert (running = '1') and (errany = '0')
report "14. parity (Run)";
wait on running, errany for 150 ns + (84 * inbit_period);
assert errpar = '1'
report "14. parity (errpar = 1)";
wait until running = '0';
assert (output_nchars = 1) and (output_chars(0) = "0001010101")
report "14. parity (received char)";
output_collect <= '0';
input_pattern <= 0;
linkstart <= '0';
wait until rising_edge(sysclk);
-- Test 15: start with wrong strobe polarity.
input_strobeflip <= '1';
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on started, connecting, running for 20 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 15. weird_strobe (Started)";
linkstart <= '0';
wait until rising_edge(sysclk);
input_pattern <= 9;
wait on started, connecting, running, errany for 20 * inbit_period;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 15. weird_strobe (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 15. weird_strobe (Run)";
linkdis <= '1';
wait until rising_edge(sysclk);
input_pattern <= 0;
input_strobeflip <= '0';
wait until input_idle = '1';
linkdis <= '0';
wait until rising_edge(sysclk);
-- Test 16: start with wrong data polarity.
input_pattern <= 10;
linkstart <= '1';
rxroom <= "001111";
wait on started, connecting, running for 25 us;
assert (started = '1') and (running = '0')
report " 16. weird_data (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (started = '1') and (connecting = '0') and (running = '0') and
(spw_do = '0') and (spw_so = '1')
report " 16. weird_data (SPW strobe)";
output_collect <= '1';
wait on started, connecting, running for (7.1 * outbit_period);
assert (started = '1') and (running = '0')
report " 16. weird_data (state 2)";
assert (output_ptr = 8) and (output_bits(0 to 7) = "01110100")
report " 16. weird_data (NULL 1)";
-- got the first NULL, wait for the second one ...
wait on started, connecting, running for (8.0 * outbit_period);
assert (started = '1') and (running = '0')
report " 16. weird_data (state 3)";
assert (output_ptr = 16) and (output_bits(8 to 15) = "01110100")
report " 16. weird_data (NULL 2)";
output_collect <= '0';
linkstart <= '0';
linkdis <= '1';
input_pattern <= 0;
wait until rising_edge(sysclk);
linkdis <= '0';
wait until rising_edge(sysclk);
-- Stop simulation
input_pattern <= 0;
wait for 100 us;
sys_clock_enable <= '0';
report "Done.";
wait;
end process;
end tb_arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 16:38:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:04 10/20/2017
-- Design Name:
-- Module Name: SEU_30 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEU_30 is
Port ( Imm_30 : in STD_LOGIC_VECTOR (29 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0));
end SEU_30;
architecture Behavioral of SEU_30 is
begin
process (Imm_30 ) begin
if(Imm_30(29) = '1')then
Imm_32<= "11" & Imm_30;
elsif(Imm_30(29) = '0')then
Imm_32<= "00" & Imm_30;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:04 10/20/2017
-- Design Name:
-- Module Name: SEU_30 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEU_30 is
Port ( Imm_30 : in STD_LOGIC_VECTOR (29 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0));
end SEU_30;
architecture Behavioral of SEU_30 is
begin
process (Imm_30 ) begin
if(Imm_30(29) = '1')then
Imm_32<= "11" & Imm_30;
elsif(Imm_30(29) = '0')then
Imm_32<= "00" & Imm_30;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architecture logic of alu4 is
signal s0, s1, s2, s3, s4, s5, s6, s7 : std_logic_vector(3 downto 0);
signal c0, c1 : std_logic;
begin
cADD: ADD4 port map(A, B, CIN, s0, c0);
cOR: BWOR4 port map(A, B, s1);
cAND: BWAND4 port map(A, B, s2);
cINV1: PINV4 port map(B, SEL(2), s4);
cSUB: ADD4 port map(A, s4, CIN, s3, c1);
process(LESS, s3, s6)
begin
if LESS = '1' then
s6 <= "0001";
SET <= s3(3);
else
s6 <= "0000";
set <= s3(3);
end if;
end process;
MUX0: MUX4X4 port map(SEL(1) & (SEL(2) or SEL(0)), s2, s1, s0, s3, s5);
MUX1: MUX4X4 port map('0' & (SEL(2) and SEL(0)), s5, s6, "0000", "0000", s7);
process(SEL, c0, c1)
begin
if SEL = "010" then
COUT <= c0;
elsif SEL = "110" then
COUT <= c1;
end if;
end process;
process(s7, A, B)
begin
if s7 = "0000" then
ZERO <= '1';
else
ZERO <= '0';
end if;
if ((A(3) = B(3)) and (s7(3) /= B(3))) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
end process;
F <= s7;
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architecture logic of alu4 is
signal s0, s1, s2, s3, s4, s5, s6, s7 : std_logic_vector(3 downto 0);
signal c0, c1 : std_logic;
begin
cADD: ADD4 port map(A, B, CIN, s0, c0);
cOR: BWOR4 port map(A, B, s1);
cAND: BWAND4 port map(A, B, s2);
cINV1: PINV4 port map(B, SEL(2), s4);
cSUB: ADD4 port map(A, s4, CIN, s3, c1);
process(LESS, s3, s6)
begin
if LESS = '1' then
s6 <= "0001";
SET <= s3(3);
else
s6 <= "0000";
set <= s3(3);
end if;
end process;
MUX0: MUX4X4 port map(SEL(1) & (SEL(2) or SEL(0)), s2, s1, s0, s3, s5);
MUX1: MUX4X4 port map('0' & (SEL(2) and SEL(0)), s5, s6, "0000", "0000", s7);
process(SEL, c0, c1)
begin
if SEL = "010" then
COUT <= c0;
elsif SEL = "110" then
COUT <= c1;
end if;
end process;
process(s7, A, B)
begin
if s7 = "0000" then
ZERO <= '1';
else
ZERO <= '0';
end if;
if ((A(3) = B(3)) and (s7(3) /= B(3))) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
end process;
F <= s7;
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architecture logic of alu4 is
signal s0, s1, s2, s3, s4, s5, s6, s7 : std_logic_vector(3 downto 0);
signal c0, c1 : std_logic;
begin
cADD: ADD4 port map(A, B, CIN, s0, c0);
cOR: BWOR4 port map(A, B, s1);
cAND: BWAND4 port map(A, B, s2);
cINV1: PINV4 port map(B, SEL(2), s4);
cSUB: ADD4 port map(A, s4, CIN, s3, c1);
process(LESS, s3, s6)
begin
if LESS = '1' then
s6 <= "0001";
SET <= s3(3);
else
s6 <= "0000";
set <= s3(3);
end if;
end process;
MUX0: MUX4X4 port map(SEL(1) & (SEL(2) or SEL(0)), s2, s1, s0, s3, s5);
MUX1: MUX4X4 port map('0' & (SEL(2) and SEL(0)), s5, s6, "0000", "0000", s7);
process(SEL, c0, c1)
begin
if SEL = "010" then
COUT <= c0;
elsif SEL = "110" then
COUT <= c1;
end if;
end process;
process(s7, A, B)
begin
if s7 = "0000" then
ZERO <= '1';
else
ZERO <= '0';
end if;
if ((A(3) = B(3)) and (s7(3) /= B(3))) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
end process;
F <= s7;
end logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architecture logic of alu4 is
signal s0, s1, s2, s3, s4, s5, s6, s7 : std_logic_vector(3 downto 0);
signal c0, c1 : std_logic;
begin
cADD: ADD4 port map(A, B, CIN, s0, c0);
cOR: BWOR4 port map(A, B, s1);
cAND: BWAND4 port map(A, B, s2);
cINV1: PINV4 port map(B, SEL(2), s4);
cSUB: ADD4 port map(A, s4, CIN, s3, c1);
process(LESS, s3, s6)
begin
if LESS = '1' then
s6 <= "0001";
SET <= s3(3);
else
s6 <= "0000";
set <= s3(3);
end if;
end process;
MUX0: MUX4X4 port map(SEL(1) & (SEL(2) or SEL(0)), s2, s1, s0, s3, s5);
MUX1: MUX4X4 port map('0' & (SEL(2) and SEL(0)), s5, s6, "0000", "0000", s7);
process(SEL, c0, c1)
begin
if SEL = "010" then
COUT <= c0;
elsif SEL = "110" then
COUT <= c1;
end if;
end process;
process(s7, A, B)
begin
if s7 = "0000" then
ZERO <= '1';
else
ZERO <= '0';
end if;
if ((A(3) = B(3)) and (s7(3) /= B(3))) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
end process;
F <= s7;
end logic; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_H" &
"AS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_H" &
"AS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_H" &
"AS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_H" &
"AS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.10.2017 20:50:53
-- Design Name:
-- Module Name: bmp_wreiter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Ändert gelesene BMP datei und schreibt es in neues BMP.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use work.sim_bmppack.all;
library xil_defaultlib;
use xil_defaultlib.CAM_PKG.all;
entity bmp_wreiter is
GENERIC(byte_per_pixel : natural := 3);
Port(resetn : in STD_LOGIC;
clk : in STD_LOGIC;
start_frame : in STD_LOGIC;
x, y : in natural;
pixel_data : in std_logic_vector(23 downto 0);
pixel_data_ready : in STD_LOGIC;
sensor_data : in sensor_vector;
sensor_data_ready : in STD_LOGIC);
end bmp_wreiter;
architecture Behavioral of bmp_wreiter is
signal file_writed : std_logic := '0';
signal ImageWidth, ImageHeight, x_old : natural := 0;
signal px_data_tmp : std_logic_vector(23 downto 0) := (others => '0');
begin
writer : process is
variable tmp_sensor_vec : sensor_vector;
variable tmp_sensor : sensor;
begin
wait until rising_edge(clk);
if resetn = '1' then
if (x /= x_old) then
x_old <= x;
if (pixel_data_ready = '1') then -- selber bild abbilden
SetPixel(x, y, pixel_data);
end if;
if (sensor_data_ready = '1' ) then -- sensor abbilden
tmp_sensor := vector2sensor(sensor_data);
px_data_tmp (7 downto 0) <= conv_std_logic_vector(tmp_sensor.color.r, 8);
px_data_tmp (15 downto 8) <= conv_std_logic_vector(tmp_sensor.color.g, 8);
px_data_tmp (23 downto 16) <= conv_std_logic_vector(tmp_sensor.color.b, 8);
end if;
if (y = 640) then -- FIXME ende schreiben, dann
DrawCross(tmp_sensor.pos.x, tmp_sensor.pos.y, px_data_tmp);
if file_writed = '0' then
report "write File...";
WriteFile(" ..\..\test_out.bmp");
file_writed <= '1';
report "File is written.";
end if;
wait;
end if;
end if;
end if;
end process writer;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01499ent IS
END c08s08b00x00p14n01i01499ent;
ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
BEGIN
TESTING: PROCESS
subtype sub_int is integer range 1 to 2;
variable V1 : integer;
variable k1 : integer := 0;
variable k2 : integer := 0;
variable k3 : integer := 0;
variable k4 : integer := 0;
BEGIN
V1 := 0;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k1 := 1;
end case;
V1 := 1;
case V1 is
when sub_int'low
to sub_int'high => k2 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 2;
case V1 is
when sub_int'low
to sub_int'high => k3 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 3;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k4 := 1;
end case;
assert NOT(k1=1 and k2=1 and k3=1 and k4=1)
report "***PASSED TEST: c08s08b00x00p14n01i01499"
severity NOTE;
assert (k1=1 and k2=1 and k3=1 and k4=1)
report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01499arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01499ent IS
END c08s08b00x00p14n01i01499ent;
ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
BEGIN
TESTING: PROCESS
subtype sub_int is integer range 1 to 2;
variable V1 : integer;
variable k1 : integer := 0;
variable k2 : integer := 0;
variable k3 : integer := 0;
variable k4 : integer := 0;
BEGIN
V1 := 0;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k1 := 1;
end case;
V1 := 1;
case V1 is
when sub_int'low
to sub_int'high => k2 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 2;
case V1 is
when sub_int'low
to sub_int'high => k3 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 3;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k4 := 1;
end case;
assert NOT(k1=1 and k2=1 and k3=1 and k4=1)
report "***PASSED TEST: c08s08b00x00p14n01i01499"
severity NOTE;
assert (k1=1 and k2=1 and k3=1 and k4=1)
report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01499arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01499ent IS
END c08s08b00x00p14n01i01499ent;
ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
BEGIN
TESTING: PROCESS
subtype sub_int is integer range 1 to 2;
variable V1 : integer;
variable k1 : integer := 0;
variable k2 : integer := 0;
variable k3 : integer := 0;
variable k4 : integer := 0;
BEGIN
V1 := 0;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k1 := 1;
end case;
V1 := 1;
case V1 is
when sub_int'low
to sub_int'high => k2 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 2;
case V1 is
when sub_int'low
to sub_int'high => k3 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 3;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k4 := 1;
end case;
assert NOT(k1=1 and k2=1 and k3=1 and k4=1)
report "***PASSED TEST: c08s08b00x00p14n01i01499"
severity NOTE;
assert (k1=1 and k2=1 and k3=1 and k4=1)
report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01499arch;
|
-- Projeto gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Descrição da Entidade: somador.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador is
port(a, b, cin, opSomador:in std_logic; s, cout: out std_logic);
end somador;
architecture estrutural of somador is
component and2
port(a, b: in std_logic; y: out std_logic);
end component;
component xor2
port(a, b: in std_logic; y: out std_logic);
end component;
component and3
port(a, b, c: in std_logic; y: out std_logic);
end component;
component or3
port(a, b, c: in std_logic; y: out std_logic);
end component;
signal s_X1_X2, s_X2_A1, s_A1_O1, s_A2_O1, s_A3_O1, s_A4_O1: std_logic;
begin
X1: xor2 port map(a=>a, b=>b, y=>s_X1_X2);
X2: xor2 port map(a=>s_X1_X2, b=>cin, y=>s_X2_A1);
A1: and2 port map(a=>s_X2_A1, b=>opSomador, y=>s);
A2: and3 port map(a=>a, b=>b, c=>opSomador, y=>s_A2_O1);
A3: and3 port map(a=>a, b=>cin, c=>opSomador, y=>s_A3_O1);
A4: and3 port map(a=>b, b=>cin, c=>opSomador, y=>s_A4_O1);
O1: or3 port map(a=>s_A2_O1, b=>s_A3_O1, c=>s_A4_O1, y=>cout);
end estrutural;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_k3_k4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k4_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_k3_k4_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_k3_k4_rtl_conf / inst_k3_k4_e
--
configuration inst_k3_k4_rtl_conf of inst_k3_k4_e is
for rtl
-- Generated Configuration
end for;
end inst_k3_k4_rtl_conf;
--
-- End of Generated Configuration inst_k3_k4_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z' after 2 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
u0 : virtex_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j));
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z' after 2 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
u0 : virtex_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j));
end generate;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc990.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p07n02i00990ent IS
END c06s03b00x00p07n02i00990ent;
ARCHITECTURE c06s03b00x00p07n02i00990arch OF c06s03b00x00p07n02i00990ent IS
BEGIN
TESTING: PROCESS
function F return BOOLEAN is
begin
return TRUE;
end F;
variable B1 : BOOLEAN;
variable V1 : BOOLEAN;
BEGIN
V1 := F.B1; -- ERROR: the prefix of an expanded name
-- cannot be a function call.
assert FALSE
report "***FAILED TEST: c06s03b00x00p07n02i00990 - The prefix of an expanded name cannot be a function call.(Expanded name used as expression)"
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p07n02i00990arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc990.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p07n02i00990ent IS
END c06s03b00x00p07n02i00990ent;
ARCHITECTURE c06s03b00x00p07n02i00990arch OF c06s03b00x00p07n02i00990ent IS
BEGIN
TESTING: PROCESS
function F return BOOLEAN is
begin
return TRUE;
end F;
variable B1 : BOOLEAN;
variable V1 : BOOLEAN;
BEGIN
V1 := F.B1; -- ERROR: the prefix of an expanded name
-- cannot be a function call.
assert FALSE
report "***FAILED TEST: c06s03b00x00p07n02i00990 - The prefix of an expanded name cannot be a function call.(Expanded name used as expression)"
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p07n02i00990arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc990.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p07n02i00990ent IS
END c06s03b00x00p07n02i00990ent;
ARCHITECTURE c06s03b00x00p07n02i00990arch OF c06s03b00x00p07n02i00990ent IS
BEGIN
TESTING: PROCESS
function F return BOOLEAN is
begin
return TRUE;
end F;
variable B1 : BOOLEAN;
variable V1 : BOOLEAN;
BEGIN
V1 := F.B1; -- ERROR: the prefix of an expanded name
-- cannot be a function call.
assert FALSE
report "***FAILED TEST: c06s03b00x00p07n02i00990 - The prefix of an expanded name cannot be a function call.(Expanded name used as expression)"
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p07n02i00990arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon_dsu_stat_base
-- File: leon_dsu_stat_base.vhd
-- Author: Cobham Gaisler AB
-- Description: Entity that instantiates LEON3 and LEON4 together with the
-- corresponding debug support unit and performance counters.
--
-- Limitations:
--
-- Primarly targeted for FPGA designs and for designs without clock gating
-- since the same clock feeds all instantiated blocks.
--
-- Memory BIST signals are not propagated to the top-level
--
-- Scan test is disabled
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.leon4.all;
use gaisler.subsys.all;
entity leon_dsu_stat_base is
generic (
-- LEON selection
leon : integer range 0 to 4 := 0;
ncpu : integer range 1 to 16 := 1;
-- LEON configuration
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Use netlist
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0;
ahbpipe : integer := 0;
--
grfpush : integer range 0 to 1 := 0;
-- DSU
dsu_hindex : integer := 2;
dsu_haddr : integer := 16#900#;
dsu_hmask : integer := 16#F00#;
atbsz : integer := 4;
--
stat : integer range 0 to 1 := 0;
stat_pindex : integer := 0;
stat_paddr : integer := 0;
stat_pmask : integer := 16#ffc#;
stat_ncnt : integer := 1;
stat_nmax : integer := 0
--
);
port (
rstn : in std_ulogic;
--
ahbclk : in std_ulogic; -- bus clock
cpuclk : in std_ulogic; -- cpu clock
hclken : in std_ulogic; -- bus clock enable qualifier
--
leon_ahbmi : in ahb_mst_in_type;
leon_ahbmo : out ahb_mst_out_vector_type(ncpu-1 downto 0);
leon_ahbsi : in ahb_slv_in_type;
leon_ahbso : in ahb_slv_out_vector;
--
irqi : in irq_in_vector(0 to ncpu-1);
irqo : out irq_out_vector(0 to ncpu-1);
--
stat_apbi : in apb_slv_in_type;
stat_apbo : out apb_slv_out_type;
stat_ahbsi : in ahb_slv_in_type;
stati : in l3stat_in_type;
--
dsu_ahbsi : in ahb_slv_in_type;
dsu_ahbso : out ahb_slv_out_type;
dsu_tahbmi : in ahb_mst_in_type;
dsu_tahbsi : in ahb_slv_in_type;
--
sysi : in leon_dsu_stat_base_in_type;
syso : out leon_dsu_stat_base_out_type
);
end;
architecture rtl of leon_dsu_stat_base is
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal vcc : std_ulogic;
begin
vcc <= '1';
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if leon = 3 generate
leon3blk : block
signal l3dbgi : l3_debug_in_vector(0 to ncpu-1);
signal l3dbgo : l3_debug_out_vector(0 to ncpu-1);
signal l3dsui : dsu_in_type;
signal l3dsuo : dsu_out_type;
begin
cpu : for i in 0 to ncpu-1 generate
leon3 : leon3x -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu + 32*grfpush,
v8 => v8,
cp => 0,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => ncpu-1,
iuft => ft mod 4,
fpft => ft mod 4,
cmft => ft/8,
iuinj => 0, --iuinj,
ceinj => 0, --ceinj,
cached => cached,
clk2x => clk2x,
netlist => netlist,
scantest => 0,
mmupgsz => 0, -- 4 KiB
bp => 2, -- programmable
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin
)
port map (
clk => ahbclk,
gclk2 => cpuclk,
gfclk2 => cpuclk,
clk2 => cpuclk,
rstn => rstn,
ahbi => leon_ahbmi,
ahbo => leon_ahbmo(i),
ahbsi => leon_ahbsi,
ahbso => leon_ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => l3dbgi(i),
dbgo => l3dbgo(i),
fpui => fpi(i),
fpuo => fpo(i),
clken => hclken);
end generate cpu;
syso.proc_error <= l3dbgo(0).error;
syso.proc_errorn <= not l3dbgo(0).error;
-- LEON3 Debug Support Unit
dsugen : if dsu = 1 generate
dsu0 : dsu3x
generic map (
hindex => dsu_hindex,
haddr => dsu_haddr,
hmask => dsu_hmask,
ncpu => ncpu,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => atbsz,
clk2x => 0,
testen => 0,
bwidth => AHBDW,
ahbpf => 0)
port map (
rst => rstn,
hclk => ahbclk,
cpuclk => cpuclk,
ahbmi => dsu_tahbmi,
ahbsi => dsu_ahbsi,
ahbso => dsu_ahbso,
tahbsi => dsu_tahbsi,
dbgi => l3dbgo,
dbgo => l3dbgi,
dsui => l3dsui,
dsuo => l3dsuo,
hclken => hclken
);
l3dsui.enable <= sysi.dsu_enable;
l3dsui.break <= sysi.dsu_break;
syso.dsu_active <= l3dsuo.active;
syso.dsu_tstop <= l3dsuo.tstop;
end generate;
nodsugen : if dsu = 0 generate
l3dbgi <= (others => dbgi_none);
end generate;
l3sgen : if stat /= 0 generate
l3s : l3stat
generic map (
pindex => stat_pindex,
paddr => stat_paddr,
pmask => stat_pmask,
ncnt => stat_ncnt,
ncpu => ncpu,
nmax => stat_nmax,
lahben => 1,
dsuen => dsu,
forcer0 => 0)
port map (
rstn => rstn,
clk => ahbclk,
apbi => stat_apbi,
apbo => stat_apbo,
ahbsi => stat_ahbsi,
dbgo => l3dbgo,
dsuo => l3dsuo,
stati => stati,
apb2i => apb_slv_in_none,
apb2o => open,
astat => amba_stat_none);
end generate;
nol3s : if stat = 0 generate
stat_apbo <= apb_none;
end generate;
end block leon3blk;
end generate;
----------------------------------------------------------------------
--- LEON4 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l4 : if leon = 4 generate
leon4blk : block
signal l4dbgi : l4_debug_in_vector(0 to ncpu-1);
signal l4dbgo : l4_debug_out_vector(0 to ncpu-1);
signal l4dsui : dsu4_in_type;
signal l4dsuo : dsu4_out_type;
begin
cpu : for i in 0 to ncpu-1 generate
leon4 : leon4x -- LEON4 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu + 32*grfpush,
v8 => v8,
cp => 0,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
cached => cached,
clk2x => 0,
scantest => 0,
wbmask => wbmask,
busw => busw,
netlist => netlist,
ft => ft,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
ahbclk => ahbclk,
cpuclk => cpuclk,
gcpuclk => cpuclk,
fpuclk => cpuclk,
hclken => hclken,
rstn => rstn,
ahbi => leon_ahbmi,
ahbo => leon_ahbmo(i),
ahbsi => leon_ahbsi,
ahbso => leon_ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => l4dbgi(i),
dbgo => l4dbgo(i),
fpui => fpi(i),
fpuo => fpo(i)
);
end generate cpu;
syso.proc_error <= l4dbgo(0).error;
syso.proc_errorn <= not l4dbgo(0).error;
-- LEON4 Debug Support Unit
dsugen : if dsu = 1 generate
dsu0 : dsu4x
generic map (
hindex => dsu_hindex,
haddr => dsu_haddr,
hmask => dsu_hmask,
ncpu => ncpu,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => atbsz,
clk2x => 0, -- fixme
bwidth => AHBDW,
ahbpf => 0, -- fixme
ahbwp => 0, -- fixme
scantest => 0,
pipedbg => 0,
pipeahbt => 0)
port map (
rst => rstn,
hclk => ahbclk,
cpuclk => cpuclk,
fcpuclk => cpuclk,
ahbmi => dsu_tahbmi,
ahbsi => dsu_ahbsi,
ahbso => dsu_ahbso,
tahbsi => dsu_tahbsi,
dbgi => l4dbgo,
dbgo => l4dbgi,
dsui => l4dsui,
dsuo => l4dsuo,
hclken => hclken
);
l4dsui.enable <= sysi.dsu_enable;
l4dsui.break <= sysi.dsu_break;
syso.dsu_active <= l4dsuo.active;
syso.dsu_tstop <= l4dsuo.tstop;
end generate;
nodsugen : if dsu = 0 generate
l4dbgi <= (others => l4_dbgi_none);
end generate;
l4sgen : if stat /= 0 generate
l4s : l4stat
generic map (
pindex => stat_pindex,
paddr => stat_paddr,
pmask => stat_pmask,
ncnt => stat_ncnt,
ncpu => ncpu,
nmax => stat_nmax,
lahben => 0,
dsuen => dsu,
nextev => 7)
port map (
rstn => rstn,
clk => ahbclk,
apbi => stat_apbi,
apbo => stat_apbo,
ahbsi => stat_ahbsi,
dbgo => l4dbgo,
dsuo => l4dsuo,
stati => stati,
apb2i => apb_slv_in_none,
apb2o => open,
astat => amba_stat_none);
end generate;
nol4s : if stat = 0 generate
stat_apbo <= apb_none;
end generate;
end block leon4blk;
end generate;
nodsu : if dsu = 0 generate
syso.dsu_tstop <= '0'; syso.dsu_active <= '0';
dsu_ahbso <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- Optional shared FPU -----------------------------------------
----------------------------------------------------------------------
shfpu : if grfpush = 1 generate
grfpush0 : grfpushwx generic map ((fpu-1), ncpu, fabtech)
port map (cpuclk, rstn, fpi, fpo);
end generate;
noshfpu : if grfpush = 0 generate
fpo <= (others => grfpu_out_none);
end generate;
end;
|
-- comparator calculate state with minimum path metric from final path metric sum
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(A,B : in std_logic_vector(2 downto 0);
CODE_A, CODE_B : in std_logic_vector(1 downto 0);
CMP : out std_logic_vector(2 downto 0);
CODE_OUT : out std_logic_vector(1 downto 0));
end comparator ;
architecture COMPARCH of comparator is
begin
CMP <= A when A <= B else B;
CODE_OUT <= CODE_A when A<=B else CODE_B;
end COMPARCH;
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator2 is
port(A,B : in std_logic_vector(2 downto 0);
CODE_A, CODE_B : in std_logic_vector(1 downto 0);
CODE_OUT : out std_logic_vector(1 downto 0));
end comparator2 ;
architecture COMPARCH of comparator2 is
begin
CODE_OUT <= CODE_A when A<=B else CODE_B;
end COMPARCH;
-------------------------------------------------
--------------------------------------------------------
------------------- Original comparator ----------------
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY COMPAR1 IS
PORT(A,B,C,D:in std_logic_vector(2 downto 0);
CODE : out std_logic_vector(1 downto 0));
END ENTITY;
-----------------------------------------------------
architecture COMPAR1_ARCH OF COMPAR1 IS
signal ab,cd : std_logic_vector(2 downto 0);
signal code_ab,code_cd : std_logic_vector(1 downto 0);
COMPONENT comparator is
port(A,B : in std_logic_vector(2 downto 0);
CODE_A, CODE_B : in std_logic_vector(1 downto 0);
CMP : out std_logic_vector(2 downto 0);
CODE_OUT : out std_logic_vector(1 downto 0));
end component ;
COMPONENT comparator2 is
port(A,B : in std_logic_vector(2 downto 0);
CODE_A, CODE_B : in std_logic_vector(1 downto 0);
CODE_OUT : out std_logic_vector(1 downto 0));
end COMPONENT ;
BEGIN
C1: comparator port map (A,B,"00","01",AB,CODE_AB);
C2: comparator port map (C,D,"10","11",CD,CODE_CD);
C3: comparator2 port map (AB,CD,CODE_AB,CODE_CD,CODE);
END;
|
use work.graphics_types_pkg.all;
package npc_pkg is
constant NPC_SPEED_MAX: integer := 12;
type npc_ai_type is (AI_BOUNCER, AI_FOLLOWER, AI_PROJECTILE);
type npc_type is record
-- start position for the NPC
initial_position: point_type;
-- start velocity for the NPC
initial_speed: point_type;
absolute_speed: integer range 0 to NPC_SPEED_MAX;
slowdown_factor: integer range 0 to NPC_SPEED_MAX;
-- boundaries for NPC movement
allowed_region: rectangle_type;
-- type of artificial intelligence for NPC movement
ai_type: npc_ai_type;
end record;
type npc_array_type is array (natural range <>) of npc_type;
function make_npc_bouncer(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type;
function make_npc_projectile(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type;
function make_npc_follower(
initial_position: point_type := (0, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1);
absolute_speed: integer range 0 to NPC_SPEED_MAX := 1;
slowdown_factor: integer range 0 to NPC_SPEED_MAX := 0
) return npc_type;
end;
package body npc_pkg is
function make_npc_bouncer(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
initial_speed => initial_speed,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_BOUNCER,
-- remaining parameters are unsused, but must have any arbitrary value
absolute_speed => 0,
slowdown_factor => 0
);
end;
function make_npc_projectile(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
initial_speed => initial_speed,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_PROJECTILE,
-- remaining parameters are unsused, but must have any arbitrary value
absolute_speed => 0,
slowdown_factor => 0
);
end;
function make_npc_follower(
initial_position: point_type := (0, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1);
absolute_speed: integer range 0 to NPC_SPEED_MAX := 1;
slowdown_factor: integer range 0 to NPC_SPEED_MAX := 0
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
absolute_speed => absolute_speed,
slowdown_factor => slowdown_factor,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_FOLLOWER,
-- remaining parameters are unsused, but must have any arbitrary value
initial_speed => (0, 0)
);
end;
end;
|
--
|
----------------------------------------------------------------------------------
-- Company: University of Genova
-- Engineer: Alessio Leoncini, Alberto Oliveri
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosAlAl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosAlAl is
generic (nbit : integer := 32);
Port ( ck : in STD_LOGIC;
res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosAlAl;
architecture Behavioral of CaosAlAl is
signal reg : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := "00000000000000000000000000000000";
constant one : signed(nbit-1 downto 0) := "01000000000000000000000000000000";
constant minusone : signed(nbit-1 downto 0) := "11000000000000000000000000000000";
constant x0 : signed(nbit-1 downto 0) := "00100000000000000000000000000000";
begin
out0 <= reg(nbit-1);
main:process(ck,res)
begin
if res = '0' then
if (ck'event and ck ='1') then
if (reg < zero) then
reg <= (( reg(nbit-2 downto 0) & '0' ) - ( "111" & reg(nbit-1 downto 3) )) + one;
else
reg <= (( reg(nbit-2 downto 0)&'0' ) - ( "000" & reg(nbit-1 downto 3) )) + minusone;
end if;
end if;
else
-- init
reg <= x0;
end if;
end process;
end Behavioral; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: VHDL package for component declarations, types and
-- functions associated to the PoC.comm namespace
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
package comm is
-- Calculates the Remainder of the Division by the Generator Polynomial GEN.
component comm_crc is
generic (
GEN : bit_vector; -- Generator Polynom
BITS : positive -- Number of Bits to be processed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(GEN'length-2 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end component;
-- Computes XOR masks for stream scrambling from an LFSR generator.
component comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0) --
);
end component;
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Module: VHDL package for component declarations, types and
-- functions associated to the PoC.comm namespace
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
package comm is
-- Calculates the Remainder of the Division by the Generator Polynomial GEN.
component comm_crc is
generic (
GEN : bit_vector; -- Generator Polynom
BITS : positive -- Number of Bits to be processed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(GEN'length-2 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end component;
-- Computes XOR masks for stream scrambling from an LFSR generator.
component comm_scramble is
generic (
GEN : bit_vector; -- Generator Polynomial (little endian)
BITS : positive -- Width of Mask Bits to be computed in parallel
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Set LFSR to provided Value
din : in std_logic_vector(GEN'length-2 downto 0); --
step : in std_logic; -- Compute a Mask Output
mask : out std_logic_vector(BITS-1 downto 0) --
);
end component;
end package;
|
-- $Id: rlink_rlbmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_rlbmux - syn
-- Description: rlink rlb multiplexer
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
entity rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end rlink_rlbmux;
architecture syn of rlink_rlbmux is
begin
proc_rlmux : process (SEL, RLB_DO, RLB_VAL, RLB_BUSY,
P0_RXDATA, P0_RXVAL, P0_TXBUSY,
P1_RXDATA, P1_RXVAL, P1_TXBUSY)
begin
P0_TXDATA <= RLB_DO;
P1_TXDATA <= RLB_DO;
if SEL = '0' then
RLB_DI <= P0_RXDATA;
RLB_ENA <= P0_RXVAL;
P0_RXHOLD <= RLB_BUSY;
P0_TXENA <= RLB_VAL;
RLB_HOLD <= P0_TXBUSY;
P1_RXHOLD <= '0';
P1_TXENA <= '0';
else
RLB_DI <= P1_RXDATA;
RLB_ENA <= P1_RXVAL;
P1_RXHOLD <= RLB_BUSY;
P1_TXENA <= RLB_VAL;
RLB_HOLD <= P1_TXBUSY;
P0_RXHOLD <= '0';
P0_TXENA <= '0';
end if;
end process proc_rlmux;
end syn;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: udp_tx_packet - Behavioral
--
-- Description: Construct and send out UDP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port( clk : in STD_LOGIC;
udp_tx_busy : out std_logic := '0';
udp_tx_valid : in std_logic;
udp_tx_data : in std_logic_vector(7 downto 0);
udp_tx_src_port : in std_logic_vector(15 downto 0);
udp_tx_dst_mac : in std_logic_vector(47 downto 0);
udp_tx_dst_ip : in std_logic_vector(31 downto 0);
udp_tx_dst_port : in std_logic_vector(15 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end udp_tx_packet;
architecture Behavioral of udp_tx_packet is
signal busy_countdown : unsigned(7 downto 0) := (others => '0');
-- For holding the destination and port details on the first data transfer
signal udp_tx_valid_last : STD_LOGIC := '0';
signal tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_length : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal pre_udp_valid : STD_LOGIC := '0';
signal pre_udp_data : STD_LOGIC_VECTOR (7 downto 0);
component buffer_count_and_checksum_data is
generic (min_length : natural);
Port ( clk : in STD_LOGIC;
hdr_valid_in : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0);
data_checksum : out std_logic_vector(15 downto 0));
end component;
signal data_length : std_logic_vector(15 downto 0);
signal data_checksum : std_logic_vector(15 downto 0);
component udp_add_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0);
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0);
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0);
udp_src_port : in std_logic_vector(15 downto 0);
udp_dst_port : in std_logic_vector(15 downto 0));
end component;
signal pre_ip_valid : STD_LOGIC := '0';
signal pre_ip_data : STD_LOGIC_VECTOR (7 downto 0);
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_data_length : std_logic_vector(15 downto 0);
component ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end component;
signal pre_header_valid : STD_LOGIC := '0';
signal pre_header_data : STD_LOGIC_VECTOR (7 downto 0);
component ethernet_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_type : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ether_dst_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal complete_valid : STD_LOGIC := '0';
signal complete_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component transport_commit_buffer
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
begin
process(clk)
begin
if rising_edge(clk) then
-- Capture the destination address data on the first cycle of the data packet
if udp_tx_valid = '1' then
if udp_tx_valid_last = '0' then
tx_src_port <= udp_tx_src_port;
tx_dst_mac <= udp_tx_dst_mac;
tx_dst_ip <= udp_tx_dst_ip;
tx_dst_port <= udp_tx_dst_port;
busy_countdown <= to_unsigned(8+64+12-4,8);
-- 8 = preamble
-- 64 = minimum ethernet header
-- 12 = minimum inter-packet gap
-- and -4 is a fix for latency
udp_tx_busy <= '1';
else
-- Allow for the bytes that will be added
if busy_countdown > 8+14+20+8+4+12 -3 then
-- allow for premable (8)
-- and ethernet Header(14)
-- and ip header (20)
-- and udp hereader (8)
-- and ethernet FCS (4)
-- and minimum inter-packet gap
-- and -3 is a fix for latency
busy_countdown <= busy_countdown-1;
end if;
end if;
else
-- Keep udp_tx_busy asserted to allow for
-- everything to be wrapped around the data
if busy_countdown > 0 then
busy_countdown <= busy_countdown - 1;
else
udp_tx_busy <= '0';
end if;
end if;
udp_tx_valid_last <= udp_tx_valid;
end if;
end process;
i_buffer_count_and_checksum_data: buffer_count_and_checksum_data generic map (
min_length => 64-14-20-8)
port map (
clk => clk,
hdr_valid_in => '0',
data_valid_in => udp_tx_valid,
data_in => udp_tx_data,
data_valid_out => pre_udp_valid,
data_out => pre_udp_data,
data_length => data_length,
data_checksum => data_checksum);
i_udp_add_udp_header: udp_add_udp_header port map (
clk => clk,
data_valid_in => pre_udp_valid,
data_in => pre_udp_data,
data_valid_out => pre_ip_valid,
data_out => pre_ip_data,
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip,
data_length => data_length,
data_checksum => data_checksum,
udp_src_port => tx_src_port,
udp_dst_port => tx_dst_port);
ip_data_length <= std_logic_vector(unsigned(data_length)+8);
i_ip_add_header: ip_add_header port map (
clk => clk,
data_valid_in => pre_ip_valid,
data_in => pre_ip_data,
data_valid_out => pre_header_valid,
data_out => pre_header_data,
ip_data_length => ip_data_length,
ip_protocol => x"11",
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip);
i_ethernet_add_header: ethernet_add_header port map (
clk => clk,
data_valid_in => pre_header_valid,
data_in => pre_header_data,
data_valid_out => complete_valid,
data_out => complete_data,
ether_type => x"0800",
ether_dst_mac => tx_dst_mac,
ether_src_mac => our_mac);
i_transport_commit_buffer: transport_commit_buffer port map (
clk => clk,
data_valid_in => complete_valid,
data_in => complete_data,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IpinReg is
end IpinReg;
architecture Behavioral of IpinReg is
begin
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IpinReg is
end IpinReg;
architecture Behavioral of IpinReg is
begin
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IpinReg is
end IpinReg;
architecture Behavioral of IpinReg is
begin
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library unisim;
use UNISIM.VComponents.all;
entity user_logic is
generic
(
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 8;
C_NUM_LUTS : integer := 1024
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute keep_hierarchy : string;
attribute keep_hierarchy of user_logic : entity is "true";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 7);
signal slv_reg_read_sel : std_logic_vector(0 to 7);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal offset : integer;
constant C_MAX_OFFSET : integer := C_NUM_LUTS - 31;
component lut_oscilator is
Port ( en : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal inout_bit : std_logic;
signal inout_vector : std_logic_vector (C_NUM_LUTS downto 0) := (others=>'0');
signal and_value : std_logic;
signal direction : std_logic_vector(32 downto 0) := (others => '0');
attribute keep : string;
attribute keep of inout_vector : signal is "true";
attribute keep of IMP : architecture is "true";
signal adjust : std_logic_vector (31 downto 0);
signal adjust_heaters : std_logic_vector (31 downto 0) := (others => '0');
constant block_items : integer := C_NUM_LUTS / 32;
signal enable_heater : std_logic;
signal enable_vector : std_logic_vector (C_NUM_LUTS - 1 downto 0);
signal j : integer := 0;
signal enabled_count : integer := 0;
signal temp : std_logic_vector (5 downto 0);
signal enable_count : std_logic_vector (31 downto 0);
signal int_adjust : integer := 0;
signal adjust_temp : integer;
begin
adjust_heaters <= slv_reg1;
init_proc : process( adjust_heaters, enable_heater ) is
begin
for i in 0 to 31 loop
for j in 0 to block_items - 1 loop
enable_vector(block_items * i + j) <= adjust_heaters(i) and enable_heater;
end loop;
end loop;
end process init_proc;
enable : process ( slv_reg0 ) is
begin
if slv_reg0 = 1 then
enable_heater <= '1';
else
enable_heater <= '0';
end if;
end process enable;
luts : for bit_index in 0 to C_NUM_LUTS - 1 generate
begin
lut_osc : lut_oscilator
port map ( en => enable_vector(bit_index),
Q => inout_vector(bit_index));
end generate luts;
slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 7);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
if slv_reg2 = 0 then
adjust_heaters <= adjust_heaters(30 downto 0) & '0';
elsif slv_reg2 = 1 then
adjust_heaters <= '1' & adjust_heaters(31 downto 1);
end if;
when "00100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
offset <= conv_integer(slv_reg3);
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= "0000000000000000000000000000000" & enable_heater;
when "01000000" => slv_ip2bus_data <= adjust_heaters;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= inout_vector(C_NUM_LUTS - offset - 1 downto C_NUM_LUTS - offset - 32);
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET Apr-25-01 -- First version
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ip2bus_srmux is
port (
-- Status Reply inputs from the IP
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Write FIFO
WFIFO_WrAck : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the Read FIFO
RFIFO_WrAck : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_Error : in std_logic;
RFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the DMA/SG engine
DMA2Bus_WrAck : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_Error : in std_logic;
DMA2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Interrupt Collector
IRPT_WrAck : in std_logic;
IRPT_RdAck : in std_logic;
IRPT_Retry : in std_logic;
IRPT_Error : in std_logic;
IRPT_ToutSup : in std_logic;
-- Status reply from the Reset block
RESET_WrAck : In std_logic;
RESET_RdAck : in std_logic;
RESET_Retry : in std_logic;
RESET_Error : in std_logic;
RESET_ToutSup : in std_logic;
-- Status Reply outputs to the Slave Attachment
IP2Bus_WrAck_mx : out std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_ToutSup_mx : out std_logic
);
end ip2bus_srmux;
architecture implementation of ip2bus_srmux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
-- The following code is for a simple 'OR' function of the input signals
-- to generate a single output. This method works in place of a multiplexer
-- since by definition inactive signals are driven to a logic '0'.
-- Combinational logic
IP2Bus_WrAck_mx <= IP2Bus_WrAck or
WFIFO_WrAck or
RFIFO_WrAck or
DMA2Bus_WrAck or
IRPT_WrAck or
RESET_WrAck;
IP2Bus_RdAck_mx <= IP2Bus_RdAck or
WFIFO_RdAck or
RFIFO_RdAck or
DMA2Bus_RdAck or
IRPT_RdAck or
RESET_RdAck;
IP2Bus_Retry_mx <= IP2Bus_Retry or
WFIFO_Retry or
RFIFO_Retry or
DMA2Bus_Retry or
IRPT_Retry or
RESET_Retry;
IP2Bus_Error_mx <= IP2Bus_Error or
WFIFO_Error or
RFIFO_Error or
DMA2Bus_Error or
IRPT_Error or
RESET_Error;
IP2Bus_ToutSup_mx <= IP2Bus_ToutSup or
WFIFO_ToutSup or
RFIFO_ToutSup or
DMA2Bus_ToutSup or
IRPT_ToutSup or
RESET_ToutSup;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET Apr-25-01 -- First version
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ip2bus_srmux is
port (
-- Status Reply inputs from the IP
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Write FIFO
WFIFO_WrAck : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the Read FIFO
RFIFO_WrAck : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_Error : in std_logic;
RFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the DMA/SG engine
DMA2Bus_WrAck : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_Error : in std_logic;
DMA2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Interrupt Collector
IRPT_WrAck : in std_logic;
IRPT_RdAck : in std_logic;
IRPT_Retry : in std_logic;
IRPT_Error : in std_logic;
IRPT_ToutSup : in std_logic;
-- Status reply from the Reset block
RESET_WrAck : In std_logic;
RESET_RdAck : in std_logic;
RESET_Retry : in std_logic;
RESET_Error : in std_logic;
RESET_ToutSup : in std_logic;
-- Status Reply outputs to the Slave Attachment
IP2Bus_WrAck_mx : out std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_ToutSup_mx : out std_logic
);
end ip2bus_srmux;
architecture implementation of ip2bus_srmux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
-- The following code is for a simple 'OR' function of the input signals
-- to generate a single output. This method works in place of a multiplexer
-- since by definition inactive signals are driven to a logic '0'.
-- Combinational logic
IP2Bus_WrAck_mx <= IP2Bus_WrAck or
WFIFO_WrAck or
RFIFO_WrAck or
DMA2Bus_WrAck or
IRPT_WrAck or
RESET_WrAck;
IP2Bus_RdAck_mx <= IP2Bus_RdAck or
WFIFO_RdAck or
RFIFO_RdAck or
DMA2Bus_RdAck or
IRPT_RdAck or
RESET_RdAck;
IP2Bus_Retry_mx <= IP2Bus_Retry or
WFIFO_Retry or
RFIFO_Retry or
DMA2Bus_Retry or
IRPT_Retry or
RESET_Retry;
IP2Bus_Error_mx <= IP2Bus_Error or
WFIFO_Error or
RFIFO_Error or
DMA2Bus_Error or
IRPT_Error or
RESET_Error;
IP2Bus_ToutSup_mx <= IP2Bus_ToutSup or
WFIFO_ToutSup or
RFIFO_ToutSup or
DMA2Bus_ToutSup or
IRPT_ToutSup or
RESET_ToutSup;
end implementation;
|
-----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2008 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal clk_125_p : std_ulogic := '0';
signal clk_125_n : std_ulogic := '1';
constant slips : integer := 11;
signal rst_125 : std_ulogic;
signal sysace_fpga_clk : std_ulogic := '0';
signal flash_we_b : std_ulogic;
signal flash_wait : std_ulogic;
signal flash_reset_b : std_ulogic;
signal flash_oe_b : std_ulogic;
signal flash_d : std_logic_vector(15 downto 0);
signal flash_clk : std_ulogic;
signal flash_ce_b : std_ulogic;
signal flash_adv_b : std_logic;
signal flash_a : std_logic_vector(21 downto 0);
signal sram_bw : std_ulogic;
signal sim_d : std_logic_vector(15 downto 0);
signal iosn : std_ulogic;
signal dimm1_ddr2_we_b : std_ulogic;
signal dimm1_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm1_ddr2_ras_b : std_ulogic;
signal dimm1_ddr2_pll_clkin_p : std_ulogic;
signal dimm1_ddr2_pll_clkin_n : std_ulogic;
signal dimm1_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm1_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm1_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm1_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm1_ddr2_cas_b : std_ulogic;
signal dimm1_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm1_ddr2_a : std_logic_vector(13 downto 0);
signal dimm0_ddr2_we_b : std_ulogic;
signal dimm0_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm0_ddr2_ras_b : std_ulogic;
signal dimm0_ddr2_pll_clkin_p : std_ulogic;
signal dimm0_ddr2_pll_clkin_n : std_ulogic;
signal dimm0_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm0_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm0_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm0_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm0_ddr2_cas_b : std_ulogic;
signal dimm0_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm0_ddr2_a : std_logic_vector(13 downto 0);
signal phy0_txer : std_ulogic;
signal phy0_txd : std_logic_vector(3 downto 0);
signal phy0_txctl_txen : std_ulogic;
signal phy0_txclk : std_ulogic;
signal phy0_rxer : std_ulogic;
signal phy0_rxd : std_logic_vector(3 downto 0);
signal phy0_rxctl_rxdv : std_ulogic;
signal phy0_rxclk : std_ulogic;
signal phy0_reset : std_ulogic;
signal phy0_mdio : std_logic;
signal phy0_mdc : std_ulogic;
signal phy1_reset : std_logic;
signal phy1_mdio : std_logic;
signal phy1_mdc : std_logic;
signal phy1_sgmii_tx_p : std_logic;
signal phy1_sgmii_tx_n : std_logic;
signal phy1_sgmii_rx_p : std_logic;
signal phy1_sgmii_rx_n : std_logic;
signal phy1_sgmii_rx_p_d : std_logic;
signal phy1_sgmii_rx_n_d : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_mpd : std_logic_vector(15 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
signal opb_bus_error : std_ulogic;
signal plb_bus_error : std_ulogic;
signal dvi_xclk_p : std_ulogic;
signal dvi_xclk_n : std_ulogic;
signal dvi_v : std_ulogic;
signal dvi_reset_b : std_ulogic;
signal dvi_h : std_ulogic;
signal dvi_gpio1 : std_logic;
signal dvi_de : std_ulogic;
signal dvi_d : std_logic_vector(11 downto 0);
signal pci_p_trdy_b : std_logic;
signal pci_p_stop_b : std_logic;
signal pci_p_serr_b : std_logic;
signal pci_p_rst_b : std_logic;
signal pci_p_req_b : std_logic_vector(0 to 4);
signal pci_p_perr_b : std_logic;
signal pci_p_par : std_logic;
signal pci_p_lock_b : std_logic;
signal pci_p_irdy_b : std_logic;
signal pci_p_intd_b : std_logic;
signal pci_p_intc_b : std_logic;
signal pci_p_intb_b : std_logic;
signal pci_p_inta_b : std_logic;
signal pci_p_gnt_b : std_logic_vector(0 to 4);
signal pci_p_frame_b : std_logic;
signal pci_p_devsel_b : std_logic;
signal pci_p_clk5_r : std_ulogic;
signal pci_p_clk5 : std_ulogic;
signal pci_p_clk4_r : std_ulogic;
signal pci_p_clk3_r : std_ulogic;
signal pci_p_clk1_r : std_ulogic;
signal pci_p_clk0_r : std_ulogic;
signal pci_p_cbe_b : std_logic_vector(3 downto 0);
signal pci_p_ad : std_logic_vector(31 downto 0);
--signal pci_fpga_idsel : std_ulogic;
signal sbr_pwg_rsm_rstj : std_logic;
signal sbr_nmi_r : std_ulogic;
signal sbr_intr_r : std_ulogic;
signal sbr_ide_rst_b : std_logic;
signal iic_sda_dvi : std_logic;
signal iic_scl_dvi : std_logic;
signal fpga_sda : std_logic;
signal fpga_scl : std_logic;
signal iic_therm_b : std_ulogic;
signal iic_reset_b : std_ulogic;
signal iic_irq_b : std_ulogic;
signal iic_alert_b : std_ulogic;
signal spi_data_out : std_logic;
signal spi_data_in : std_logic;
signal spi_data_cs_b : std_ulogic;
signal spi_clk : std_ulogic;
signal uart1_txd : std_ulogic;
signal uart1_rxd : std_ulogic;
signal uart1_rts_b : std_ulogic;
signal uart1_cts_b : std_ulogic;
signal uart0_txd : std_ulogic;
signal uart0_rxd : std_ulogic;
signal uart0_rts_b : std_ulogic;
--signal uart0_cts_b : std_ulogic;
--signal test_mon_vrefp : std_ulogic;
signal test_mon_vp0_p : std_ulogic;
signal test_mon_vn0_n : std_ulogic;
--signal test_mon_avdd : std_ulogic;
signal data : std_logic_vector(31 downto 0);
signal phy0_rxdl : std_logic_vector(7 downto 0);
signal phy0_txdl : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_fpga_clk <= not sysace_fpga_clk after 15 ns;
pci_p_clk5 <= pci_p_clk5_r;
clk_125_p <= not clk_125_p after 4 ns;
clk_125_n <= not clk_125_n after 4 ns;
flash_wait <= 'L';
phy0_txdl <= "0000" & phy0_txd; phy0_rxd <= phy0_rxdl(3 downto 0);
sysace_mpd <= (others => 'H'); sysace_mpirq <= 'L';
dbg_led <= (others => 'H');
dvi_gpio1 <= 'H';
pci_p_trdy_b <= 'H'; pci_p_stop_b <= 'H';
pci_p_serr_b <= 'H'; pci_p_rst_b <= 'H';
pci_p_req_b <= (others => 'H'); pci_p_perr_b <= 'H';
pci_p_par <= 'H'; pci_p_lock_b <= 'H';
pci_p_irdy_b <= 'H'; pci_p_intd_b <= 'H';
pci_p_intc_b <= 'H'; pci_p_intb_b <= 'H';
pci_p_inta_b <= 'H'; pci_p_gnt_b <= (others => 'H');
pci_p_frame_b <= 'H'; pci_p_devsel_b <= 'H';
pci_p_cbe_b <= (others => 'H'); pci_p_ad <= (others => 'H');
-- pci_fpga_idsel <= 'H';
sbr_pwg_rsm_rstj <= 'H'; sbr_nmi_r <= 'H';
sbr_intr_r <= 'L'; sbr_ide_rst_b <= 'H';
iic_sda_dvi <= 'H'; iic_scl_dvi <= 'H';
fpga_sda <= 'H'; fpga_scl <= 'H';
iic_therm_b <= 'L'; iic_irq_b <= 'L'; iic_alert_b <= 'L';
spi_data_out <= 'H';
uart1_rxd <= 'H'; uart1_cts_b <= uart1_rts_b;
uart0_rxd <= 'H'; --uart0_cts_b <= uart0_rts_b;
test_mon_vp0_p <= 'H'; test_mon_vn0_n <= 'H';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, transtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, sysace_fpga_clk,
-- Flash
flash_we_b, flash_wait, flash_reset_b, flash_oe_b,
flash_d, flash_clk, flash_ce_b, flash_adv_b, flash_a,
sram_bw, sim_d, iosn,
-- DDR2 slot 1
dimm1_ddr2_we_b, dimm1_ddr2_s_b, dimm1_ddr2_ras_b,
dimm1_ddr2_pll_clkin_p, dimm1_ddr2_pll_clkin_n,
dimm1_ddr2_odt, dimm1_ddr2_dqs_p, dimm1_ddr2_dqs_n,
dimm1_ddr2_dqm, dimm1_ddr2_dq, dimm1_ddr2_cke,
dimm1_ddr2_cas_b, dimm1_ddr2_ba, dimm1_ddr2_a,
-- DDR2 slot 0
dimm0_ddr2_we_b, dimm0_ddr2_s_b, dimm0_ddr2_ras_b,
dimm0_ddr2_pll_clkin_p, dimm0_ddr2_pll_clkin_n,
dimm0_ddr2_odt, dimm0_ddr2_dqs_p, dimm0_ddr2_dqs_n,
dimm0_ddr2_dqm, dimm0_ddr2_dq, dimm0_ddr2_cke,
dimm0_ddr2_cas_b, dimm0_ddr2_ba, dimm0_ddr2_a,
open,
-- Ethernet PHY0
phy0_txer, phy0_txd, phy0_txctl_txen, phy0_txclk,
phy0_rxer, phy0_rxd, phy0_rxctl_rxdv, phy0_rxclk,
phy0_reset, phy0_mdio, phy0_mdc,
-- Ethernet PHY1
clk_125_p, clk_125_n,
phy1_reset, phy1_mdio, phy1_mdc, open,
phy1_sgmii_tx_p, phy1_sgmii_tx_n, phy1_sgmii_rx_p, phy1_sgmii_rx_n,
-- System ACE MPU
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_mpd,
-- GPIO/Green LEDs
dbg_led,
-- Red/Green LEDs
opb_bus_error, plb_bus_error,
-- LCD
-- fpga_lcd_rw, fpga_lcd_rs, fpga_lcd_e, fpga_lcd_db,
-- DVI
dvi_xclk_p, dvi_xclk_n, dvi_v, dvi_reset_b, dvi_h,
dvi_gpio1, dvi_de, dvi_d,
-- PCI
pci_p_trdy_b, pci_p_stop_b, pci_p_serr_b, pci_p_rst_b,
pci_p_req_b, pci_p_perr_b, pci_p_par, pci_p_lock_b,
pci_p_irdy_b, pci_p_intd_b, pci_p_intc_b, pci_p_intb_b,
pci_p_inta_b, pci_p_gnt_b, pci_p_frame_b, pci_p_devsel_b,
pci_p_clk5_r, pci_p_clk5, pci_p_clk4_r, pci_p_clk3_r,
pci_p_clk1_r, pci_p_clk0_r, pci_p_cbe_b, pci_p_ad,
-- pci_fpga_idsel,
sbr_pwg_rsm_rstj, sbr_nmi_r, sbr_intr_r, sbr_ide_rst_b,
-- IIC/SMBus and sideband signals
iic_sda_dvi, iic_scl_dvi, fpga_sda, fpga_scl, iic_therm_b,
iic_reset_b, iic_irq_b, iic_alert_b,
-- SPI
spi_data_out, spi_data_in, spi_data_cs_b, spi_clk,
-- UARTs
uart1_txd, uart1_rxd, uart1_rts_b, uart1_cts_b,
uart0_txd, uart0_rxd, uart0_rts_b--, --uart0_cts_b
-- System monitor
-- test_mon_vp0_p, test_mon_vn0_n
);
-- ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b,
-- RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0),
-- BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0),
-- CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p,
-- CLKB => dimm0_ddr2_pll_clkin_n,
-- UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem0 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 14, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm0_ddr2_pll_clkin_p, ckn => dimm0_ddr2_pll_clkin_n,
cke => dimm0_ddr2_cke(0), csn => dimm0_ddr2_s_b(0),
odt => gnd, rasn => dimm0_ddr2_ras_b,
casn => dimm0_ddr2_cas_b, wen => dimm0_ddr2_we_b,
dm => dimm0_ddr2_dqm(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), ba => dimm0_ddr2_ba,
a => dimm0_ddr2_a, dq => dimm0_ddr2_dq2(63 downto 64-CFG_DDR2SP_DATAWIDTH),
dqs => dimm0_ddr2_dqs_p(7 downto 8-CFG_DDR2SP_DATAWIDTH/8),
dqsn =>dimm0_ddr2_dqs_n(7 downto 8-CFG_DDR2SP_DATAWIDTH/8));
-- ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b,
-- RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0),
-- BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0),
-- CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p,
-- CLKB => dimm1_ddr2_pll_clkin_n,
-- UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem1 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm1_ddr2_pll_clkin_p, ckn => dimm1_ddr2_pll_clkin_n,
cke => dimm1_ddr2_cke(0), csn => dimm1_ddr2_s_b(0),
odt => gnd, rasn => dimm1_ddr2_ras_b,
casn => dimm1_ddr2_cas_b, wen => dimm1_ddr2_we_b,
dm => dimm1_ddr2_dqm(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), ba => dimm1_ddr2_ba(1 downto 0),
a => dimm1_ddr2_a(12 downto 0), dq => dimm1_ddr2_dq2(CFG_DDR2SP_DATAWIDTH-1 downto 0),
dqs => dimm1_ddr2_dqs_p(CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dqsn =>dimm1_ddr2_dqs_n(CFG_DDR2SP_DATAWIDTH/8-1 downto 0));
ddr2delay0 : delay_wire
generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2);
ddr2delay1 : delay_wire
generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (flash_a(romdepth-1 downto 0), flash_d(15 downto 0),
gnd, gnd, flash_ce_b, flash_we_b, flash_oe_b);
phy0_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(phy0_reset, phy0_mdio, phy0_txclk, phy0_rxclk, phy0_rxdl,
phy0_rxctl_rxdv, phy0_rxer, open, open, phy0_txdl,
phy0_txctl_txen, phy0_txer, phy0_mdc, '0');
rst_125 <= not phy1_reset;
phy1_sgmii_rx_p <= transport phy1_sgmii_rx_p_d after 0.8 ns * slips;
phy1_sgmii_rx_n <= transport phy1_sgmii_rx_n_d after 0.8 ns * slips;
sp0: ser_phy
generic map(
address => 7,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
transtech => CFG_TRANSTECH
)
port map(
rstn => phy1_reset,
clk_125 => clk_125_p,
rst_125 => rst_125,
eth_rx_p => phy1_sgmii_rx_p_d,
eth_rx_n => phy1_sgmii_rx_n_d,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
mdio => phy1_mdio,
mdc => phy1_mdc
);
i0: i2c_slave_model
port map (iic_scl_dvi, iic_sda_dvi);
i1: i2c_slave_model
port map (fpga_scl, fpga_sda);
iuerr : process
begin
wait for 5000 ns;
if to_x01(opb_bus_error) = '0' then wait on opb_bus_error; end if;
assert (to_x01(opb_bus_error) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= flash_d & sim_d;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, opb_bus_error, flash_a(20 downto 1), data,
iosn, flash_oe_b, sram_bw, open);
flash_d <= buskeep(flash_d), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
|
-------------------------------------------------------------------------------
-- ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end ilmb_wrapper;
architecture STRUCTURE of ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 downto 0);
b: in std_logic_vector(16 downto 0);
s: out std_logic_vector(16 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
port (
faa : IN STD_LOGIC_VECTOR (5-1 downto 0);
fab : IN STD_LOGIC_VECTOR (5-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (5-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(16 downto 0);
signal b_reg : std_logic_vector(16 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(4 downto 0);
signal b0_cb : std_logic_vector(4 downto 0);
signal a1_cb : std_logic_vector(9 downto 5);
signal b1_cb : std_logic_vector(9 downto 5);
signal a2_cb : std_logic_vector(14 downto 10);
signal b2_cb : std_logic_vector(14 downto 10);
signal a3_cb : std_logic_vector(16 downto 15);
signal b3_cb : std_logic_vector(16 downto 15);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(16 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(4 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(4 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(4 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(16 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(4 downto 0);
b0_cb <= b_reg(4 downto 0);
a1_cb <= a_reg(9 downto 5);
b1_cb <= b_reg(9 downto 5);
a2_cb <= a_reg(14 downto 10);
b2_cb <= b_reg(14 downto 10);
a3_cb <= a_reg(16 downto 15);
b3_cb <= b_reg(16 downto 15);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(4 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(9 downto 5),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(14 downto 10),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(16 downto 15),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(4 downto 0);
s1_ca_rego1 (0) <= fas(9 downto 5);
s2_ca_rego2 (0) <= fas(14 downto 10);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(4 downto 0) <= s0_ca_rego0(2);
s_tmp(9 downto 5) <= s1_ca_rego1(1);
s_tmp(14 downto 10) <= s2_ca_rego2(0);
s_tmp(16 downto 15) <= fas(16 downto 15);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
generic(N : natural :=5);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_17ns_17s_17_4 is
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6_U : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_6
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
package myfixed is
generic ( whole : natural; frac : natural ); -- OK
constant width : natural := whole + frac; -- OK
type fixed_t is array (1 to width) of bit; -- OK
function "+"(x, y : fixed_t) return fixed_t; -- OK
end package;
package body myfixed is
function "+"(x, y : fixed_t) return fixed_t is
variable result : fixed_t;
begin
for i in 1 to width loop
result(i) := x(i) or y(i);
end loop;
return result;
end function;
end package body;
-------------------------------------------------------------------------------
package my_consts is
constant x : integer := 5;
constant y : integer := 6;
end package;
-------------------------------------------------------------------------------
use work.my_consts.all;
package myfixed_4_8 is new work.myfixed generic map ( x, y ); -- OK
-------------------------------------------------------------------------------
entity ent is
end entity;
architecture test of ent is
package myfixed_2_4 is new work.myfixed generic map (2, 4); -- OK
package bad1 is new work.ent generic map (2, 4); -- Error
package bad2 is new std.standard generic map (2, 4); -- Error
package bad3 is new work.not_here generic map (2, 4); -- Error
package bad4 is new work.myfixed generic map (2); -- Error
constant c : natural := myfixed_2_4.width; -- OK
constant d : myfixed_2_4.fixed_t := (others => '0'); -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package myfloat is
generic ( package fixed_pkg is new work.myfixed generic map (<>) ); -- OK
use fixed_pkg.width; -- OK
end package;
package body myfloat is
use fixed_pkg.all; -- OK
constant k : natural := whole; -- OK
function add(a, b : fixed_t) return fixed_t is
begin
return a + b; -- OK
end function;
end package body;
-------------------------------------------------------------------------------
package bad is
generic ( package bad_std is new std.standard generic map (<>) ); -- Error
end package;
-------------------------------------------------------------------------------
package my_poly1 is new work.myfloat generic map ( fixed_pkg => not_here); -- Error
-------------------------------------------------------------------------------
architecture test2 of ent is
package p1 is new work.myfloat
generic map ( fixed_pkg => work.myfixed_4_8 ); -- OK
package p2 is new work.myfloat
generic map ( fixed_pkg => p1 ); -- Error
package p3 is new work.myfloat
generic map ( fixed_pkg => std.standard ); -- Error
package p4 is new work.bad
generic map ( bad_std => work.myfixed_4_8 ); -- Error
begin
end architecture;
-------------------------------------------------------------------------------
package ptr_pkg is
generic ( type t );
type ptr is access t;
end package;
-------------------------------------------------------------------------------
package int_ptr_pkg is new work.ptr_pkg
generic map ( t => integer );
-------------------------------------------------------------------------------
use work.int_ptr_pkg;
architecture test3 of ent is
procedure p is
variable v : int_ptr_pkg.ptr;
begin
v := new integer; -- OK
int_ptr_pkg.deallocate(v); -- OK
end procedure;
begin
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_2 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_2;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_2_arch OF affine_block_ieee754_fp_multiplier_1_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_2_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_2 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_2;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_2_arch OF affine_block_ieee754_fp_multiplier_1_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_2_arch;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PREADY_FIFO_CTRL: out vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
PPE2SSE_PSEL : in vl_logic;
PPE2SSE_PWDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_STALL : out vl_logic;
ADC_FIFO_rd : in vl_logic;
ADC0_FIFO_CTRL_reg_move_target: in vl_logic;
ADC1_FIFO_CTRL_reg_move_target: in vl_logic;
ADC2_FIFO_CTRL_reg_move_target: in vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC_FIFO_PTR_inc: in vl_logic;
ADC_FIFO_PTR_clr: in vl_logic;
ADC_FIFO_PTR : out vl_logic_vector(1 downto 0);
RAM_DO_B : in vl_logic_vector(31 downto 0);
PC_init_addr : out vl_logic_vector(9 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
CURRENT_ADC_RESULT: out vl_logic_vector(11 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
ADC_FIFO_EMPTY : out vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: out vl_logic;
RRDIS0 : in vl_logic;
RRDIS1 : in vl_logic;
RRDIS2 : in vl_logic;
RR_DISABLE : out vl_logic;
ADC0_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA3 : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FIFO_CTRL;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PREADY_FIFO_CTRL: out vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
PPE2SSE_PSEL : in vl_logic;
PPE2SSE_PWDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_STALL : out vl_logic;
ADC_FIFO_rd : in vl_logic;
ADC0_FIFO_CTRL_reg_move_target: in vl_logic;
ADC1_FIFO_CTRL_reg_move_target: in vl_logic;
ADC2_FIFO_CTRL_reg_move_target: in vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC_FIFO_PTR_inc: in vl_logic;
ADC_FIFO_PTR_clr: in vl_logic;
ADC_FIFO_PTR : out vl_logic_vector(1 downto 0);
RAM_DO_B : in vl_logic_vector(31 downto 0);
PC_init_addr : out vl_logic_vector(9 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
CURRENT_ADC_RESULT: out vl_logic_vector(11 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
ADC_FIFO_EMPTY : out vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: out vl_logic;
RRDIS0 : in vl_logic;
RRDIS1 : in vl_logic;
RRDIS2 : in vl_logic;
RR_DISABLE : out vl_logic;
ADC0_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA3 : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FIFO_CTRL;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO_CTRL is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
PADDR : in vl_logic_vector(12 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PREADY_FIFO_CTRL: out vl_logic;
xfer_din_mux : in vl_logic_vector(31 downto 0);
PPE2SSE_PSEL : in vl_logic;
PPE2SSE_PWDATA : in vl_logic_vector(15 downto 0);
PPE2SSE_STALL : out vl_logic;
ADC_FIFO_rd : in vl_logic;
ADC0_FIFO_CTRL_reg_move_target: in vl_logic;
ADC1_FIFO_CTRL_reg_move_target: in vl_logic;
ADC2_FIFO_CTRL_reg_move_target: in vl_logic;
SSE_ADC0_RESULTS: in vl_logic;
SSE_ADC1_RESULTS: in vl_logic;
SSE_ADC2_RESULTS: in vl_logic;
ADC0_DATAVALID_rise: in vl_logic;
ADC1_DATAVALID_rise: in vl_logic;
ADC2_DATAVALID_rise: in vl_logic;
ADC0_RESULT : in vl_logic_vector(11 downto 0);
ADC1_RESULT : in vl_logic_vector(11 downto 0);
ADC2_RESULT : in vl_logic_vector(11 downto 0);
ADC0_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC1_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC2_CHNUMBER : in vl_logic_vector(4 downto 0);
ADC_FIFO_PTR_inc: in vl_logic;
ADC_FIFO_PTR_clr: in vl_logic;
ADC_FIFO_PTR : out vl_logic_vector(1 downto 0);
RAM_DO_B : in vl_logic_vector(31 downto 0);
PC_init_addr : out vl_logic_vector(9 downto 0);
CURRENT_ADC_CHAN: out vl_logic_vector(5 downto 0);
CURRENT_ADC_RESULT: out vl_logic_vector(11 downto 0);
ADC0_FIFO_FULL : out vl_logic;
ADC0_FIFO_AFULL : out vl_logic;
ADC1_FIFO_FULL : out vl_logic;
ADC1_FIFO_AFULL : out vl_logic;
ADC2_FIFO_FULL : out vl_logic;
ADC2_FIFO_AFULL : out vl_logic;
ADC0_FIFO_EMPTY : out vl_logic;
ADC1_FIFO_EMPTY : out vl_logic;
ADC2_FIFO_EMPTY : out vl_logic;
ADC_FIFO_EMPTY : out vl_logic;
OTHER_ADC_FIFOS_NOT_EMPTY: out vl_logic;
RRDIS0 : in vl_logic;
RRDIS1 : in vl_logic;
RRDIS2 : in vl_logic;
RR_DISABLE : out vl_logic;
ADC0_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC0_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC0_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC1_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC1_FIFO_DATA3 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_CTRL : out vl_logic_vector(31 downto 0);
ADC2_FIFO_STATUS: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA_PEEK: out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA0 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA1 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA2 : out vl_logic_vector(31 downto 0);
ADC2_FIFO_DATA3 : out vl_logic_vector(31 downto 0)
);
end F2DSS_ACE_PPE_FIFO_CTRL;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 10:19:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v13_1_2,Vivado 2016.3";
begin
end;
|
entity repro is
end repro;
architecture Behavioral of repro is
constant c_CLOCK_FREQUENCY : natural := 32000000;
constant c_SWITCH_ON_TIME_ms : time := 200 ms;
constant c_switch_ms : natural := c_SWITCH_ON_TIME_ms / 1 ms;
constant c_freq1 : real := real(c_CLOCK_FREQUENCY *
(c_SWITCH_ON_TIME_ms / 1 ms));
constant c_SWITCH_COUNT_CYCLES : integer := integer(real(c_CLOCK_FREQUENCY *
(c_SWITCH_ON_TIME_ms / 1 ms)) / 1000.0);
begin
process is
begin
report " Switch ON time " & time'image(c_SWITCH_ON_TIME_ms) severity NOTE;
report " Switch count " & natural'image(c_SWITCH_COUNT_CYCLES) severity NOTE;
-- sanity checks on time constraints
report "Clock frequency = " & natural'image(c_CLOCK_FREQUENCY) & " Hz" severity NOTE;
report "switch_time (ms): " & natural'image (c_switch_ms);
report "freq * switch_time (ms): " & real'image (c_freq1);
report "Clock period = " & time'image( 1 sec / c_CLOCK_FREQUENCY) severity NOTE;
report "Switch period = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity NOTE;
Assert c_SWITCH_ON_TIME_ms = 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES
report "Wrong Switch ON time = " & time'image ( 1 sec / c_CLOCK_FREQUENCY * c_SWITCH_COUNT_CYCLES) severity ERROR;
wait;
end process;
end Behavioral;
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
entity bounds9 is
end entity;
architecture test of bounds9 is
procedure foo(x : bit_vector) is
variable s : string(x'range);
begin
report "should not print this" severity failure;
end procedure;
begin
process is
variable v : bit_vector(0 to 3);
begin
foo(v);
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_07300_good.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Use of wait statement in testbenches: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_07300_good is
end STD_07300_good;
architecture Simulation of STD_07300_good is
-- All signals for tested modules inputs/outputs
signal Clock : std_logic := '0';
signal Reset_n : std_logic;
signal D_Signal : std_logic;
signal Q_Signal : std_logic;
-- Used to stop simulation when no more stimulus are present
signal End_Sim : std_logic;
component DFlipFlop
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end component;
begin
-- The D Flip-Flop to test
T_DFlipFlop : DFlipFlop
port map (
i_Clock => Clock,
i_Reset_n => Reset_n,
i_D => D_Signal,
o_Q => Q_Signal,
o_Q_n => open
);
-- Clock process
P_Clock : process
begin
while (End_Sim /= '1') loop
Clock <= not Clock after 5 ns;
end loop;
wait;
end process;
--CODE
-- Test process
P_Test : process
begin
Reset_n <= '0';
D_Signal <= '0';
wait until rising_edge(Clock);
Reset_n <= '1';
wait until rising_edge(Clock);
D_Signal <= '1';
wait until rising_edge(Clock);
D_Signal <= '0';
End_Sim <= '1';
wait;
-- Or if your simulator supports VHDL-2008:
-- finish(2);
end process;
--CODE
end Simulation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc360.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00360ent IS
END c03s02b01x01p02n01i00360ent;
ARCHITECTURE c03s02b01x01p02n01i00360arch OF c03s02b01x01p02n01i00360ent IS
type bit_vctor is array (positive to 7) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00360 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00360arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc360.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00360ent IS
END c03s02b01x01p02n01i00360ent;
ARCHITECTURE c03s02b01x01p02n01i00360arch OF c03s02b01x01p02n01i00360ent IS
type bit_vctor is array (positive to 7) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00360 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00360arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc360.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00360ent IS
END c03s02b01x01p02n01i00360ent;
ARCHITECTURE c03s02b01x01p02n01i00360arch OF c03s02b01x01p02n01i00360ent IS
type bit_vctor is array (positive to 7) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00360 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00360arch;
|
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector testbench
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity edgeDetector_tb is
end edgeDetector_tb;
architecture Behavioral of edgeDetector_tb is
-- Declare component:
component edgeDetector
port(
clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC
);
end component;
-- Inputs
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal enable: std_logic := '0';
signal input: std_logic := '0';
-- Outputs
signal detected: std_logic;
-- clk period
constant clk_period: time := 20 ns;
begin
-- Instantiation of edgeDetector:
uut: edgeDetector
port map(
clk => clk,
reset => reset,
enable => enable,
input => input,
detected => detected
);
-- Clock signal
clk_process : process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-- Other stimulus
stim_process : process
begin
-- Reset circuit:
reset <= '0';
wait for 80 ns;
reset <= '1';
wait for 20 ns;
-- Test circuit with enable disabled:
enable <= '0';
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
-- Test circuit with enable enabled:
enable <= '1';
wait for 2*clk_period;
input <= '1';
wait for 2*clk_period;
input <= '0';
wait for 2*clk_period;
-- Test circuit with enable disabled again:
enable <= '0';
input <= '1';
wait for 3*clk_period;
input <= '0';
wait for clk_period;
wait;
end process;
end Behavioral;
|
-------------------------------------------------------------------------
-- This file is part of Oggonachip project
---------------------------------------------------------------------------
-- Entities: butterfly_8
-- File: mdctcomp.vhd
-- Author: Luis L. Azuara
-- Description: Components requiered to perform the mdct.
-- Creation date: 27.03.02
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all;
-- use IEEE.std_logic_unsigned."+";
-- use IEEE.std_logic_unsigned."-";
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
entity butterfly_8 is
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf8_data;
dataout : out btf8_data;
enabled : in std_logic
);
end butterfly_8;
architecture rtl of butterfly_8 is
type btf8_regs is array (0 to 3) of std_logic_vector (31 downto 0);
signal procdata : btf8_data;
begin
btf8 : process (rst,datain,procdata)
variable r: btf8_regs;
variable x: btf8_data;
begin
x := datain;
r(0) := x(6) + x(2);
r(1) := x(6) - x(2);
r(2) := x(4) + x(0);
r(3) := x(4) - x(0);
x(6) := r(0) + r(2);
x(4) := r(0) - r(2);
r(0) := x(5) - x(1);
r(2) := x(7) - x(3);
x(0) := r(1) + r(0);
x(2) := r(1) - r(0);
r(0) := x(5) + x(1);
r(1) := x(7) + x(3);
x(3) := r(2) + r(3);
x(1) := r(2) - r(3);
x(7) := r(1) + r(0);
x(5) := r(1) - r(0);
procdata <= x;
dataout <= procdata;
if rst ='0' then
dataout <= (others => "00000000000000000000000000000000");
end if;
end process;
end;
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
entity butterfly_16 is
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf16_data;
dataout : out btf16_data;
enabled : in std_logic
);
end butterfly_16;
architecture rtl of butterfly_16 is
type btf16_regs is array (0 to 1) of std_logic_vector (31 downto 0);
signal procdata,bt16result : btf16_data;
component butterfly_8
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf8_data;
dataout : out btf8_data;
enabled : in std_logic
);
end component;
begin
btf16 : process (rst,datain,bt16result)
variable r: btf16_regs;
variable x: btf16_data;
begin
x := datain;
-- process butterfly 16
r(0):= x(0)(1) - x(1)(1);
r(1):= x(0)(0) - x(1)(0);
x(1)(0):= x(1)(0) + x(0)(0);
x(1)(1):= x(1)(1) + x(0)(1);
x(0)(0) := MULT_NORM((r(0) + r(1)) * cPI2_8);
x(0)(1) := MULT_NORM((r(0) - r(1)) * cPI2_8);
r(0):= x(0)(3) - x(1)(3);
r(1):= x(1)(2) - x(0)(2);
x(1)(2):= x(1)(2) + x(0)(2);
x(1)(3):= x(1)(3) + x(0)(3);
x(0)(2):= r(0);
x(0)(3):= r(1);
r(0):= x(1)(4) - x(0)(4);
r(1):= x(1)(5) - x(0)(5);
x(1)(4) := x(1)(4) + x(0)(4);
x(1)(5) := x(1)(5) + x(0)(5);
x(0)(4) := MULT_NORM((r(0) - r (1)) * cPI2_8);
x(0)(5) := MULT_NORM((r(0) + r (1)) * cPI2_8);
r(0) := x(1)(6) - x(0)(6);
r(1) := x(1)(7) - x(0)(7);
x(1)(6) := x(1)(6) + x(0)(6);
x(1)(7) := x(1)(7) + x(0)(7);
x(0)(6) := r(0);
x(0)(7) := r(1);
-- end prcess butterfly 16
if rst ='0' then
dataout(0) <= (others => "00000000000000000000000000000000");
dataout(1) <= (others => "00000000000000000000000000000000");
procdata(0)<= (others => "00000000000000000000000000000000");
procdata(1) <= (others => "00000000000000000000000000000000");
end if;
procdata <= x; -- update processed data
dataout <= bt16result;
end process;
b8_0: butterfly_8
port map (
rst => rst,
clk => clk,
datain => procdata(0),
dataout => bt16result(0),
enabled => enabled
);
b8_1: butterfly_8
port map (
rst => rst,
clk => clk,
datain => procdata(1),
dataout => bt16result(1),
enabled => enabled
);
end;
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
entity butterfly_32 is
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf32_data;
dataout : out btf32_data;
enabled : in std_logic;
ready : out std_logic
);
end butterfly_32;
architecture rtl of butterfly_32 is
type btf32_regs is array (0 to 1) of std_logic_vector (31 downto 0);
type btf32 is record
state: std_logic_vector (2 downto 0);
active: bit;
end record;
signal procdata,bt32result : btf32_data ;
signal rin: btf32;
component butterfly_16
port (
rst : in std_logic;
clk : in std_logic;
datain : in btf16_data;
dataout : out btf16_data;
enabled : in std_logic
);
end component;
begin
bf32 : process (rst,bt32result,enabled,rin,clk,datain,procdata)
variable r: btf32_regs := (others => "00000000000000000000000000000000");
variable x: block32_data:= (others => "00000000000000000000000000000000");
variable active: bit:='0';
variable bt32ready: std_logic:='1';
variable state: std_logic_vector (2 downto 0):="000";
begin
state:= rin.state;
active:=rin.active;
if rising_edge(clk) then
x := BT32_to_BLOCK32(procdata); -- loads data in register x to process
-- process butterfly 32
case state is
when "000" =>
if enabled='1' then
active:='1';
x := BT32_to_BLOCK32(datain); -- loads data in register x to process
dataout <= bt32result;
end if;
r(0) := x(30) - x(14);
r(1) := x(31) - x(15);
x(30) := x(30) + x(14);
x(31) := x(31) + x(15);
x(14) := r(0);
x(15) := r(1);
when "001" =>
r(0) := x(28) - x(12);
r(1) := x(29) - x(13);
x(28) := x(28) + x(12);
x(29) := x(29) + x(13);
x(12) := MULT_NORM( (r(0) * cPI1_8) - (r(1) * cPI3_8) );-- Normalization
x(13) := MULT_NORM( (r(0) * cPI3_8) + (r(1) * cPI1_8 ));
when "010" =>
r(0) := x(26) - x(10);
r(1) := x(27) - x(11);
x(26) := x(26) + x(10);
x(27) := x(27) + x(11);
x(10) := MULT_NORM(( r(0) - r(1) ) * cPI2_8);
x(11) := MULT_NORM(( r(0) + r(1) ) * cPI2_8);
when "011" =>
r(0) := x(24) - x(8);
r(1) := x(25) - x(9);
x(24) := x(24) + x(8);
x(25) := x(25) + x(9);
x(8) := MULT_NORM( (r(0) * cPI3_8) - (r(1) * cPI1_8) );
x(9) := MULT_NORM( (r(1) * cPI3_8) + (r(0) * cPI1_8) );
when "100" =>
r(0) := x(22) - x(6);
r(1) := x(7) - x(23);
x(22) := x(22) + x(6);
x(23) := x(23) + x(7);
x(6) := r(1);
x(7) := r(0);
when "101" =>
r(0) := x(4) - x(20);
r(1) := x(5) - x(21);
x(20) := x(20) + x(4);
x(21) := x(21) + x(5);
x(4) := MULT_NORM( (r(1) * cPI1_8) + (r(0) * cPI3_8) );
x(5) := MULT_NORM( (r(1) * cPI3_8) - (r(0) * cPI1_8) );
when "110" =>
r(0) := x(2) - x(18);
r(1) := x(3) - x(19);
x(18) := x(18) + x(2);
x(19) := x(19) + x(3);
x(2) := MULT_NORM(( r(1) + r(0) ) * cPI2_8);
x(3) := MULT_NORM(( r(1) - r(0) ) * cPI2_8);
when "111" =>
if rin.active='1' then
r(0) := x(0) - x(16);
r(1) := x(1) - x(17);
x(16) := x(16) + x(0);
x(17) := x(17) + x(1);
x(0) := MULT_NORM( (r(1) * cPI3_8) + r(0) * cPI1_8 );
x(1) := MULT_NORM( (r(1) * cPI1_8) - r(0) * cPI3_8 );
end if;
active:='0';
state:="000";
when others =>
state:="000";
end case;
-- end prcess butterfly 32
if active='1' then
state:=state +1;
end if;
rin.state <= state;
end if;
if bt32ready='0' then
procdata <= BLOCK32_to_BT32(x); -- update processed data
else
dataout <= bt32result; -- give out result
end if;
if rst='0' then
dataout(0) <= ((others => "00000000000000000000000000000000"),(others => "00000000000000000000000000000000"));
dataout(1) <= ((others => "00000000000000000000000000000000"),(others => "00000000000000000000000000000000"));
procdata(0)<= ((others => "00000000000000000000000000000000"),(others => "00000000000000000000000000000000"));
procdata(1) <= ((others => "00000000000000000000000000000000"),(others => "00000000000000000000000000000000"));
r := (others => "00000000000000000000000000000000");
x := (others => "00000000000000000000000000000000");
state := "000";
active := '0';
bt32ready := '1';
end if;
rin.active <= active;
ready <= bt32ready;
if bt32result'event and active='0' then
bt32ready:='1';
end if;
if rising_edge(enabled) then
ready <= '0';
bt32ready:='0';
end if;
end process;
--mult_gen: for i in 0 to MAXMULT generate
-- m : wbm GENERIC MAP (n=>32, m=>32)
-- port map (
-- mps(i).op1,
-- mps(i).op2,
-- mps_res(i)
-- );
--end generate;
b16_0: butterfly_16
port map (
rst => rst,
clk => clk,
datain => procdata(0),
dataout => bt32result(0),
enabled => enabled
);
b16_1: butterfly_16
port map (
rst => rst,
clk => clk,
datain => procdata(1),
dataout => bt32result(1),
enabled => enabled
);
end;
---------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
use work.mdctrom256.all;
entity butterfly_1_stage is
port (
rst : in std_logic;
clk : in std_logic;
datain : in block16_data;
dataout : out block16_data;
points : in std_logic_vector(9 downto 0);
enabled : in std_logic
);
end butterfly_1_stage;
architecture rtl of butterfly_1_stage is
type btf_1_regs is array (0 to 1) of std_logic_vector (31 downto 0);
begin
btf_1 : process (rst,datain)
variable r: btf_1_regs;
variable x1,x2: block8_data;
begin
x1 := BLOCK16_to_BLOCK8(datain,0);
x2 := BLOCK16_to_BLOCK8(datain,1);
-- Multiplication process
r(0) := x1(6) - x2(6);
r(1) := x1(7) - x2(7);
x1(6) := x1(6) + x2(6);
x1(7) := x1(7) + x2(7);
x2(6) := MULT_NORM(r(1) * T(1) + r(0) * T(0));
x2(7) := MULT_NORM(r(1) * T(0) - r(0) * T(1));
r(0) := x1(4) - x2(4);
r(1) := x1(5) - x2(5);
x1(4) := x1(4) + x2(4);
x1(5) := x1(5) + x2(5);
x2(4) := MULT_NORM(r(1) * T(5) + r(0) * T(4));
x2(5) := MULT_NORM(r(1) * T(4) - r(0) * T(5));
r(0) := x1(2) - x2(2);
r(1) := x1(3) - x2(3);
x1(2) := x1(2) + x2(2);
x1(3) := x1(3) + x2(3);
x2(2) := MULT_NORM(r(1) * T(9) + r(0) * T(8));
x2(3) := MULT_NORM(r(1) * T(8) - r(0) * T(9));
r(0) := x1(0) - x2(0);
r(1) := x1(1) - x2(1);
x1(0) := x1(0) + x2(0);
x1(1) := x1(1) + x2(1);
x2(0) := MULT_NORM(r(1) * T(13) + r(0) * T(12));
x2(1) := MULT_NORM(r(1) * T(12) - r(0) * T(13));
-- End Multiplication process
dataout <= BLOCK8_to_BLOCK16(x1,x2);
if rst ='0' then
dataout <= (others => "00000000000000000000000000000000");
end if;
end process;
end;
--------------------------------------------------------------------------------------------------
---------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
use work.mdctrom256.all;
entity butterfly_generic is
port (
rst : in std_logic;
clk : in std_logic;
datain : in block16_data;
dataout : out block16_data;
points : in std_logic_vector(9 downto 0);
trigint : in std_logic_vector(2 downto 0);
enabled : in std_logic
);
end butterfly_generic;
architecture rtl of butterfly_generic is
type btf_genregs is array (0 to 1) of std_logic_vector (31 downto 0);
begin
btf_1 : process (rst,datain)
variable r: btf_genregs;
variable x1,x2: block8_data;
begin
x1 := BLOCK16_to_BLOCK8(datain,0);
x2 := BLOCK16_to_BLOCK8(datain,1);
-- butterfly_generic process
r(0) := x1(6) - x2(6);
r(1) := x1(7) - x2(7);
x1(6) := x1(6) + x2(6);
x1(7) := x1(7) + x2(7);
x2(6) := MULT_NORM(r(1) * T(1) + r(0) * T(0));
x2(7) := MULT_NORM(r(1) * T(0) - r(0) * T(1));
-- T+:=trigint;
r(0) := x1(4) - x2(4);
r(1) := x1(5) - x2(5);
x1(4) := x1(4) + x2(4);
x1(5) := x1(5) + x2(5);
x2(4) := MULT_NORM(r(1) * T(1) + r(0) * T(0));
x2(5) := MULT_NORM(r(1) * T(0) - r(0) * T(1));
-- T+:=trigint;
r(0) := x1(2) - x2(2);
r(1) := x1(3) - x2(3);
x1(2) := x1(2) + x2(2);
x1(3) := x1(3) + x2(3);
x2(2) := MULT_NORM(r(1) * T(1) + r(0) * T(0));
x2(3) := MULT_NORM(r(1) * T(0) - r(0) * T(1));
-- T+:=trigint;
r(0) := x1(0) - x2(0);
r(1) := x1(1) - x2(1);
x1(0) := x1(0) + x2(0);
x1(1) := x1(1) + x2(1);
x2(0) := MULT_NORM(r(1) * T(1) + r(0) * T(0));
x2(1) := MULT_NORM(r(1) * T(0) - r(0) * T(1));
-- T+:=trigint;
-- End butterfly_generic process
dataout <= BLOCK8_to_BLOCK16(x1,x2);
if rst ='0' then
dataout <= (others => "00000000000000000000000000000000");
end if;
end process;
end;
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
use work.mdctrom256.all;
entity bit_reverse is
port (
rst : in std_logic;
clk : in std_logic;
datain : in block16_data;
dataout : out block16_data;
points : in std_logic_vector(9 downto 0);
trigint : in std_logic_vector(2 downto 0);
enabled : in std_logic;
ready : out std_logic
);
end bit_reverse;
architecture rtl of bit_reverse is
type bitrev_regs is array (0 to 3) of std_logic_vector (31 downto 0);
begin
btf_1 : process (rst,datain)
variable r: bitrev_regs;
variable x0,x1: block8_data;
variable w0,w1: bitrev_regs;
begin
x0 := BLOCK16_to_BLOCK8(datain,0);
x1 := BLOCK16_to_BLOCK8(datain,1);
-- bit_reverse process
-- DATA_TYPE *x0 := x+bit(0);
-- DATA_TYPE *x1 := x+bit(1);
-- REG_TYPE r0 := x0(1) - x1(1);
-- REG_TYPE r1 := x0(0) + x1(0);
-- REG_TYPE r2 := MULT_NORM(r(1) * T(0) + r(0) * T(1));
-- REG_TYPE r3 := MULT_NORM(r(1) * T(1) - r(0) * T(0));
-- w1 -:= 4;
r(0) := HALVE(x0(1) + x1(1));
r(1) := HALVE(x0(0) - x1(0));
w0(0) := r(0) + r(2);
w1(2) := r(0) - r(2);
w0(1) := r(1) + r(3);
w1(3) := r(3) - r(1);
-- x0 := x+bit(2);
-- x1 := x+bit(3);
r(0) := x0(1) - x1(1);
r(1) := x0(0) + x1(0);
r(2) := MULT_NORM(r(1) * T(2) + r(0) * T(3));
r(3) := MULT_NORM(r(1) * T(3) - r(0) * T(2));
r(0) := HALVE(x0(1) + x1(1));
r(1) := HALVE(x0(0) - x1(0));
w0(2) := r(0) + r(2);
w1(0) := r(0) - r(2);
w0(3) := r(1) + r(3);
w1(1) := r(3) - r(1);
-- T +:= 4;
-- bit +:= 4;
-- w0 +:= 4;
-- End bit_reverse process
dataout <= BLOCK8_to_BLOCK16(x0,x1);
if rst ='0' then
dataout <= (others => "00000000000000000000000000000000");
end if;
end process;
end;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
--use work.mdctrom256.all;
entity pre_process is
port (
rst : in std_logic;
clk : in std_logic;
datain : in block4_data;
dataout : out block4_data;
lut : in block4_data;
funct : in std_logic;
enabled : in std_logic;
ready : out std_logic
);
end pre_process;
architecture rtl of pre_process is
constant s0 : std_logic:='0';
constant s1 : std_logic:='1';
type inctrl is record
state : std_logic;
procdata : block4_data;
active : std_logic;
end record;
signal r,rin : inctrl;
begin
premult : process (rst,r,datain,enabled,lut)
variable iX,oX,T: block4_data;
variable tmp: inctrl;
begin
tmp := r;
if enabled ='1' then
case r.state is
when s0 =>
tmp.active:='1';
ix := datain; -- read data
T:=lut;
ready <= '0'; -- processing
oX(0):= MULT_NORM(-iX(1) * T(3) - iX(0) * T(2));
oX(1):= MULT_NORM (iX(0) * T(3) - iX(1) * T(2));
tmp.state:=s1;
when s1 =>
oX(2):= MULT_NORM(-iX(3) * T(1) - iX(2) * T(0));
oX(3):= MULT_NORM (iX(2) * T(1) - iX(3) * T(0));
tmp.state:=s0;
tmp.active:='0';
when others => null;
end case;
tmp.procdata:=oX;
else
tmp.active:='0';
end if;
if r.active'event and r.active='0' then -- when deactivated
dataout <= r.procdata;
ready <= '1';
end if;
if rst ='0' then
dataout <= (others => "00000000000000000000000000000000");
ready <= '1';
tmp.state:=s0;
tmp.procdata:=(others => "00000000000000000000000000000000");
tmp.active:='0';
end if;
rin <= tmp;
end process;
clkup: process (clk)
begin -- process clk
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
entity multadd is
port (
rst : in std_logic;
clk : in std_logic;
datain : in in_multadd;
dataout : out out_multadd
);
end multadd;
architecture rtl of multadd is
begin
-- purpose: 2 multiplications with an 64-bits adder
-- return 32 bits result after multipliers and adder
-- r_mult=MULT_NORM(op1_m1*op2_m1+/-op1_m2*op2_m2)
-- type : combinational
-- inputs : clk,rst,datain
-- outputs: dataout
mult: process (clk,rst,datain)
variable r1_64,r2_64: std_logic_vector (63 downto 0) := (others => '0');
-- result registers for multiplication
variable ra_32 : std_logic_vector (31 downto 0) := (others => '0');
-- result register after addition
begin -- process mult
r1_64 := datain.op1_m1 * datain.op2_m1;
r2_64 := datain.op1_m2 * datain.op2_m2;
if datain.add_fun='1' then
ra_32 := MULT_NORM(r1_64 + r2_64);
elsif datain.add_fun='0' then
ra_32 := MULT_NORM(r1_64 - r2_64);
end if;
if rst='0' then
dataout.r_m1 <= (others => '0');
dataout.r_m2 <= (others => '0');
dataout.r_mult <= (others => '0');
elsif rst='1' then
dataout.r_m1 <= MULT_NORM(r1_64);
dataout.r_m2 <= MULT_NORM(r2_64);
dataout.r_mult <= ra_32;
end if;
end process mult;
end;
--------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.mdctlib.all;
use IEEE.std_logic_signed.all;
entity addbank is
port (
rst : in std_logic;
clk : in std_logic;
datain : in in_addbank;
dataout : out out_addbank
);
end addbank;
architecture rtl of addbank is
begin -- rtl
-- purpose: 3 preconf adders and 3 substractions
-- type : combinational
-- inputs : clk,rst,datain
-- outputs: dataout
add: process (clk,rst,datain)
begin -- process add
if rst ='0' then
dataout.r_a1 <= (others => '0');
dataout.r_a2 <= (others => '0');
dataout.r_a3 <= (others => '0');
dataout.r_s1 <= (others => '0');
dataout.r_s2 <= (others => '0');
dataout.r_s3 <= (others => '0');
elsif rst='1' then
dataout.r_a1 <= datain.op1_a1 + datain.op2_a1;
dataout.r_a2 <= datain.op1_a2 + datain.op2_a2;
dataout.r_a3 <= datain.op1_a3 + datain.op2_a3;
dataout.r_s1 <= datain.op1_s1 - datain.op2_s1;
dataout.r_s2 <= datain.op1_s2 - datain.op2_s2;
dataout.r_s3 <= datain.op1_s3 - datain.op2_s3;
end if;
end process add;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_baud_gen is
generic (
g_baud_acc_width : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baudrate_i : in std_logic_vector(g_baud_acc_width downto 0);
baud_tick_o : out std_logic;
baud8_tick_o : out std_logic);
end uart_baud_gen;
architecture behavioral of uart_baud_gen is
signal Baud8GeneratorInc : unsigned(g_baud_acc_width downto 0);
signal Baud8GeneratorAcc : unsigned(g_baud_acc_width downto 0);
signal Baud8Tick : std_logic;
signal Baud_sreg : std_logic_vector(7 downto 0) := "10000000";
begin -- behavioral
Baud8GeneratorInc <= unsigned(baudrate_i);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
Baud8GeneratorAcc <= (others => '0');
else
Baud8GeneratorAcc <= ('0' & Baud8GeneratorAcc(Baud8GeneratorAcc'high-1 downto 0)) + Baud8GeneratorInc;
end if;
end if;
end process;
Baud8Tick <= std_logic(Baud8GeneratorAcc(g_baud_acc_width));
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
Baud_sreg <= "10000000";
elsif Baud8Tick = '1' then
Baud_sreg <= Baud_sreg(0) & Baud_sreg(7 downto 1);
end if;
end if;
end process;
baud_tick_o <= Baud_sreg(0) and Baud8Tick;
baud8_tick_o <= Baud8Tick;
end behavioral;
|
entity ent is
generic (
t1 : time := 2 sec;
t2 : time := 5 sec
);
end;
architecture a of ent is
constant t3 : time := t1 + t2;
constant diff : time := abs (t1 - t2);
constant shorter : time := minimum(t1, t2);
constant longer : time := maximum(t1, t2);
constant ratio1 : natural := t1 / t2;
constant ratio2 : natural := (t1 / 2) / (t2 * 0.5);
constant ratio3 : natural := (t1 * 2) / (t2 / 0.5);
begin
assert t3 > 6 sec;
assert t3 = 7 sec;
assert t3 < 8 sec;
assert t3 /= 1 ns;
assert t3 >= shorter;
assert shorter <= longer;
assert diff = longer - shorter;
assert -diff = +(shorter-longer);
assert ratio1 = ratio2;
assert ratio1 = ratio3;
assert t1 * 2 = 2 * t1;
assert t1 * 0.5 = 0.5 * t1;
end;
|
--Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_edge_to_pulse;
architecture europa of niosII_openMac_clock_1_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_slave_FSM;
architecture europa of niosII_openMac_clock_1_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_master_FSM;
architecture europa of niosII_openMac_clock_1_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_1_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1_bit_pipe;
architecture europa of niosII_openMac_clock_1_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_1
entity niosII_openMac_clock_1 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_1;
architecture europa of niosII_openMac_clock_1 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_1_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_edge_to_pulse;
component niosII_openMac_clock_1_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_slave_FSM;
component niosII_openMac_clock_1_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_master_FSM;
component niosII_openMac_clock_1_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_1_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_1_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_1_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_1_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_1_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("00000000000000000000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("00000000000000000000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000000000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("00000000");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("00000000");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
|
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--64-bit Kogge-Stone adder is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------
-------------------------------------------------------
-- Project : Computer arithmetic, fast adders (3rd year mini project)
-- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi
-- Date : 10-05-2014
-- File : KSA_pkg.vhd
-- Design : 64-bit Kogge-Stone adder
------------------------------------------------------
-- Description : a package containing components used in a 64-bit Kogge-Stone adder
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE KSA_pkg IS
--g,p generator--
COMPONENT gp_gen IS
PORT(
x : IN std_logic;
y : IN std_logic;
g : OUT std_logic;
p : OUT std_logic
);
END COMPONENT;
--carry operator--
COMPONENT carry_op IS
PORT(
g1 : IN std_logic;
p1 : IN std_logic;
g2 : IN std_logic;
p2 : IN std_logic;
go : OUT std_logic;
po : OUT std_logic
);
END COMPONENT;
END KSA_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: hs
-- File: hs.vhd
-- Author: David Lindh - Gaisler Research
-- Description: High speed DDR memory interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
library gaisler;
use gaisler.ddrrec.all;
entity hs is
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end entity hs;
architecture rtl of hs is
type wait_times_row_type is array(7 downto 0) of integer range 0 to 31;
type wait_times_matrix_type is array(7 downto 0) of wait_times_row_type;
constant DELAY_15NS : integer := (((15*1000)-1) / (clkperiod*1000))+1;
constant DELAY_20NS : integer := (((20*1000)-1) / (clkperiod*1000))+1;
constant DELAY_50NS : integer := (((50*1000)-1) / (clkperiod*1000))+1;
constant DELAY_75NS : integer := (((75*1000)-1) / (clkperiod*1000))+1;
constant DELAY_80NS : integer := (((80*1000)-1) / (clkperiod*1000))+1;
constant DELAY_120NS : integer := (((120*1000)-1) / (clkperiod*1000))+1;
constant wait_times : wait_times_matrix_type :=
-- NOP,BST,READ,WRITE,ACT,PRE,RFSH,LMR
((0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 2, DELAY_20NS, 10, 10, 10),
(0, 0, 3, 0, DELAY_20NS, 10, 10, 10),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, DELAY_15NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, 0, 1+DELAY_15NS, DELAY_50NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2));
--signal cmdr : cmd_reg_type; signal cmdri: cmd_reg_type;
signal rwr : rw_reg_type; signal rwri : rw_reg_type;
signal data_out : std_logic_vector((dqsize-1) downto 0);
signal data_in : std_logic_vector((dqsize-1) downto 0);
signal strobe_out : std_logic_vector((strobesize-1) downto 0);
signal mask_out : std_logic_vector((dmsize-1) downto 0);
signal dq1_i : std_logic_vector((dqsize-1) downto 0);
signal dq1del_i : std_logic_vector((dqsize-1) downto 0);
signal dq2_i : std_logic_vector((dqsize-1) downto 0);
signal dq1_o : std_logic_vector((dqsize-1) downto 0);
signal dq2_o : std_logic_vector((dqsize-1) downto 0);
signal dm1_o : std_logic_vector((dmsize-1) downto 0);
signal dm2_o : std_logic_vector((dmsize-1) downto 0);
signal dqs1_o, dqs2_o, w_ce, r_ce, vcc, gnd : std_ulogic;
-- DQS delay control signal
signal uddcntl : std_ulogic;
signal lock : std_ulogic;
signal dqsdel : std_ulogic;
signal read : std_ulogic;
signal dqso : std_logic_vector((strobesize-1) downto 0);
signal ddrclkpol : std_logic_vector((strobesize-1) downto 0);
signal invrst : std_logic;
signal clk_90 :std_ulogic;
begin
-------------------------------------------------------------------------------
rwcomb : process(rst, hssi, rwr, dq1_i, dq1del_i, dq2_i)
variable v : rw_reg_type;
begin
v:= rwr;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
v.begin_read := '0';
v.begin_write := '0';
-------------------------------------------------------------------------------
-- Buffer for incoming command
-------------------------------------------------------------------------------
case v.cbufstate is
when no_cmd =>
v.hs_busy := '0';
if hssi.cmd_valid = '1' then
v.next_bl := hssi.bl; v.next_buf := hssi.buf; v.next_cas := hssi.cas;
v.next_adr := hssi.adr; v.next_cs := hssi.cs; v.next_cmd := hssi.cmd;
v.next_ml := hssi.ml; v.next_ahb := hssi.ahb;
v.cbufstate := new_cmd;
end if;
when new_cmd =>
v.hs_busy := '1';
end case;
-------------------------------------------------------------------------------
-- Send commands
-------------------------------------------------------------------------------
case v.cmdstate is
when idle =>
v.holdcnt := 0;
if rwr.cbufstate = new_cmd then
v.rw_cmd := rwr.next_cmd;
v.rw_bl := rwr.next_bl;
v.rw_cas := 2 + conv_integer(rwr.next_cas(0))+ conv_integer(rwr.next_cas(1));
v.set_cmd := rwr.next_cmd;
v.set_adr := rwr.next_adr;
v.set_cs := rwr.next_cs;
v.set_cke := '1';
v.cbufstate := no_cmd;
v.cmdstate := hold;
-- Read command, delay start of Read machine
if rwr.next_cmd = CMD_READ then
if rwr.next_cas = "00" then -- cas 2
v.readwait(5) := '1';
v.bufwait(5):= rwr.next_buf;
v.ahbwait(5) := rwr.next_ahb;
v.blwait(5) := rwr.next_bl;
v.caswait(5) := rwr.next_cas(0);
else -- cas 2.5 or 3
v.readwait(6) := '1';
v.bufwait(6):= rwr.next_buf;
v.ahbwait(6) := rwr.next_ahb;
v.blwait(6) := rwr.next_bl;
v.caswait(6) := rwr.next_cas(0);
end if;
-- Calculate delay until write can begin
v.r2wholdcnt := rwr.rw_cas + rwr.rw_bl/2 +2;
-- Write command, immediately start Write machine
elsif rwr.next_cmd = CMD_WRITE then
v.writewait(1) := '1';
v.bufwait(1):= rwr.next_buf;
v.ahbwait(1) := rwr.next_ahb;
v.blwait(1) := rwr.next_bl;
v.mlwait(1) := rwr.next_ml;
-- Active command, begin count towards ealiest precharge
elsif rwr.next_cmd = CMD_ACTIVE then
v.act2precnt := DELAY_50NS-1;
end if;
end if;
-- Wait until next cmd is valid to send
when hold =>
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
-- Some waittimes which isn't constant
if v.rw_cmd = CMD_READ and rwr.next_cmd = CMD_WRITE then
v.wait_time := v.rw_cas + v.rw_bl/2;
elsif v.rw_cmd = CMD_READ or v.rw_cmd = CMD_WRITE then
v.wait_time := v.rw_bl/2;
else
v.wait_time := 0;
end if;
-- Calculate total wait time
if rwr.cbufstate = new_cmd then
if ((v.holdcnt+2 >= wait_times(conv_integer(rwr.next_cmd))(conv_integer(v.rw_cmd))+ v.wait_time)
and (v.r2wholdcnt = 0 or rwr.next_cmd /= CMD_WRITE)
and (v.act2precnt = 0 or rwr.next_cmd /= CMD_PRE)) then
v.cmdstate := idle;
end if;
elsif v.holdcnt >= 4+DELAY_120NS then
v.cmdstate := idle;
end if;
v.holdcnt := v.holdcnt +1;
end case;
-- Separate count for time beteen a read and write and between active and precharge
if v.r2wholdcnt /= 0 then v.r2wholdcnt := v.r2wholdcnt -1; end if;
if v.act2precnt /= 0 then v.act2precnt := v.act2precnt -1; end if;
-------------------------------------------------------------------------------
-- Delay cmd data for Read machine during CAS period
-------------------------------------------------------------------------------
if v.readwait(0) = '1' or v.writewait(0) = '1' then
v.begin_read := v.readwait(0);
v.begin_write := v.writewait(0);
v.use_ahb := v.ahbwait(0);
v.use_buf := v.bufwait(0);
v.use_bl := v.blwait(0);
if v.writewait(0) = '1' then
v.use_ml := v.mlwait(0);
else
v.use_cas := v.caswait(0);
end if;
end if;
v.readwait := '0' & v.readwait(6 downto 1);
v.writewait := '0' & v.writewait(1);
v.bufwait(5 downto 0) := v.bufwait(6 downto 1);
v.ahbwait := 0 & v.ahbwait(6 downto 1);
v.blwait := 8 & v.blwait(6 downto 1);
v.mlwait := 1 & v.mlwait(1);
v.caswait := '0' & v.caswait(6 downto 1);
-------------------------------------------------------------------------------
-- Send/recieve data
-------------------------------------------------------------------------------
-- Read and Write routines
case v.rwstate is
when idle =>
v.sync_adr(0) := (v.cur_buf(0)+1) & "00";
v.sync_adr(1) := (v.cur_buf(1)+1) & "00";
v.cmdDone := v.cur_buf;
v.sync_write:= "00";
v.dq_dqs_oe := '1';
v.dqs1_o := '0';
v.w_ce := '0';
v.r_ce := '1';
v.cnt := 0;
if v.begin_write = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.dq_dqs_oe := '0';
v.w_ce := '1';
v.cnt := v.cnt +2;
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.rwstate := w;
elsif v.begin_read = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
v.sync_write(v.use_ahb) := '1';
v.cnt := v.cnt +2;
v.cmdDone(v.use_ahb) := v.use_buf;
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
v.rwstate := r;
end if;
-- Write
when w =>
v.dqs1_o := '1';
v.dq_dqs_oe := '0';
if v.cnt = v.use_bl then
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.begin_write = '0' then -- No new write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else -- New write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.cnt := 2;
end if;
else
v.cnt := v.cnt +2;
if v.cnt = v.use_bl then
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
else
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb)+1;
end if;
end if;
-- Read
when r =>
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
if v.cnt = v.use_bl then
if v.begin_read = '0' then
v.sync_write := "00";
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 2;
v.cur_ahb := v.use_ahb;
v.cur_buf(v.use_ahb) := v.use_buf;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
if v.use_ahb = 0 then
v.sync_write := "01";
else
v.sync_write := "10";
end if;
end if;
else
v.cnt := v.cnt +2;
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb) +1;
end if;
end case;
-- Calculate and set data mask
if v.use_ml+1 < v.cnt then
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
elsif v.use_ml+1 = v.cnt then
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o := (others => '1');
else
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+2*dmsize)-1 downto (2*dqsize+dmsize));
end if;
-------------------------------------------------------------------------------
-- Register and reset
if rst = '0' then
v.cbufstate := no_cmd;
v.cmdstate := idle;
v.rwstate := idle;
v.cur_buf := (others => (others => '1'));
v.cur_ahb := 0;
v.use_bl := 4;
v.use_ml := 2;
v.use_buf := (others => '1');
v.use_cas := '0';
v.rw_cmd := CMD_NOP;
v.rw_bl := 4;
v.rw_cas := 2;
v.next_bl := 4;
v.next_ml := 2;
v.next_buf := (others => '1');
v.next_cas := "00";
v.next_adr := (others => '0');
v.next_cs := "11";
v.next_cmd := CMD_NOP;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "00";
v.set_cke := '0';
v.hs_busy := '0';
v.cmdDone := (others => (others => '1'));
v.begin_read := '0';
v.begin_write := '0';
v.dq_dqs_oe := '1';
v.w_ce := '0';
v.r_ce := '0';
v.cnt := 0;
v.holdcnt := 0;
v.r2wholdcnt:= 0;
v.act2precnt:= 0;
v.wait_time := 10;
v.readwait := (others => '0');
v.writewait := (others => '0');
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
v.dqs1_o := '0';
v.sync_adr := (others => (others => '0'));
v.sync_write := "00";
v.sync_wdata := (others => '0');
end if;
rwri <= v;
-- Combinatiorial outputs
hsso.hs_busy <= v.hs_busy;
dqs1_o <= v.dqs1_o;
dqs2_o <= '0';
hsso.dsramsi(0).address2 <= v.sync_adr(0);
hsso.dsramsi(0).write2 <= v.sync_write(0);
hsso.dsramsi(0).datain2 <= v.sync_wdata;
hsso.dsramsi(1).address2 <= v.sync_adr(1);
hsso.dsramsi(1).write2 <= v.sync_write(1);
hsso.dsramsi(1).datain2 <= v.sync_wdata;
end process;
-------------------------------------------------------------------------------
-- Clocked processes
-- CLK0, Main register
rwclk : process(clk0)
begin
if rising_edge(clk0) then
rwr <= rwri;
-- Registered outputs
r_ce <= rwri.r_ce;
w_ce <= rwri.w_ce;
hsso.cmdDone <= rwri.cmdDone;
dm1_o <= rwri.dm1_o((dmsize-1) downto 0);
dm2_o <= rwri.dm2_o((dmsize-1) downto 0);
-- Registers
dq1del_i <= dq1_i;
dq1_o <= hssi.dsramso(rwri.use_ahb).dataout2(dqsize-1 downto 0);
dq2_o <= hssi.dsramso(rwri.use_ahb).dataout2((2*dqsize)-1 downto dqsize);
end if;
end process;
---- CLK270, Drives output enable signal
--oeclk : process(rst, clk270)
-- begin
-- if rst = '0' then
-- hsso.ddsi.dq_dqs_oe <= '1';
-- elsif rising_edge(clk270) then
-- hsso.ddsi.dq_dqs_oe <= rwri.dq_dqs_oe;
-- end if;
-- end process;
-- CLK0, Drives control signals
cmdclk : process(clk0)
begin
if rising_edge(clk0) then
hsso.ddsi.control <= rwri.set_cmd;
hsso.ddsi.adr <= rwri.set_adr((adrbits-3) downto 0);
hsso.ddsi.ba <= rwri.set_adr((adrbits-1) downto (adrbits-2));
hsso.ddsi.cs <= rwri.set_cs;
hsso.ddsi.cke <= rwri.set_cke;
end if;
end process;
vcc <= '1';
gnd <= '0';
data_in <= hssi.ddso.dq((dqsize-1) downto 0);
hsso.ddsi.dq((dqsize-1) downto 0) <= data_out;
hsso.ddsi.dqs((strobesize-1) downto 0) <= strobe_out;
hsso.ddsi.dm((dmsize-1) downto 0) <= mask_out;
dqot : if dqsize < maxdqsize generate
hsso.ddsi.dq((maxdqsize-1) downto dqsize) <= (others => '-');
end generate;
dqsot : if strobesize < maxstrobesize generate
hsso.ddsi.dqs((maxstrobesize-1) downto strobesize) <= (others => '-');
end generate;
dmot : if dmsize <= maxdmsize generate
hsso.ddsi.dm((maxdmsize-1) downto dmsize) <= (others => '-');
end generate;
-------------------------------------------------------------------------------
-- DDR IO registers
-------------------------------------------------------------------------------
-- Input and Output DQ
dqio : for i in 0 to (dqsize-1) generate
in1 : ddr_ireg generic map( tech => tech)
port map(
Q1 => dq1_i(i),
Q2 => dq2_i(i),
C1 => clk0,
C2 => clk180,
CE => vcc, --r_ce,
D => data_in(i),
R => gnd,
S => gnd);
out1 : ddr_oreg
generic map( tech => tech)
port map(
Q => data_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => dq1_o(i),
D2 => dq2_o(i),
R => gnd,
S => gnd);
dq_tri : ddr_oreg generic map(
tech => tech)
port map(
Q => hsso.ddsi.dq_oe(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- output DQS
dqsio : for i in 0 to (strobesize-1) generate
dqso : ddr_oreg
generic map(
tech => tech)
port map(
Q => strobe_out(i),
C1 => clk270,
C2 => clk90,
CE => vcc,
D1 => dqs1_o,
D2 => dqs2_o,
R => gnd,
S => gnd);
dqso_tri : ddr_oreg
generic map(
tech => tech)
port map(
Q => hsso.ddsi.dqs_oe(i),
C1 => clk270,
C2 => clk90,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- Output DM
dmo : for i in 0 to (dmsize-1) generate
U4 : ddr_oreg
generic map(
tech => tech)
port map(
Q => mask_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce, --write_ce
D1 => dm1_o(i),
D2 => dm2_o(i),
R => gnd,
S => gnd);
end generate;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: hs
-- File: hs.vhd
-- Author: David Lindh - Gaisler Research
-- Description: High speed DDR memory interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
library gaisler;
use gaisler.ddrrec.all;
entity hs is
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end entity hs;
architecture rtl of hs is
type wait_times_row_type is array(7 downto 0) of integer range 0 to 31;
type wait_times_matrix_type is array(7 downto 0) of wait_times_row_type;
constant DELAY_15NS : integer := (((15*1000)-1) / (clkperiod*1000))+1;
constant DELAY_20NS : integer := (((20*1000)-1) / (clkperiod*1000))+1;
constant DELAY_50NS : integer := (((50*1000)-1) / (clkperiod*1000))+1;
constant DELAY_75NS : integer := (((75*1000)-1) / (clkperiod*1000))+1;
constant DELAY_80NS : integer := (((80*1000)-1) / (clkperiod*1000))+1;
constant DELAY_120NS : integer := (((120*1000)-1) / (clkperiod*1000))+1;
constant wait_times : wait_times_matrix_type :=
-- NOP,BST,READ,WRITE,ACT,PRE,RFSH,LMR
((0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 2, DELAY_20NS, 10, 10, 10),
(0, 0, 3, 0, DELAY_20NS, 10, 10, 10),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, DELAY_15NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, 0, 1+DELAY_15NS, DELAY_50NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2));
--signal cmdr : cmd_reg_type; signal cmdri: cmd_reg_type;
signal rwr : rw_reg_type; signal rwri : rw_reg_type;
signal data_out : std_logic_vector((dqsize-1) downto 0);
signal data_in : std_logic_vector((dqsize-1) downto 0);
signal strobe_out : std_logic_vector((strobesize-1) downto 0);
signal mask_out : std_logic_vector((dmsize-1) downto 0);
signal dq1_i : std_logic_vector((dqsize-1) downto 0);
signal dq1del_i : std_logic_vector((dqsize-1) downto 0);
signal dq2_i : std_logic_vector((dqsize-1) downto 0);
signal dq1_o : std_logic_vector((dqsize-1) downto 0);
signal dq2_o : std_logic_vector((dqsize-1) downto 0);
signal dm1_o : std_logic_vector((dmsize-1) downto 0);
signal dm2_o : std_logic_vector((dmsize-1) downto 0);
signal dqs1_o, dqs2_o, w_ce, r_ce, vcc, gnd : std_ulogic;
-- DQS delay control signal
signal uddcntl : std_ulogic;
signal lock : std_ulogic;
signal dqsdel : std_ulogic;
signal read : std_ulogic;
signal dqso : std_logic_vector((strobesize-1) downto 0);
signal ddrclkpol : std_logic_vector((strobesize-1) downto 0);
signal invrst : std_logic;
signal clk_90 :std_ulogic;
begin
-------------------------------------------------------------------------------
rwcomb : process(rst, hssi, rwr, dq1_i, dq1del_i, dq2_i)
variable v : rw_reg_type;
begin
v:= rwr;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
v.begin_read := '0';
v.begin_write := '0';
-------------------------------------------------------------------------------
-- Buffer for incoming command
-------------------------------------------------------------------------------
case v.cbufstate is
when no_cmd =>
v.hs_busy := '0';
if hssi.cmd_valid = '1' then
v.next_bl := hssi.bl; v.next_buf := hssi.buf; v.next_cas := hssi.cas;
v.next_adr := hssi.adr; v.next_cs := hssi.cs; v.next_cmd := hssi.cmd;
v.next_ml := hssi.ml; v.next_ahb := hssi.ahb;
v.cbufstate := new_cmd;
end if;
when new_cmd =>
v.hs_busy := '1';
end case;
-------------------------------------------------------------------------------
-- Send commands
-------------------------------------------------------------------------------
case v.cmdstate is
when idle =>
v.holdcnt := 0;
if rwr.cbufstate = new_cmd then
v.rw_cmd := rwr.next_cmd;
v.rw_bl := rwr.next_bl;
v.rw_cas := 2 + conv_integer(rwr.next_cas(0))+ conv_integer(rwr.next_cas(1));
v.set_cmd := rwr.next_cmd;
v.set_adr := rwr.next_adr;
v.set_cs := rwr.next_cs;
v.set_cke := '1';
v.cbufstate := no_cmd;
v.cmdstate := hold;
-- Read command, delay start of Read machine
if rwr.next_cmd = CMD_READ then
if rwr.next_cas = "00" then -- cas 2
v.readwait(5) := '1';
v.bufwait(5):= rwr.next_buf;
v.ahbwait(5) := rwr.next_ahb;
v.blwait(5) := rwr.next_bl;
v.caswait(5) := rwr.next_cas(0);
else -- cas 2.5 or 3
v.readwait(6) := '1';
v.bufwait(6):= rwr.next_buf;
v.ahbwait(6) := rwr.next_ahb;
v.blwait(6) := rwr.next_bl;
v.caswait(6) := rwr.next_cas(0);
end if;
-- Calculate delay until write can begin
v.r2wholdcnt := rwr.rw_cas + rwr.rw_bl/2 +2;
-- Write command, immediately start Write machine
elsif rwr.next_cmd = CMD_WRITE then
v.writewait(1) := '1';
v.bufwait(1):= rwr.next_buf;
v.ahbwait(1) := rwr.next_ahb;
v.blwait(1) := rwr.next_bl;
v.mlwait(1) := rwr.next_ml;
-- Active command, begin count towards ealiest precharge
elsif rwr.next_cmd = CMD_ACTIVE then
v.act2precnt := DELAY_50NS-1;
end if;
end if;
-- Wait until next cmd is valid to send
when hold =>
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
-- Some waittimes which isn't constant
if v.rw_cmd = CMD_READ and rwr.next_cmd = CMD_WRITE then
v.wait_time := v.rw_cas + v.rw_bl/2;
elsif v.rw_cmd = CMD_READ or v.rw_cmd = CMD_WRITE then
v.wait_time := v.rw_bl/2;
else
v.wait_time := 0;
end if;
-- Calculate total wait time
if rwr.cbufstate = new_cmd then
if ((v.holdcnt+2 >= wait_times(conv_integer(rwr.next_cmd))(conv_integer(v.rw_cmd))+ v.wait_time)
and (v.r2wholdcnt = 0 or rwr.next_cmd /= CMD_WRITE)
and (v.act2precnt = 0 or rwr.next_cmd /= CMD_PRE)) then
v.cmdstate := idle;
end if;
elsif v.holdcnt >= 4+DELAY_120NS then
v.cmdstate := idle;
end if;
v.holdcnt := v.holdcnt +1;
end case;
-- Separate count for time beteen a read and write and between active and precharge
if v.r2wholdcnt /= 0 then v.r2wholdcnt := v.r2wholdcnt -1; end if;
if v.act2precnt /= 0 then v.act2precnt := v.act2precnt -1; end if;
-------------------------------------------------------------------------------
-- Delay cmd data for Read machine during CAS period
-------------------------------------------------------------------------------
if v.readwait(0) = '1' or v.writewait(0) = '1' then
v.begin_read := v.readwait(0);
v.begin_write := v.writewait(0);
v.use_ahb := v.ahbwait(0);
v.use_buf := v.bufwait(0);
v.use_bl := v.blwait(0);
if v.writewait(0) = '1' then
v.use_ml := v.mlwait(0);
else
v.use_cas := v.caswait(0);
end if;
end if;
v.readwait := '0' & v.readwait(6 downto 1);
v.writewait := '0' & v.writewait(1);
v.bufwait(5 downto 0) := v.bufwait(6 downto 1);
v.ahbwait := 0 & v.ahbwait(6 downto 1);
v.blwait := 8 & v.blwait(6 downto 1);
v.mlwait := 1 & v.mlwait(1);
v.caswait := '0' & v.caswait(6 downto 1);
-------------------------------------------------------------------------------
-- Send/recieve data
-------------------------------------------------------------------------------
-- Read and Write routines
case v.rwstate is
when idle =>
v.sync_adr(0) := (v.cur_buf(0)+1) & "00";
v.sync_adr(1) := (v.cur_buf(1)+1) & "00";
v.cmdDone := v.cur_buf;
v.sync_write:= "00";
v.dq_dqs_oe := '1';
v.dqs1_o := '0';
v.w_ce := '0';
v.r_ce := '1';
v.cnt := 0;
if v.begin_write = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.dq_dqs_oe := '0';
v.w_ce := '1';
v.cnt := v.cnt +2;
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.rwstate := w;
elsif v.begin_read = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
v.sync_write(v.use_ahb) := '1';
v.cnt := v.cnt +2;
v.cmdDone(v.use_ahb) := v.use_buf;
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
v.rwstate := r;
end if;
-- Write
when w =>
v.dqs1_o := '1';
v.dq_dqs_oe := '0';
if v.cnt = v.use_bl then
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.begin_write = '0' then -- No new write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else -- New write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.cnt := 2;
end if;
else
v.cnt := v.cnt +2;
if v.cnt = v.use_bl then
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
else
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb)+1;
end if;
end if;
-- Read
when r =>
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
if v.cnt = v.use_bl then
if v.begin_read = '0' then
v.sync_write := "00";
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 2;
v.cur_ahb := v.use_ahb;
v.cur_buf(v.use_ahb) := v.use_buf;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
if v.use_ahb = 0 then
v.sync_write := "01";
else
v.sync_write := "10";
end if;
end if;
else
v.cnt := v.cnt +2;
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb) +1;
end if;
end case;
-- Calculate and set data mask
if v.use_ml+1 < v.cnt then
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
elsif v.use_ml+1 = v.cnt then
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o := (others => '1');
else
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+2*dmsize)-1 downto (2*dqsize+dmsize));
end if;
-------------------------------------------------------------------------------
-- Register and reset
if rst = '0' then
v.cbufstate := no_cmd;
v.cmdstate := idle;
v.rwstate := idle;
v.cur_buf := (others => (others => '1'));
v.cur_ahb := 0;
v.use_bl := 4;
v.use_ml := 2;
v.use_buf := (others => '1');
v.use_cas := '0';
v.rw_cmd := CMD_NOP;
v.rw_bl := 4;
v.rw_cas := 2;
v.next_bl := 4;
v.next_ml := 2;
v.next_buf := (others => '1');
v.next_cas := "00";
v.next_adr := (others => '0');
v.next_cs := "11";
v.next_cmd := CMD_NOP;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "00";
v.set_cke := '0';
v.hs_busy := '0';
v.cmdDone := (others => (others => '1'));
v.begin_read := '0';
v.begin_write := '0';
v.dq_dqs_oe := '1';
v.w_ce := '0';
v.r_ce := '0';
v.cnt := 0;
v.holdcnt := 0;
v.r2wholdcnt:= 0;
v.act2precnt:= 0;
v.wait_time := 10;
v.readwait := (others => '0');
v.writewait := (others => '0');
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
v.dqs1_o := '0';
v.sync_adr := (others => (others => '0'));
v.sync_write := "00";
v.sync_wdata := (others => '0');
end if;
rwri <= v;
-- Combinatiorial outputs
hsso.hs_busy <= v.hs_busy;
dqs1_o <= v.dqs1_o;
dqs2_o <= '0';
hsso.dsramsi(0).address2 <= v.sync_adr(0);
hsso.dsramsi(0).write2 <= v.sync_write(0);
hsso.dsramsi(0).datain2 <= v.sync_wdata;
hsso.dsramsi(1).address2 <= v.sync_adr(1);
hsso.dsramsi(1).write2 <= v.sync_write(1);
hsso.dsramsi(1).datain2 <= v.sync_wdata;
end process;
-------------------------------------------------------------------------------
-- Clocked processes
-- CLK0, Main register
rwclk : process(clk0)
begin
if rising_edge(clk0) then
rwr <= rwri;
-- Registered outputs
r_ce <= rwri.r_ce;
w_ce <= rwri.w_ce;
hsso.cmdDone <= rwri.cmdDone;
dm1_o <= rwri.dm1_o((dmsize-1) downto 0);
dm2_o <= rwri.dm2_o((dmsize-1) downto 0);
-- Registers
dq1del_i <= dq1_i;
dq1_o <= hssi.dsramso(rwri.use_ahb).dataout2(dqsize-1 downto 0);
dq2_o <= hssi.dsramso(rwri.use_ahb).dataout2((2*dqsize)-1 downto dqsize);
end if;
end process;
---- CLK270, Drives output enable signal
--oeclk : process(rst, clk270)
-- begin
-- if rst = '0' then
-- hsso.ddsi.dq_dqs_oe <= '1';
-- elsif rising_edge(clk270) then
-- hsso.ddsi.dq_dqs_oe <= rwri.dq_dqs_oe;
-- end if;
-- end process;
-- CLK0, Drives control signals
cmdclk : process(clk0)
begin
if rising_edge(clk0) then
hsso.ddsi.control <= rwri.set_cmd;
hsso.ddsi.adr <= rwri.set_adr((adrbits-3) downto 0);
hsso.ddsi.ba <= rwri.set_adr((adrbits-1) downto (adrbits-2));
hsso.ddsi.cs <= rwri.set_cs;
hsso.ddsi.cke <= rwri.set_cke;
end if;
end process;
vcc <= '1';
gnd <= '0';
data_in <= hssi.ddso.dq((dqsize-1) downto 0);
hsso.ddsi.dq((dqsize-1) downto 0) <= data_out;
hsso.ddsi.dqs((strobesize-1) downto 0) <= strobe_out;
hsso.ddsi.dm((dmsize-1) downto 0) <= mask_out;
dqot : if dqsize < maxdqsize generate
hsso.ddsi.dq((maxdqsize-1) downto dqsize) <= (others => '-');
end generate;
dqsot : if strobesize < maxstrobesize generate
hsso.ddsi.dqs((maxstrobesize-1) downto strobesize) <= (others => '-');
end generate;
dmot : if dmsize <= maxdmsize generate
hsso.ddsi.dm((maxdmsize-1) downto dmsize) <= (others => '-');
end generate;
-------------------------------------------------------------------------------
-- DDR IO registers
-------------------------------------------------------------------------------
-- Input and Output DQ
dqio : for i in 0 to (dqsize-1) generate
in1 : ddr_ireg generic map( tech => tech)
port map(
Q1 => dq1_i(i),
Q2 => dq2_i(i),
C1 => clk0,
C2 => clk180,
CE => vcc, --r_ce,
D => data_in(i),
R => gnd,
S => gnd);
out1 : ddr_oreg
generic map( tech => tech)
port map(
Q => data_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => dq1_o(i),
D2 => dq2_o(i),
R => gnd,
S => gnd);
dq_tri : ddr_oreg generic map(
tech => tech)
port map(
Q => hsso.ddsi.dq_oe(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- output DQS
dqsio : for i in 0 to (strobesize-1) generate
dqso : ddr_oreg
generic map(
tech => tech)
port map(
Q => strobe_out(i),
C1 => clk270,
C2 => clk90,
CE => vcc,
D1 => dqs1_o,
D2 => dqs2_o,
R => gnd,
S => gnd);
dqso_tri : ddr_oreg
generic map(
tech => tech)
port map(
Q => hsso.ddsi.dqs_oe(i),
C1 => clk270,
C2 => clk90,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- Output DM
dmo : for i in 0 to (dmsize-1) generate
U4 : ddr_oreg
generic map(
tech => tech)
port map(
Q => mask_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce, --write_ce
D1 => dm1_o(i),
D2 => dm2_o(i),
R => gnd,
S => gnd);
end generate;
end rtl;
|
library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity ctrl1_tb is
end ctrl1_tb;
architecture TB_ARCHITECTURE of ctrl1_tb is
component MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end component;
component MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end component;
component DPATH is
port(
EN: in std_logic;
CLK: in std_logic;
OT: in operation;
OP: in operand;
RES: out operand;
ZF: out std_logic;
Stop: out std_logic
);
end component;
-- Component declaration of the tested unit
component ctrl1
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Start : in STD_LOGIC;
Stop : out STD_LOGIC;
ROM_re : out STD_LOGIC;
ROM_addr : out mem_addr;
ROM_dout : in command;
RAM_rw : out STD_LOGIC;
RAM_addr : out mem_addr;
RAM_din : out operand;
RAM_dout : in operand;
DP_op : out operand;
DP_ot : out operation;
DP_en : out STD_LOGIC;
DP_res : in operand;
DP_zf : in STD_LOGIC;
DP_stop : in STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal Start : STD_LOGIC;
signal ROM_dout : command;
signal RAM_dout : operand;
signal DP_res : operand;
signal DP_zf : STD_LOGIC;
signal DP_stop : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal Stop : STD_LOGIC;
signal ROM_re : STD_LOGIC;
signal ROM_addr : mem_addr;
signal RAM_rw : STD_LOGIC;
signal RAM_addr : mem_addr;
signal RAM_din : operand;
signal DP_op : operand;
signal DP_ot : operation;
signal DP_en : STD_LOGIC;
constant CLK_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : ctrl1
port map (
CLK => CLK,
RST => RST,
Start => Start,
Stop => Stop,
ROM_re => ROM_re,
ROM_addr => ROM_addr,
ROM_dout => ROM_dout,
RAM_rw => RAM_rw,
RAM_addr => RAM_addr,
RAM_din => RAM_din,
RAM_dout => RAM_dout,
DP_op => DP_op,
DP_ot => DP_ot,
DP_en => DP_en,
DP_res => DP_res,
DP_zf => DP_zf,
DP_stop => DP_stop
);
UMRAM: MRAM
port map(
CLK => CLK,
RW => ram_rw,
ADDR => ram_addr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Stack)
port map (
RE => rom_re,
ADDR => rom_addr,
DOUT => rom_dout
);
UDPATH: DPATH
port map(
EN => dp_en,
CLK => CLK,
OT => dp_ot,
OP => dp_op,
RES => dp_res,
ZF => dp_zf,
STOP => dp_stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
rst <= '1';
wait for 1 * CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ctrl1 of ctrl1_tb is
for TB_ARCHITECTURE
for UUT : ctrl1
use entity work.ctrl1(beh_stack);
end for;
end for;
end TESTBENCH_FOR_ctrl1;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : case expression generate
end generate;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : DS18b20 Reader Package
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-14
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.onewire_pkg.all;
package ds18b20_pkg is
type ds18b20_out_type is record
value : std_logic_vector(15 downto 0);
update : std_logic;
err : std_logic;
end record;
type ds18b20_in_type is record
refresh : std_logic;
end record;
component ds18b20
port (
ow_out : in onewire_out_type;
ow_in : out onewire_in_type;
ds18b20_in : in ds18b20_in_type;
ds18b20_out : out ds18b20_out_type;
clk : in std_logic);
end component;
end ds18b20_pkg;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver: Wishbone bus cycle decoder. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/24 19:25:03 gedra
-- Added data output.
--
-- Revision 1.1 2004/06/23 18:09:57 gedra
-- Wishbone bus cycle decoder.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_wb_decoder is
generic (DATA_WIDTH: integer;
ADDR_WIDTH: integer);
port (
wb_clk_i: in std_logic; -- wishbone clock
wb_rst_i: in std_logic; -- reset signal
wb_sel_i: in std_logic; -- select input
wb_stb_i: in std_logic; -- strobe input
wb_we_i: in std_logic; -- write enable
wb_cyc_i: in std_logic; -- cycle input
wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
wb_ack_o: out std_logic; -- acknowledge
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
version_rd: out std_logic; -- Version register read
config_rd: out std_logic; -- Config register read
config_wr: out std_logic; -- Config register write
status_rd: out std_logic; -- Status register read
intmask_rd: out std_logic; -- Interrupt mask register read
intmask_wr: out std_logic; -- Interrupt mask register write
intstat_rd: out std_logic; -- Interrupt status register read
intstat_wr: out std_logic; -- Interrupt status register read
mem_rd: out std_logic; -- Sample memory read
mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
end rx_wb_decoder;
architecture rtl of rx_wb_decoder is
constant REG_RXVERSION : std_logic_vector(6 downto 0) := "0000000";
constant REG_RXCONFIG : std_logic_vector(6 downto 0) := "0000001";
constant REG_RXSTATUS : std_logic_vector(6 downto 0) := "0000010";
constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
signal iack, iwr, ird : std_logic;
signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
wb_ack_o <= iack;
-- acknowledge generation
ACK: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
iack <= '0';
elsif rising_edge(wb_clk_i) then
if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then
case wb_cti_i is
when "010" => -- incrementing burst
case wb_bte_i is -- burst extension
when "00" => -- linear burst
iack <= '1';
when others => -- all other treated assert classic cycle
iack <= not iack;
end case;
when "111" => -- end of burst
iack <= not iack;
when others => -- all other treated assert classic cycle
iack <= not iack;
end case;
else
iack <= '0';
end if;
end if;
end process ACK;
-- write generation
WR: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
iwr <= '0';
elsif rising_edge(wb_clk_i) then
if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
wb_we_i = '1' then
case wb_cti_i is
when "010" => -- incrementing burst
case wb_bte_i is -- burst extension
when "00" => -- linear burst
iwr <= '1';
when others => -- all other treated assert classic cycle
iwr <= not iwr;
end case;
when "111" => -- end of burst
iwr <= not iwr;
when others => -- all other treated assert classic cycle
iwr <= not iwr;
end case;
else
iwr <= '0';
end if;
end if;
end process WR;
-- read generation
ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
wb_we_i = '0' else '0';
wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout;
DREG: process (wb_clk_i) -- clock data from registers
begin
if rising_edge(wb_clk_i) then
rdout <= data_out;
end if;
end process DREG;
-- sample memory read address. This needs special attention due to read latency
mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when
wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
SMA: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
acnt <= 0;
elsif rising_edge(wb_clk_i) then
if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
if iack = '0' then
if wb_adr_i = all_ones then
acnt <= 0;
else
acnt <= to_integer(unsigned(wb_adr_i)) + 1;
end if;
else
if acnt < 2**(ADDR_WIDTH - 1) - 1 then
acnt <= acnt + 1;
else
acnt <= 0;
end if;
end if;
end if;
end if;
end process SMA;
-- read and write strobe generation
version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
else '0';
config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
else '0';
config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
else '0';
status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
else '0';
intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
else '0';
intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
else '0';
intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
else '0';
intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
else '0';
mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
-- capture register strobes
CR32: if DATA_WIDTH = 32 generate
CRST: for k in 0 to 7 generate
ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
else '0';
end generate CRST;
end generate CR32;
CR16: if DATA_WIDTH = 16 generate
ch_st_cap_rd(7 downto 0) <= (others => '0');
ch_st_cap_wr(7 downto 0) <= (others => '0');
ch_st_data_rd(7 downto 0) <= (others => '0');
end generate CR16;
end rtl;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE spi_slave_pkg IS
COMPONENT spi_slave IS
GENERIC(
TRANSFER_WIDTH : INTEGER := 32;
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_trig : OUT STD_LOGIC;
isl_sclk : IN STD_LOGIC;
isl_ss : IN STD_LOGIC;
isl_mosi : IN STD_LOGIC;
osl_miso : OUT STD_LOGIC
);
END COMPONENT spi_slave;
END PACKAGE spi_slave_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.spi_slave_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY spi_slave IS
GENERIC(
TRANSFER_WIDTH : INTEGER := 32;
CPOL: STD_LOGIC := '0'; -- clock polarity: 0 = The inactive state of SCK is logic zero, 1 = The inactive state of SCK is logic one.
CPHA: STD_LOGIC := '0'; -- clock phase 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK
-- the leading edge is always the first edge! If cpol = 0 the leading edge is a rising edge. If cpol = 1 the leading edge is a falling edge.
-- the trailing edge is always the second edge! If cpol = 0 the trailing edge is a falling edge. If cpol = 1 the training edge is a rising edge.
SSPOL: STD_LOGIC := '0' -- slave select 0 = slave select zero active. 1 = slave select one active.
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_tx_data : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
oslv_rx_data : OUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
osl_rx_trig : OUT STD_LOGIC;
isl_sclk : IN STD_LOGIC;
isl_ss : IN STD_LOGIC;
isl_mosi : IN STD_LOGIC;
osl_miso : OUT STD_LOGIC
);
END ENTITY spi_slave;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF spi_slave IS
TYPE t_states IS (idle,run,wait_for_rearm);
TYPE t_internal_register IS RECORD
state :t_states;
-- synchronize signals
sync_sclk_1 : STD_LOGIC;
sync_sclk_2 : STD_LOGIC;
sync_sclk_3 : STD_LOGIC;
sync_ss_1 : STD_LOGIC;
sync_ss_2 : STD_LOGIC;
sync_mosi_1 : STD_LOGIC;
sync_mosi_2 : STD_LOGIC;
bit_count : UNSIGNED(6 DOWNTO 0); --Allows a maximum transfer size of 127bit
rx_trig : STD_LOGIC;
rx_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
tx_buf : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
miso : STD_LOGIC;
rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_sclk,isl_ss,isl_mosi,islv_tx_data)
VARIABLE vi: t_internal_register;
PROCEDURE capture_data IS
BEGIN
vi.rx_buf(to_integer(vi.bit_count)) := vi.sync_mosi_2;
END capture_data;
PROCEDURE change_data IS
BEGIN
vi.miso := vi.tx_buf(to_integer(vi.bit_count));
END change_data;
BEGIN
-- keep variables stable
vi:=ri;
-- synchronisation
vi.sync_sclk_1 := isl_sclk;
vi.sync_sclk_2 := ri.sync_sclk_1;
vi.sync_sclk_3 := ri.sync_sclk_2;
vi.sync_ss_1 := isl_ss;
vi.sync_ss_2 := ri.sync_ss_1;
vi.sync_mosi_1 := isl_mosi;
vi.sync_mosi_2 := ri.sync_mosi_1;
--standard values:
vi.rx_trig := '0';
CASE vi.state IS
WHEN idle =>
IF(vi.sync_ss_2 = SSPOL) THEN
vi.state := run;
vi.bit_count := to_unsigned(TRANSFER_WIDTH-1,7);
vi.rx_buf := (OTHERS => '0');
vi.tx_buf := islv_tx_data;
END IF;
WHEN run =>
IF vi.sync_sclk_3 /= vi.sync_sclk_2 THEN --sclk edge
IF vi.sync_sclk_3 = CPOL THEN --leading edge
IF CPHA = '0' THEN
capture_data;
ELSE
change_data;
END IF;
ELSE -- trailing edge
IF CPHA = '0' THEN
change_data;
ELSE
capture_data;
END IF;
IF vi.bit_count = to_unsigned(0,7) THEN
vi.state := wait_for_rearm;
vi.rx_data := vi.rx_buf;
vi.rx_trig := '1';
END IF;
vi.bit_count := vi.bit_count - 1;
END IF;
END IF;
WHEN wait_for_rearm =>
IF(vi.sync_ss_2 /= SSPOL) THEN
vi.state := idle;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset signal
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.bit_count := (OTHERS => '0');
vi.rx_buf := (OTHERS => '0');
vi.tx_buf := (OTHERS => '0');
vi.miso := '0';
vi.rx_data := (OTHERS => '0');
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_rx_trig <= ri.rx_trig;
osl_miso <= ri.miso;
oslv_rx_data <= ri.rx_data;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
|
library verilog;
use verilog.vl_types.all;
entity Servo is
generic(
CLK_FREQUENCY : integer := 50000000;
VALUE_SCALING : integer := 256;
CTR_LEN : integer := 21;
SPEED_DATA_LEN : integer := 5;
POSITION_DATA_LEN: integer := 8;
ADDR_LEN : integer := 8;
MAX_RAM_POS : integer := 256;
DATA_LEN : integer := 13
);
port(
clk : in vl_logic;
rst : in vl_logic;
data : in vl_logic_vector;
address : out vl_logic_vector;
servo_q : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of CLK_FREQUENCY : constant is 1;
attribute mti_svvh_generic_type of VALUE_SCALING : constant is 1;
attribute mti_svvh_generic_type of CTR_LEN : constant is 1;
attribute mti_svvh_generic_type of SPEED_DATA_LEN : constant is 1;
attribute mti_svvh_generic_type of POSITION_DATA_LEN : constant is 1;
attribute mti_svvh_generic_type of ADDR_LEN : constant is 1;
attribute mti_svvh_generic_type of MAX_RAM_POS : constant is 1;
attribute mti_svvh_generic_type of DATA_LEN : constant is 1;
end Servo;
|
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