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-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc678.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:00 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:31 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:39 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00678ent IS END c03s04b01x00p23n01i00678ent; ARCHITECTURE c03s04b01x00p23n01i00678arch OF c03s04b01x00p23n01i00678ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. type WORD is array(0 to 31) of BIT; type FT is file of WORD; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.50"; -- Declare a variable into which we will read. constant CON : WORD := B"11111111111111111111111111111111"; variable VAR : WORD; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00678" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00678 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00678arch;
library verilog; use verilog.vl_types.all; entity xorGate is port( busXOR : out vl_logic_vector(31 downto 0); busA : in vl_logic_vector(31 downto 0); busB : in vl_logic_vector(31 downto 0); zXOR : out vl_logic; oXOR : out vl_logic; cXOR : out vl_logic; nXOR : out vl_logic ); end xorGate;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:24:54 06/03/2016 -- Design Name: -- Module Name: /home/inmcm/Dev/speck/MUX_SYNCHRONIZER_TB.vhd -- Project Name: speck -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: MUX_SYNCHRONIZER -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY MUX_SYNCHRONIZER_TB IS END MUX_SYNCHRONIZER_TB; ARCHITECTURE behavior OF MUX_SYNCHRONIZER_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MUX_SYNCHRONIZER PORT( CLK_A : IN std_logic; CLK_B : IN std_logic; RST : IN std_logic; DATA_BUS_A_IN : IN std_logic_vector(127 downto 0); DATA_BUS_B_OUT : OUT std_logic_vector(127 downto 0) ); END COMPONENT; --Inputs signal CLK_A : std_logic := '0'; signal CLK_B : std_logic := '0'; signal RST : std_logic := '0'; signal DATA_BUS_A_IN : std_logic_vector(127 downto 0) := (others => '0'); --Outputs signal DATA_BUS_B_OUT_1 : std_logic_vector(127 downto 0); signal DATA_BUS_B_OUT_2 : std_logic_vector(127 downto 0); -- Clock period definitions constant CLK_A_period : time := 20 ns; constant CLK_B_period : time := 3500 ps; BEGIN -- Instantiate the Unit Under Test (UUT) uut_1: MUX_SYNCHRONIZER PORT MAP ( CLK_A => CLK_A, CLK_B => CLK_B, RST => RST, DATA_BUS_A_IN => DATA_BUS_A_IN, DATA_BUS_B_OUT => DATA_BUS_B_OUT_1 ); -- Instantiate the Unit Under Test (UUT) uut_2: MUX_SYNCHRONIZER PORT MAP ( CLK_A => CLK_B, CLK_B => CLK_A, RST => RST, DATA_BUS_A_IN => DATA_BUS_A_IN, DATA_BUS_B_OUT => DATA_BUS_B_OUT_2 ); -- Clock process definitions CLK_A_process :process begin CLK_A <= '0'; wait for CLK_A_period/2; CLK_A <= '1'; wait for CLK_A_period/2; end process; CLK_B_process :process begin CLK_B <= '0'; wait for CLK_B_period/2; CLK_B <= '1'; wait for CLK_B_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 400 ns; DATA_BUS_A_IN <= X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; wait for CLK_A_period*10; RST <= '1'; wait for CLK_A_period*10; DATA_BUS_A_IN <= X"123456789ABCDEF00FEDCBA987654321"; wait for CLK_A_period*10; RST <= '0'; wait for CLK_A_period*50; DATA_BUS_A_IN <= X"CACACACACACACACACACACACACACACACA"; wait for CLK_A_period*50; -- insert stimulus here wait; end process; END;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008, 2009, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: iu3 -- File: iu3.vhd -- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research -- Description: LEON3 7-stage integer pipline ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; use grlib.sparc.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.leon3.all; use gaisler.libiu.all; use gaisler.arith.all; -- pragma translate_off use grlib.sparc_disas.all; -- pragma translate_on entity iu3 is generic ( nwin : integer range 2 to 32 := 8; isets : integer range 1 to 4 := 2; dsets : integer range 1 to 4 := 2; fpu : integer range 0 to 15 := 0; v8 : integer range 0 to 63 := 2; cp, mac : integer range 0 to 1 := 0; dsu : integer range 0 to 1 := 1; nwp : integer range 0 to 4 := 2; pclow : integer range 0 to 2 := 2; notag : integer range 0 to 1 := 0; index : integer range 0 to 15:= 0; lddel : integer range 1 to 2 := 1; irfwt : integer range 0 to 1 := 0; disas : integer range 0 to 2 := 0; tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer) pwd : integer range 0 to 2 := 0; -- power-down svt : integer range 0 to 1 := 0; -- single-vector trapping rstaddr : integer := 16#00000#; -- reset vector MSB address smp : integer range 0 to 15 := 0; -- support SMP systems fabtech : integer range 0 to NTECH := 20; clk2x : integer := 0 ); port ( clk : in std_ulogic; rstn : in std_ulogic; holdn : in std_ulogic; ici : buffer icache_in_type; ico : in icache_out_type; dci : buffer dcache_in_type; dco : in dcache_out_type; rfi : buffer iregfile_in_type; rfo : in iregfile_out_type; irqi : in l3_irq_in_type; irqo : buffer l3_irq_out_type; dbgi : in l3_debug_in_type; dbgo : buffer l3_debug_out_type; muli : buffer mul32_in_type; mulo : in mul32_out_type; divi : buffer div32_in_type; divo : in div32_out_type; fpo : in fpc_out_type; fpi : buffer fpc_in_type; cpo : in fpc_out_type; cpi : buffer fpc_in_type; tbo : in tracebuf_out_type; tbi : buffer tracebuf_in_type; sclk : in std_ulogic ); end; architecture rtl of iu3 is constant ISETMSB : integer := 0; constant DSETMSB : integer := 0; constant RFBITS : integer range 6 to 10 := 8; constant NWINLOG2 : integer range 1 to 5 := 3; constant CWPOPT : boolean := true; constant CWPMIN : std_logic_vector(2 downto 0) := "000"; constant CWPMAX : std_logic_vector(2 downto 0) := "111"; constant FPEN : boolean := (fpu /= 0); constant CPEN : boolean := false; constant MULEN : boolean := true; constant MULTYPE: integer := 0; constant DIVEN : boolean := true; constant MACEN : boolean := false; constant MACPIPE: boolean := false; constant IMPL : integer := 15; constant VER : integer := 3; constant DBGUNIT : boolean := true; constant TRACEBUF : boolean := true; constant TBUFBITS : integer := 7; constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0); constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0); constant RS1OPT : boolean := true; constant DYNRST : boolean := false; subtype word is std_logic_vector(31 downto 0); subtype pctype is std_logic_vector(31 downto 2); subtype rfatype is std_logic_vector(8-1 downto 0); subtype cwptype is std_logic_vector(3-1 downto 0); type icdtype is array (0 to 2-1) of word; type dcdtype is array (0 to 2-1) of word; type dc_in_type is record signed, enaddr, read, write, lock , dsuen : std_ulogic; size : std_logic_vector(1 downto 0); asi : std_logic_vector(7 downto 0); end record; type pipeline_ctrl_type is record pc : pctype; inst : word; cnt : std_logic_vector(1 downto 0); rd : rfatype; tt : std_logic_vector(5 downto 0); trap : std_ulogic; annul : std_ulogic; wreg : std_ulogic; wicc : std_ulogic; wy : std_ulogic; ld : std_ulogic; pv : std_ulogic; rett : std_ulogic; end record; type fetch_reg_type is record pc : pctype; branch : std_ulogic; end record; type decode_reg_type is record pc : pctype; inst : icdtype; cwp : cwptype; set : std_logic_vector(0 downto 0); mexc : std_ulogic; cnt : std_logic_vector(1 downto 0); pv : std_ulogic; annul : std_ulogic; inull : std_ulogic; step : std_ulogic; end record; type regacc_reg_type is record ctrl : pipeline_ctrl_type; rs1 : std_logic_vector(4 downto 0); rfa1, rfa2 : rfatype; rsel1, rsel2 : std_logic_vector(2 downto 0); rfe1, rfe2 : std_ulogic; cwp : cwptype; imm : word; ldcheck1 : std_ulogic; ldcheck2 : std_ulogic; ldchkra : std_ulogic; ldchkex : std_ulogic; su : std_ulogic; et : std_ulogic; wovf : std_ulogic; wunf : std_ulogic; ticc : std_ulogic; jmpl : std_ulogic; step : std_ulogic; mulstart : std_ulogic; divstart : std_ulogic; end record; type execute_reg_type is record ctrl : pipeline_ctrl_type; op1 : word; op2 : word; aluop : std_logic_vector(2 downto 0); -- Alu operation alusel : std_logic_vector(1 downto 0); -- Alu result select aluadd : std_ulogic; alucin : std_ulogic; ldbp1, ldbp2 : std_ulogic; invop2 : std_ulogic; shcnt : std_logic_vector(4 downto 0); -- shift count sari : std_ulogic; -- shift msb shleft : std_ulogic; -- shift left/right ymsb : std_ulogic; -- shift left/right rd : std_logic_vector(4 downto 0); jmpl : std_ulogic; su : std_ulogic; et : std_ulogic; cwp : cwptype; icc : std_logic_vector(3 downto 0); mulstep: std_ulogic; mul : std_ulogic; mac : std_ulogic; end record; type memory_reg_type is record ctrl : pipeline_ctrl_type; result : word; y : word; icc : std_logic_vector(3 downto 0); nalign : std_ulogic; dci : dc_in_type; werr : std_ulogic; wcwp : std_ulogic; irqen : std_ulogic; irqen2 : std_ulogic; mac : std_ulogic; divz : std_ulogic; su : std_ulogic; mul : std_ulogic; end record; type exception_state is (run, trap, dsu1, dsu2); type exception_reg_type is record ctrl : pipeline_ctrl_type; result : word; y : word; icc : std_logic_vector( 3 downto 0); annul_all : std_ulogic; data : dcdtype; set : std_logic_vector(0 downto 0); mexc : std_ulogic; dci : dc_in_type; laddr : std_logic_vector(1 downto 0); rstate : exception_state; npc : std_logic_vector(2 downto 0); intack : std_ulogic; ipend : std_ulogic; mac : std_ulogic; debug : std_ulogic; nerror : std_ulogic; end record; type dsu_registers is record tt : std_logic_vector(7 downto 0); err : std_ulogic; tbufcnt : std_logic_vector(7-1 downto 0); asi : std_logic_vector(7 downto 0); crdy : std_logic_vector(2 downto 1); -- diag cache access ready end record; type irestart_register is record addr : pctype; pwd : std_ulogic; end record; type pwd_register_type is record pwd : std_ulogic; error : std_ulogic; end record; type special_register_type is record cwp : cwptype; -- current window pointer icc : std_logic_vector(3 downto 0); -- integer condition codes tt : std_logic_vector(7 downto 0); -- trap type tba : std_logic_vector(19 downto 0); -- trap base address wim : std_logic_vector(8-1 downto 0); -- window invalid mask pil : std_logic_vector(3 downto 0); -- processor interrupt level ec : std_ulogic; -- enable CP ef : std_ulogic; -- enable FP ps : std_ulogic; -- previous supervisor flag s : std_ulogic; -- supervisor flag et : std_ulogic; -- enable traps y : word; asr18 : word; svt : std_ulogic; -- enable traps dwt : std_ulogic; -- disable write error trap end record; type write_reg_type is record s : special_register_type; result : word; wa : rfatype; wreg : std_ulogic; except : std_ulogic; end record; type registers is record f : fetch_reg_type; d : decode_reg_type; a : regacc_reg_type; e : execute_reg_type; m : memory_reg_type; x : exception_reg_type; w : write_reg_type; end record; type exception_type is record pri : std_ulogic; ill : std_ulogic; fpdis : std_ulogic; cpdis : std_ulogic; wovf : std_ulogic; wunf : std_ulogic; ticc : std_ulogic; end record; type watchpoint_register is record addr : std_logic_vector(31 downto 2); -- watchpoint address mask : std_logic_vector(31 downto 2); -- watchpoint mask exec : std_ulogic; -- trap on instruction load : std_ulogic; -- trap on load store : std_ulogic; -- trap on store end record; type watchpoint_registers is array (0 to 3) of watchpoint_register; constant wpr_none : watchpoint_register := ( "000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0'); function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is variable dmode : std_ulogic; begin dmode := '0'; if (not r.x.ctrl.annul and trap) = '1' then if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or ((dbgi.bsoft = '1') and (tt = "10000001")) or (dbgi.btrapa = '1') or ((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or (tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or (tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or (((not r.w.s.et) and dbgi.berror) = '1')) then dmode := '1'; end if; end if; return(dmode); end; function dbgerr(r : registers; dbgi : l3_debug_in_type; tt : std_logic_vector(7 downto 0)) return std_ulogic is variable err : std_ulogic; begin err := not r.w.s.et; if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or ((dbgi.bsoft = '1') and (tt = ("10000001")))) then err := '0'; end if; return(err); end; procedure diagwr(r : in registers; dsur : in dsu_registers; ir : in irestart_register; dbg : in l3_debug_in_type; wpr : in watchpoint_registers; s : out special_register_type; vwpr : out watchpoint_registers; asi : out std_logic_vector(7 downto 0); pc, npc : out pctype; tbufcnt : out std_logic_vector(7-1 downto 0); wr : out std_ulogic; addr : out std_logic_vector(9 downto 0); data : out word; fpcwr : out std_ulogic) is variable i : integer range 0 to 3; begin s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0'; vwpr := wpr; asi := dsur.asi; addr := "0000000000"; data := dbg.ddata; tbufcnt := dsur.tbufcnt; fpcwr := '0'; if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then case dbg.daddr(23 downto 20) is when "0001" => if (dbg.daddr(16) = '1') and true then -- trace buffer control reg tbufcnt := dbg.ddata(7-1 downto 0); end if; when "0011" => -- IU reg file if dbg.daddr(12) = '0' then wr := '1'; addr := "0000000000"; addr(8-1 downto 0) := dbg.daddr(8+1 downto 2); else -- FPC fpcwr := '1'; end if; when "0100" => -- IU special registers case dbg.daddr(7 downto 6) is when "00" => -- IU regs Y - TBUF ctrl reg case dbg.daddr(5 downto 2) is when "0000" => -- Y s.y := dbg.ddata; when "0001" => -- PSR s.cwp := dbg.ddata(3-1 downto 0); s.icc := dbg.ddata(23 downto 20); s.ec := dbg.ddata(13); if FPEN then s.ef := dbg.ddata(12); end if; s.pil := dbg.ddata(11 downto 8); s.s := dbg.ddata(7); s.ps := dbg.ddata(6); s.et := dbg.ddata(5); when "0010" => -- WIM s.wim := dbg.ddata(8-1 downto 0); when "0011" => -- TBR s.tba := dbg.ddata(31 downto 12); s.tt := dbg.ddata(11 downto 4); when "0100" => -- PC pc := dbg.ddata(31 downto 2); when "0101" => -- NPC npc := dbg.ddata(31 downto 2); when "0110" => --FSR fpcwr := '1'; when "0111" => --CFSR when "1001" => -- ASI reg asi := dbg.ddata(7 downto 0); --when "1001" => -- TBUF ctrl reg -- tbufcnt := dbg.ddata(7-1 downto 0); when others => end case; when "01" => -- ASR16 - ASR31 case dbg.daddr(5 downto 2) is when "0001" => -- %ASR17 s.dwt := dbg.ddata(14); s.svt := dbg.ddata(13); when "0010" => -- %ASR18 if false then s.asr18 := dbg.ddata; end if; when "1000" => -- %ASR24 - %ASR31 vwpr(0).addr := dbg.ddata(31 downto 2); vwpr(0).exec := dbg.ddata(0); when "1001" => vwpr(0).mask := dbg.ddata(31 downto 2); vwpr(0).load := dbg.ddata(1); vwpr(0).store := dbg.ddata(0); when "1010" => vwpr(1).addr := dbg.ddata(31 downto 2); vwpr(1).exec := dbg.ddata(0); when "1011" => vwpr(1).mask := dbg.ddata(31 downto 2); vwpr(1).load := dbg.ddata(1); vwpr(1).store := dbg.ddata(0); when "1100" => vwpr(2).addr := dbg.ddata(31 downto 2); vwpr(2).exec := dbg.ddata(0); when "1101" => vwpr(2).mask := dbg.ddata(31 downto 2); vwpr(2).load := dbg.ddata(1); vwpr(2).store := dbg.ddata(0); when "1110" => vwpr(3).addr := dbg.ddata(31 downto 2); vwpr(3).exec := dbg.ddata(0); when "1111" => -- vwpr(3).mask := dbg.ddata(31 downto 2); vwpr(3).load := dbg.ddata(1); vwpr(3).store := dbg.ddata(0); when others => -- end case; -- disabled due to bug in XST -- i := conv_integer(dbg.daddr(4 downto 3)); -- if dbg.daddr(2) = '0' then -- vwpr(i).addr := dbg.ddata(31 downto 2); -- vwpr(i).exec := dbg.ddata(0); -- else -- vwpr(i).mask := dbg.ddata(31 downto 2); -- vwpr(i).load := dbg.ddata(1); -- vwpr(i).store := dbg.ddata(0); -- end if; when others => end case; when others => end case; end if; end; function asr17_gen ( r : in registers) return word is variable asr17 : word; variable fpu2 : integer range 0 to 3; begin asr17 := "00000000000000000000000000000000"; asr17(31 downto 28) := conv_std_logic_vector(index, 4); if (clk2x > 8) then asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2); asr17(17) := '1'; elsif (clk2x > 0) then asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2); end if; asr17(14) := r.w.s.dwt; if svt = 1 then asr17(13) := r.w.s.svt; end if; if lddel = 2 then asr17(12) := '1'; end if; if (fpu > 0) and (fpu < 8) then fpu2 := 1; elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3; elsif fpu = 15 then fpu2 := 2; else fpu2 := 0; end if; asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2); if mac = 1 then asr17(9) := '1'; end if; if 2 /= 0 then asr17(8) := '1'; end if; asr17(7 downto 5) := conv_std_logic_vector(nwp, 3); asr17(4 downto 0) := conv_std_logic_vector(8-1, 5); return(asr17); end; procedure diagread(dbgi : in l3_debug_in_type; r : in registers; dsur : in dsu_registers; ir : in irestart_register; wpr : in watchpoint_registers; dco : in dcache_out_type; tbufo : in tracebuf_out_type; data : out word) is variable cwp : std_logic_vector(4 downto 0); variable rd : std_logic_vector(4 downto 0); variable i : integer range 0 to 3; begin data := "00000000000000000000000000000000"; cwp := "00000"; cwp(3-1 downto 0) := r.w.s.cwp; case dbgi.daddr(22 downto 20) is when "001" => -- trace buffer if true then if dbgi.daddr(16) = '1' then -- trace buffer control reg if true then data(7-1 downto 0) := dsur.tbufcnt; end if; else case dbgi.daddr(3 downto 2) is when "00" => data := tbufo.data(127 downto 96); when "01" => data := tbufo.data(95 downto 64); when "10" => data := tbufo.data(63 downto 32); when others => data := tbufo.data(31 downto 0); end case; end if; end if; when "011" => -- IU reg file if dbgi.daddr(12) = '0' then data := rfo.data1(31 downto 0); if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then data := rfo.data2(31 downto 0); end if; else data := fpo.dbg.data; end if; when "100" => -- IU regs case dbgi.daddr(7 downto 6) is when "00" => -- IU regs Y - TBUF ctrl reg case dbgi.daddr(5 downto 2) is when "0000" => data := r.w.s.y; when "0001" => data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp; when "0010" => data(8-1 downto 0) := r.w.s.wim; when "0011" => data := r.w.s.tba & r.w.s.tt & "0000"; when "0100" => data(31 downto 2) := r.f.pc; when "0101" => data(31 downto 2) := ir.addr; when "0110" => -- FSR data := fpo.dbg.data; when "0111" => -- CPSR when "1000" => -- TT reg data(12 downto 4) := dsur.err & dsur.tt; when "1001" => -- ASI reg data(7 downto 0) := dsur.asi; when others => end case; when "01" => if dbgi.daddr(5) = '0' then -- %ASR17 if dbgi.daddr(4 downto 2) = "001" then -- %ASR17 data := asr17_gen(r); elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18 data := r.w.s.asr18; end if; else -- %ASR24 - %ASR31 i := conv_integer(dbgi.daddr(4 downto 3)); -- if dbgi.daddr(2) = '0' then data(31 downto 2) := wpr(i).addr; data(0) := wpr(i).exec; else data(31 downto 2) := wpr(i).mask; data(1) := wpr(i).load; data(0) := wpr(i).store; end if; end if; when others => end case; when "111" => data := r.x.data(conv_integer(r.x.set)); when others => end case; end; procedure itrace(r : in registers; dsur : in dsu_registers; vdsu : in dsu_registers; res : in word; exc : in std_ulogic; dbgi : in l3_debug_in_type; error : in std_ulogic; trap : in std_ulogic; tbufcnt : out std_logic_vector(7-1 downto 0); di : out tracebuf_in_type) is variable meminst : std_ulogic; begin di.addr := (others => '0'); di.data := (others => '0'); di.enable := '0'; di.write := (others => '0'); tbufcnt := vdsu.tbufcnt; meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30); if true then di.addr(7-1 downto 0) := dsur.tbufcnt; di.data(127) := '0'; di.data(126) := not r.x.ctrl.pv; di.data(125 downto 96) := dbgi.timer(29 downto 0); di.data(95 downto 64) := res; di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2); di.data(33) := trap; di.data(32) := error; di.data(31 downto 0) := r.x.ctrl.inst; if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then di.enable := '1'; di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4); if dbgi.dwrite = '1' then case dbgi.daddr(3 downto 2) is when "00" => di.write(3) := '1'; when "01" => di.write(2) := '1'; when "10" => di.write(1) := '1'; when others => di.write(0) := '1'; end case; di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata; end if; end if; elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then di.enable := '1'; di.write := (others => '1'); tbufcnt := dsur.tbufcnt + 1; end if; di.diag := dco.testen & "000"; if dco.scanen = '1' then di.enable := '0'; end if; end if; end; procedure dbg_cache(holdn : in std_ulogic; dbgi : in l3_debug_in_type; r : in registers; dsur : in dsu_registers; mresult : in word; dci : in dc_in_type; mresult2 : out word; dci2 : out dc_in_type ) is begin mresult2 := mresult; dci2 := dci; dci2.dsuen := '0'; if true then if r.x.rstate = dsu2 then dci2.asi := dsur.asi; if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2); dci2.enaddr := dbgi.denable; dci2.size := "10"; dci2.read := '1'; dci2.write := '0'; if (dbgi.denable and not r.m.dci.enaddr) = '1' then mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2); else mresult2 := dbgi.ddata; end if; if dbgi.dwrite = '1' then dci2.read := '0'; dci2.write := '1'; end if; end if; end if; end if; end; procedure fpexack(r : in registers; fpexc : out std_ulogic) is begin fpexc := '0'; if FPEN then if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if; end if; end; procedure diagrdy(denable : in std_ulogic; dsur : in dsu_registers; dci : in dc_in_type; mds : in std_ulogic; ico : in icache_out_type; crdy : out std_logic_vector(2 downto 1)) is begin crdy := dsur.crdy(1) & '0'; if dci.dsuen = '1' then case dsur.asi(4 downto 0) is when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST => crdy(2) := ico.diagrdy and not dsur.crdy(2); when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA => crdy(1) := not denable and dci.enaddr and not dsur.crdy(1); when others => crdy(2) := dci.enaddr and denable; end case; end if; end; signal r, rin : registers; signal wpr, wprin : watchpoint_registers; signal dsur, dsuin : dsu_registers; signal ir, irin : irestart_register; signal rp, rpin : pwd_register_type; -- execute stage operations constant EXE_AND : std_logic_vector(2 downto 0) := "000"; constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2 constant EXE_OR : std_logic_vector(2 downto 0) := "010"; constant EXE_XNOR : std_logic_vector(2 downto 0) := "011"; constant EXE_ANDN : std_logic_vector(2 downto 0) := "100"; constant EXE_ORN : std_logic_vector(2 downto 0) := "101"; constant EXE_DIV : std_logic_vector(2 downto 0) := "110"; constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000"; constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001"; constant EXE_STB : std_logic_vector(2 downto 0) := "010"; constant EXE_STH : std_logic_vector(2 downto 0) := "011"; constant EXE_ONES : std_logic_vector(2 downto 0) := "100"; constant EXE_RDY : std_logic_vector(2 downto 0) := "101"; constant EXE_SPR : std_logic_vector(2 downto 0) := "110"; constant EXE_LINK : std_logic_vector(2 downto 0) := "111"; constant EXE_SLL : std_logic_vector(2 downto 0) := "001"; constant EXE_SRL : std_logic_vector(2 downto 0) := "010"; constant EXE_SRA : std_logic_vector(2 downto 0) := "100"; constant EXE_NOP : std_logic_vector(2 downto 0) := "000"; -- EXE result select constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00"; constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01"; constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10"; constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11"; -- Load types constant SZBYTE : std_logic_vector(1 downto 0) := "00"; constant SZHALF : std_logic_vector(1 downto 0) := "01"; constant SZWORD : std_logic_vector(1 downto 0) := "10"; constant SZDBL : std_logic_vector(1 downto 0) := "11"; -- calculate register file address procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0); rao : out rfatype) is variable ra : rfatype; constant globals : std_logic_vector(8-5 downto 0) := conv_std_logic_vector(8, 8-4); begin ra := (others => '0'); ra(4 downto 0) := reg; if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals; else ra(3+3 downto 4) := cwp + ra(4); if ra(8-1 downto 4) = globals then ra(8-1 downto 4) := (others => '0'); end if; end if; rao := ra; end; -- branch adder function branch_address(inst : word; pc : pctype) return std_logic_vector is variable baddr, caddr, tmp : pctype; begin caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0); caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2); baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21)); baddr(23 downto 2) := inst(21 downto 0); baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2); if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if; return(tmp); end; -- evaluate branch condition function branch_true(icc : std_logic_vector(3 downto 0); inst : word) return std_ulogic is variable n, z, v, c, branch : std_ulogic; begin n := icc(3); z := icc(2); v := icc(1); c := icc(0); case inst(27 downto 25) is when "000" => branch := inst(28) xor '0'; -- bn, ba when "001" => branch := inst(28) xor z; -- be, bne when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg when "011" => branch := inst(28) xor (n xor v); -- bl, bge when "100" => branch := inst(28) xor (c or z); -- bleu, bgu when "101" => branch := inst(28) xor c; -- bcs, bcc when "110" => branch := inst(28) xor n; -- bneg, bpos when others => branch := inst(28) xor v; -- bvs, bvc end case; return(branch); end; -- detect RETT instruction in the pipeline and set the local psr.su and psr.et procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic; su, et : out std_ulogic) is begin if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1') and (r.x.annul_all = '0') then su := xc_ps; et := '1'; else su := xc_s; et := xc_et; end if; end; -- detect watchpoint trap function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type) return std_ulogic is variable exc : std_ulogic; begin exc := '0'; for i in 1 to NWP loop if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then exc := '1'; end if; end if; end loop; if true then if (debug.dsuen and not r.a.ctrl.annul) = '1' then exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step)); end if; end if; return(exc); end; -- 32-bit shifter function shift3(r : registers; aluin1, aluin2 : word) return word is variable shiftin : unsigned(63 downto 0); variable shiftout : unsigned(63 downto 0); variable cnt : natural range 0 to 31; begin cnt := conv_integer(r.e.shcnt); if r.e.shleft = '1' then shiftin(30 downto 0) := (others => '0'); shiftin(63 downto 31) := '0' & unsigned(aluin1); else shiftin(63 downto 32) := (others => r.e.sari); shiftin(31 downto 0) := unsigned(aluin1); end if; shiftout := SHIFT_RIGHT(shiftin, cnt); return(std_logic_vector(shiftout(31 downto 0))); end; function shift2(r : registers; aluin1, aluin2 : word) return word is variable ushiftin : unsigned(31 downto 0); variable sshiftin : signed(32 downto 0); variable cnt : natural range 0 to 31; variable resleft, resright : word; begin cnt := conv_integer(r.e.shcnt); ushiftin := unsigned(aluin1); sshiftin := signed('0' & aluin1); if r.e.shleft = '1' then resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt)); return(resleft); else if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if; sshiftin := SHIFT_RIGHT(sshiftin, cnt); resright := std_logic_vector(sshiftin(31 downto 0)); return(resright); -- else -- ushiftin := SHIFT_RIGHT(ushiftin, cnt); -- return(std_logic_vector(ushiftin)); -- end if; end if; end; function shift(r : registers; aluin1, aluin2 : word; shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is variable shiftin : std_logic_vector(63 downto 0); begin shiftin := "00000000000000000000000000000000" & aluin1; if r.e.shleft = '1' then shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1; else shiftin(63 downto 32) := (others => sari); end if; if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if; if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if; if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if; if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if; if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if; return(shiftin(31 downto 0)); end; -- Check for illegal and privileged instructions procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type; trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0); trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is variable illegal_inst, privileged_inst : std_ulogic; variable cp_disabled, fp_disabled, fpop : std_ulogic; variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable rd : std_logic_vector(4 downto 0); variable inst : word; variable wph : std_ulogic; begin inst := r.a.ctrl.inst; trap := trapin; tt := ttin; if r.a.ctrl.annul = '0' then op := inst(31 downto 30); op2 := inst(24 downto 22); op3 := inst(24 downto 19); rd := inst(29 downto 25); illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0'; fp_disabled := '0'; fpop := '0'; case op is when CALL => null; when FMT2 => case op2 is when SETHI | BICC => null; when FBFCC => if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if; when CBCCC => if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if; when others => illegal_inst := '1'; end case; when FMT3 => case op3 is when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY => null; when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV => if notag = 1 then illegal_inst := '1'; end if; when UMAC | SMAC => if not false then illegal_inst := '1'; end if; when UMUL | SMUL | UMULCC | SMULCC => if not true then illegal_inst := '1'; end if; when UDIV | SDIV | UDIVCC | SDIVCC => if not true then illegal_inst := '1'; end if; when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su; when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su; when WRY => null; when WRPSR => privileged_inst := not r.a.su; when WRWIM | WRTBR => privileged_inst := not r.a.su; when FPOP1 | FPOP2 => if FPEN then fp_disabled := not r.w.s.ef; fpop := '1'; else fp_disabled := '1'; fpop := '0'; end if; when CPOP1 | CPOP2 => if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if; when others => illegal_inst := '1'; end case; when others => -- LDST case op3 is when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP => null; when LDDA | STDA => illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su; when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA => illegal_inst := inst(13); privileged_inst := not r.a.su; when LDDF | STDF | LDF | LDFSR | STF | STFSR => if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if; when STDFQ => privileged_inst := not r.a.su; if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if; when STDCQ => privileged_inst := not r.a.su; if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if; when LDC | LDCSR | LDDC | STC | STCSR | STDC => if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if; when others => illegal_inst := '1'; end case; end case; wph := wphit(r, wpr, dbgi); trap := '1'; if r.a.ctrl.trap = '1' then tt := TT_IAEX; elsif privileged_inst = '1' then tt := TT_PRIV; elsif illegal_inst = '1' then tt := TT_IINST; elsif fp_disabled = '1' then tt := TT_FPDIS; elsif cp_disabled = '1' then tt := TT_CPDIS; elsif wph = '1' then tt := TT_WATCH; elsif r.a.wovf= '1' then tt := TT_WINOF; elsif r.a.wunf= '1' then tt := TT_WINUF; elsif r.a.ticc= '1' then tt := TT_TICC; else trap := '0'; tt:= (others => '0'); end if; end if; end; -- instructions that write the condition codes (psr.icc) procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is begin wicc := '0'; wy := '0'; if inst(31 downto 30) = FMT3 then case inst(24 downto 19) is when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR => wicc := '1'; when WRY => if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if; when MULSCC => wicc := '1'; wy := '1'; when UMAC | SMAC => if false then wy := '1'; end if; when UMULCC | SMULCC => if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then wicc := '1'; wy := '1'; end if; when UMUL | SMUL => if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then wy := '1'; end if; when UDIVCC | SDIVCC => if true and (divo.nready = '1') and (r.d.cnt /= "00") then wicc := '1'; end if; when others => end case; end if; end; -- select cwp procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype; cwp : out cwptype) is begin if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp; elsif (wcwp = '1') and (annul = '0') then cwp := ncwp; elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0); else cwp := r.d.cwp; end if; end; -- generate wcwp in ex stage procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is begin if (r.e.ctrl.inst(31 downto 30) = FMT3) and (r.e.ctrl.inst(24 downto 19) = WRPSR) then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if; end; -- generate next cwp & window under- and overflow traps procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0); inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable wim : word; variable ncwp : cwptype; begin op := inst(31 downto 30); op3 := inst(24 downto 19); wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0'); wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0'; if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then wcwp := '1'; if (op3 = SAVE) then if (not true) and (r.d.cwp = "000") then ncwp := "111"; else ncwp := r.d.cwp - 1 ; end if; else if (not true) and (r.d.cwp = "111") then ncwp := "000"; else ncwp := r.d.cwp + 1; end if; end if; if wim(conv_integer(ncwp)) = '1' then if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if; end if; end if; de_cwp := ncwp; end; -- generate register read address 1 procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0); rs1mod : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); begin op := inst(31 downto 30); op3 := inst(24 downto 19); rs1 := inst(18 downto 14); rs1mod := '0'; if (op = LDST) then if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or (r.d.cnt = "10") then rs1mod := '1'; rs1 := inst(29 downto 25); end if; if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then rs1(0) := '1'; end if; end if; end; -- load/icc interlock detection procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0); rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic; lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable cond : std_logic_vector(3 downto 0); variable rs1 : std_logic_vector(4 downto 0); variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic; variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic; variable lddlock : boolean; begin op := inst(31 downto 30); op3 := inst(24 downto 19); op2 := inst(24 downto 22); cond := inst(28 downto 25); rs1 := inst(18 downto 14); lddlock := false; i := inst(13); ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0'; ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0'; y_check := '0'; if (r.d.annul = '0') then case op is when FMT2 => if (op2 = BICC) and (cond(2 downto 0) /= "000") then icc_check := '1'; end if; when FMT3 => ldcheck1 := '1'; ldcheck2 := not i; case op3 is when TICC => if (cond(2 downto 0) /= "000") then icc_check := '1'; end if; when RDY => ldcheck1 := '0'; ldcheck2 := '0'; if false then y_check := '1'; end if; when RDWIM | RDTBR => ldcheck1 := '0'; ldcheck2 := '0'; when RDPSR => ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1'; if true then icc_check := '1'; end if; -- when ADDX | ADDXCC | SUBX | SUBXCC => -- if true then icc_check := '1'; end if; when SDIV | SDIVCC | UDIV | UDIVCC => if true then y_check := '1'; end if; when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; when others => end case; when LDST => ldcheck1 := '1'; ldchkra := '0'; case r.d.cnt is when "00" => if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if; ldcheck2 := not i; ldchkra := '1'; when "01" => ldcheck2 := not i; when others => ldchkex := '0'; end case; if (op3(2 downto 0) = "011") then lddlock := true; end if; when others => null; end case; end if; if true or true then chkmul := mulinsn; bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul)); else chkmul := '0'; end if; if true then bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy)); chkmul := chkmul or divinsn; end if; bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc)); if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and (((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or ((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or ((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd))) then ldlock := '1'; end if; if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and ((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and (((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or ((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2))) then ldlock := '1'; end if; ldlock := ldlock or bicc_hold or fpc_lock; lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock; lldchkra := ldchkra; lldchkex := ldchkex; end; procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0); branch : out std_ulogic) is variable cond : std_logic_vector(3 downto 0); variable fbres : std_ulogic; begin cond := inst(28 downto 25); case cond(2 downto 0) is when "000" => fbres := '0'; -- fba, fbn when "001" => fbres := fcc(1) or fcc(0); when "010" => fbres := fcc(1) xor fcc(0); when "011" => fbres := fcc(0); when "100" => fbres := (not fcc(1)) and fcc(0); when "101" => fbres := fcc(1); when "110" => fbres := fcc(1) and not fcc(0); when others => fbres := fcc(1) and fcc(0); end case; branch := cond(3) xor fbres; end; -- PC generation procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true, fbranch_true, cbranch_true, fccv, cccv : in std_ulogic; cnt : out std_logic_vector(1 downto 0); de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull, de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart, divstart : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable cond : std_logic_vector(3 downto 0); variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic; variable de_jmpl : std_ulogic; begin branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1'; hold_pc := '0'; ticc_exception := '0'; rett_inst := '0'; op := inst(31 downto 30); op3 := inst(24 downto 19); op2 := inst(24 downto 22); cond := inst(28 downto 25); annul := inst(29); de_jmpl := '0'; cnt := "00"; mulstart := '0'; divstart := '0'; if r.d.annul = '0' then case inst(31 downto 30) is when CALL => branch := '1'; if r.d.inull = '1' then hold_pc := '1'; annul_current := '1'; end if; when FMT2 => if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then if (FPEN and (op2 = FBFCC)) then branch := fbranch_true; if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if; elsif (false and (op2 = CBCCC)) then branch := cbranch_true; if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if; else branch := branch_true; end if; if hold_pc = '0' then if (branch = '1') then if (cond = BA) and (annul = '1') then annul_next := '1'; end if; else annul_next := annul; end if; if r.d.inull = '1' then -- contention with JMPL hold_pc := '1'; annul_current := '1'; annul_next := '0'; end if; end if; end if; when FMT3 => case op3 is when UMUL | SMUL | UMULCC | SMULCC => if true and (0 /= 0) then mulstart := '1'; end if; if true and (0 = 0) then case r.d.cnt is when "00" => cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1'; when "01" => if mulo.nready = '1' then cnt := "00"; else cnt := "01"; pv := '0'; hold_pc := '1'; end if; when others => null; end case; end if; when UDIV | SDIV | UDIVCC | SDIVCC => if true then case r.d.cnt is when "00" => cnt := "01"; hold_pc := '1'; pv := '0'; divstart := '1'; when "01" => if divo.nready = '1' then cnt := "00"; else cnt := "01"; pv := '0'; hold_pc := '1'; end if; when others => null; end case; end if; when TICC => if branch_true = '1' then ticc_exception := '1'; end if; when RETT => rett_inst := '1'; --su := sregs.ps; when JMPL => de_jmpl := '1'; when WRY => if false then if inst(29 downto 25) = "10011" then -- %ASR19 case r.d.cnt is when "00" => pv := '0'; cnt := "00"; hold_pc := '1'; if r.x.ipend = '1' then cnt := "01"; end if; when "01" => cnt := "00"; when others => end case; end if; end if; when others => null; end case; when others => -- LDST case r.d.cnt is when "00" => if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD cnt := "01"; hold_pc := '1'; pv := '0'; end if; when "01" => if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or ((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110")) then -- LDD/STD/LDSTUB/SWAP cnt := "10"; pv := '0'; hold_pc := '1'; else cnt := "00"; end if; when "10" => cnt := "00"; when others => null; end case; end case; end if; if ldlock = '1' then cnt := r.d.cnt; annul_next := '0'; pv := '1'; end if; hold_pc := (hold_pc or ldlock) and not annul_all; if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if; annul_current := (annul_current or ldlock or annul_all); ctrl_annul := r.d.annul or annul_all or annul_current; pv := pv and not ((r.d.inull and not hold_pc) or annul_all); jmpl_inst := de_jmpl and not annul_current; annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all; if (annul_next = '1') or (rstn = '0') then cnt := (others => '0'); end if; de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next; de_pv := pv; ctrl_pv := r.d.pv and not ((r.d.annul and not r.d.pv) or annul_all or annul_current); inull := (not rstn) or r.d.inull or hold_pc or annul_all; end; -- register write address generation procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic; rdo : out std_logic_vector(4 downto 0)) is variable write_reg : std_ulogic; variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable rd : std_logic_vector(4 downto 0); begin op := inst(31 downto 30); op2 := inst(24 downto 22); op3 := inst(24 downto 19); write_reg := '0'; rd := inst(29 downto 25); ld := '0'; case op is when CALL => write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7) when FMT2 => if (op2 = SETHI) then write_reg := '1'; end if; when FMT3 => case op3 is when UMUL | SMUL | UMULCC | SMULCC => if true then if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then write_reg := '1'; end if; else write_reg := '1'; end if; when UDIV | SDIV | UDIVCC | SDIVCC => if true then if (divo.nready = '1') and (r.d.cnt /= "00") then write_reg := '1'; end if; else write_reg := '1'; end if; when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null; when FPOP1 | FPOP2 => null; when CPOP1 | CPOP2 => null; when others => write_reg := '1'; end case; when others => -- LDST ld := not op3(2); if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1')) then write_reg := '1'; end if; case op3 is when SWAP | SWAPA | LDSTUB | LDSTUBA => if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if; when others => null; end case; if r.d.cnt = "01" then case op3 is when LDD | LDDA | LDDC | LDDF => rd(0) := '1'; when others => end case; end if; end case; if (rd = "00000") then write_reg := '0'; end if; wreg := write_reg; rdo := rd; end; -- immediate data generation function imm_data (r : registers; insn : word) return word is variable immediate_data, inst : word; begin immediate_data := (others => '0'); inst := insn; case inst(31 downto 30) is when FMT2 => immediate_data := inst(21 downto 0) & "0000000000"; when others => -- LDST immediate_data(31 downto 13) := (others => inst(12)); immediate_data(12 downto 0) := inst(12 downto 0); end case; return(immediate_data); end; -- read special registers function get_spr (r : registers) return word is variable spr : word; begin spr := (others => '0'); case r.e.ctrl.inst(24 downto 19) is when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) & conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et; spr(3-1 downto 0) := r.e.cwp; when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt; when RDWIM => spr(8-1 downto 0) := r.w.s.wim; when others => end case; return(spr); end; -- immediate data select function imm_select(inst : word) return boolean is variable imm : boolean; begin imm := false; case inst(31 downto 30) is when FMT2 => case inst(24 downto 22) is when SETHI => imm := true; when others => end case; when FMT3 => case inst(24 downto 19) is when RDWIM | RDPSR | RDTBR => imm := true; when others => if (inst(13) = '1') then imm := true; end if; end case; when LDST => if (inst(13) = '1') then imm := true; end if; when others => end case; return(imm); end; -- EXE operation procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0); my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0); alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic; shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb, mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable rd : std_logic_vector(4 downto 0); variable icc : std_logic_vector(3 downto 0); variable y0 : std_ulogic; begin op := r.a.ctrl.inst(31 downto 30); op2 := r.a.ctrl.inst(24 downto 22); op3 := r.a.ctrl.inst(24 downto 19); aop1 := iop1; aop2 := iop2; ldbp2 := ldbp; aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1'; shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0'; ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0'; macins := '0'; if r.e.ctrl.wy = '1' then y0 := my; elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0); elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0); else y0 := r.w.s.y(0); end if; if r.e.ctrl.wicc = '1' then icc := me_icc; elsif r.m.ctrl.wicc = '1' then icc := r.m.icc; elsif r.x.ctrl.wicc = '1' then icc := r.x.icc; else icc := r.w.s.icc; end if; case op is when CALL => aluop := EXE_LINK; when FMT2 => case op2 is when SETHI => aluop := EXE_PASS2; when others => end case; when FMT3 => case op3 is when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT => alusel := EXE_RES_ADD; when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV => alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1'; when MULSCC => alusel := EXE_RES_ADD; aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1); if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if; mulstep := '1'; when UMUL | UMULCC | SMUL | SMULCC => if true then mulins := '1'; end if; when UMAC | SMAC => if false then mulins := '1'; macins := '1'; end if; when UDIV | UDIVCC | SDIV | SDIVCC => if true then aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1'; end if; when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC; when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC; when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC; when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC; when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC; when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY => aluop := EXE_XOR; alusel := EXE_RES_LOGIC; when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR; when RDY => aluop := EXE_RDY; when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1'; shcnt := not iop2(4 downto 0); invop2 := '1'; when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT; when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31); when FPOP1 | FPOP2 => when others => end case; when others => -- LDST case r.a.ctrl.cnt is when "00" => alusel := EXE_RES_ADD; when "01" => case op3 is when LDD | LDDA | LDDC => alusel := EXE_RES_ADD; when LDDF => alusel := EXE_RES_ADD; when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD; when STF | STDF => when others => aluop := EXE_PASS1; if op3(2) = '1' then if op3(1 downto 0) = "01" then aluop := EXE_STB; elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if; end if; end case; when "10" => aluop := EXE_PASS1; if op3(2) = '1' then -- ST if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A end if; when others => end case; end case; end; function ra_inull_gen(r, v : registers) return std_ulogic is variable de_inull : std_ulogic; begin de_inull := '0'; if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if; if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if; return(de_inull); end; -- operand generation procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word; rsel : in std_logic_vector(2 downto 0); ldbp : out std_ulogic; d : out word) is begin ldbp := '0'; case rsel is when "000" => d := rfd; when "001" => d := ed; when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if; when "011" => d := xd; when "100" => d := im; when "101" => d := (others => '0'); when "110" => d := r.w.result; when others => d := (others => '-'); end case; end; procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic; rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic; osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is begin rfe := '0'; if im then osel := "100"; elsif rs1 = "00000" then osel := "101"; -- %g0 elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001"; elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010"; elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011"; elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110"; else osel := "000"; rfe := ldcheck; end if; end; -- generate carry-in for alu procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable ncin : std_ulogic; begin op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19); if r.e.ctrl.wicc = '1' then ncin := me_cin; else ncin := r.m.icc(0); end if; cin := '0'; case op is when FMT3 => case op3 is when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1'; when ADDX | ADDXCC => cin := ncin; when SUBX | SUBXCC => cin := not ncin; when others => null; end case; when others => null; end case; end; procedure logic_op(r : registers; aluin1, aluin2, mey : word; ymsb : std_ulogic; logicres, y : out word) is variable logicout : word; begin case r.e.aluop is when EXE_AND => logicout := aluin1 and aluin2; when EXE_ANDN => logicout := aluin1 and not aluin2; when EXE_OR => logicout := aluin1 or aluin2; when EXE_ORN => logicout := aluin1 or not aluin2; when EXE_XOR => logicout := aluin1 xor aluin2; when EXE_XNOR => logicout := aluin1 xor not aluin2; when EXE_DIV => if true then logicout := aluin2; else logicout := (others => '-'); end if; when others => logicout := (others => '-'); end case; if (r.e.ctrl.wy and r.e.mulstep) = '1' then y := ymsb & r.m.y(31 downto 1); elsif r.e.ctrl.wy = '1' then y := logicout; elsif r.m.ctrl.wy = '1' then y := mey; elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32); elsif r.x.ctrl.wy = '1' then y := r.x.y; else y := r.w.s.y; end if; logicres := logicout; end; procedure misc_op(r : registers; wpr : watchpoint_registers; aluin1, aluin2, ldata, mey : word; mout, edata : out word) is variable miscout, bpdata, stdata : word; variable wpi : integer; begin wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00"; edata := aluin1; bpdata := aluin1; if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and (r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and (r.e.ctrl.cnt /= "10") then bpdata := ldata; end if; case r.e.aluop is when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) & bpdata(7 downto 0) & bpdata(7 downto 0); edata := miscout; when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0); edata := miscout; when EXE_PASS1 => miscout := bpdata; edata := miscout; when EXE_PASS2 => miscout := aluin2; when EXE_ONES => miscout := (others => '1'); edata := miscout; when EXE_RDY => if true and (r.m.ctrl.wy = '1') then miscout := mey; else miscout := r.m.y; end if; if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then wpi := conv_integer(r.e.ctrl.inst(16 downto 15)); if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec; else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if; end if; if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17 miscout := asr17_gen(r); end if; if false then if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18 if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then miscout := mulo.result(31 downto 0); -- data forward of asr18 else miscout := r.w.s.asr18; end if; else if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then miscout := mulo.result(63 downto 32); -- data forward Y end if; end if; end if; when EXE_SPR => miscout := get_spr(r); when others => null; end case; mout := miscout; end; procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0); op1, op2 : word; shiftout, logicout, miscout : word; res : out word; me_icc : std_logic_vector(3 downto 0); icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable icc : std_logic_vector(3 downto 0); variable aluresult : word; begin op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19); icc := (others => '0'); case r.e.alusel is when EXE_RES_ADD => aluresult := addout(32 downto 1); if r.e.aluadd = '0' then icc(0) := ((not op1(31)) and not op2(31)) or -- Carry (addout(32) and ((not op1(31)) or not op2(31))); icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow (addout(32) and (not op1(31)) and not op2(31)); else icc(0) := (op1(31) and op2(31)) or -- Carry ((not addout(32)) and (op1(31) or op2(31))); icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow (addout(32) and (not op1(31)) and (not op2(31))); end if; if notag = 0 then case op is when FMT3 => case op3 is when TADDCC | TADDCCTV => icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1); when TSUBCC | TSUBCCTV => icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1); when others => null; end case; when others => null; end case; end if; if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if; when EXE_RES_SHIFT => aluresult := shiftout; when EXE_RES_LOGIC => aluresult := logicout; if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if; when others => aluresult := miscout; end case; if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if; icc(3) := aluresult(31); divz := icc(2); if r.e.ctrl.wicc = '1' then if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20); else icco := icc; end if; elsif r.m.ctrl.wicc = '1' then icco := me_icc; elsif r.x.ctrl.wicc = '1' then icco := r.x.icc; else icco := r.w.s.icc; end if; res := aluresult; end; procedure dcache_gen(r, v : registers; dci : out dc_in_type; link_pc, jump, force_a2, load : out std_ulogic) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable su : std_ulogic; begin op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19); dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD; if op = LDST then case op3 is when LDUB | LDUBA => dci.size := SZBYTE; when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1'; when LDUH | LDUHA => dci.size := SZHALF; when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1'; when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1'; when LD | LDA | LDF | LDC => dci.size := SZWORD; when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1'; when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL; when STB | STBA => dci.size := SZBYTE; when STH | STHA => dci.size := SZHALF; when ST | STA | STF => dci.size := SZWORD; when ISTD | STDA => dci.size := SZDBL; when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if; when STDC | STDCQ => if false then dci.size := SZDBL; end if; when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0'; end case; end if; link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0'; dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2); -- load/store control decoding if (r.e.ctrl.annul = '0') then case op is when CALL => link_pc := '1'; when FMT3 => case op3 is when JMPL => jump := '1'; link_pc := '1'; when RETT => jump := '1'; when others => null; end case; when LDST => case r.e.ctrl.cnt is when "00" => dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP load := op3(3) or not op3(2); dci.enaddr := '1'; when "01" => force_a2 := not op3(2); -- LDD load := not op3(2); dci.enaddr := not op3(2); if op3(3 downto 2) = "01" then -- ST/STD dci.write := '1'; end if; if op3(3 downto 2) = "11" then -- LDST/SWAP dci.enaddr := '1'; end if; when "10" => -- STD/LDST/SWAP dci.write := '1'; when others => null; end case; if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then dci.enaddr := '0'; end if; when others => null; end case; end if; if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps; else su := r.w.s.s; end if; if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if; if (op3(4) = '1') and ((op3(5) = '0') or not false) then dci.asi := r.e.ctrl.inst(12 downto 5); end if; end; procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0); edata2, eres2 : out word) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); begin edata2 := edata; eres2 := eres; op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19); if FPEN then if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then edata2 := fpstdata; eres2 := fpstdata; end if; end if; end; function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0); size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is variable align_data, rdata : word; begin align_data := data(conv_integer(set)); rdata := (others => '0'); case size is when "00" => -- byte read case laddr is when "00" => rdata(7 downto 0) := align_data(31 downto 24); if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if; when "01" => rdata(7 downto 0) := align_data(23 downto 16); if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if; when "10" => rdata(7 downto 0) := align_data(15 downto 8); if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if; when others => rdata(7 downto 0) := align_data(7 downto 0); if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if; end case; when "01" => -- half-word read if laddr(1) = '1' then rdata(15 downto 0) := align_data(15 downto 0); if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if; else rdata(15 downto 0) := align_data(31 downto 16); if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if; end if; when others => -- single and double word read rdata := align_data; end case; return(rdata); end; procedure mem_trap(r : registers; wpr : watchpoint_registers; annul, holdn : in std_ulogic; trapout, iflush, nullify, werrout : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is variable cwp : std_logic_vector(3-1 downto 0); variable cwpx : std_logic_vector(5 downto 3); variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable nalign_d : std_ulogic; variable trap, werr : std_ulogic; begin op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22); op3 := r.m.ctrl.inst(24 downto 19); cwpx := r.m.result(5 downto 3); cwpx(5) := '0'; iflush := '0'; trap := r.m.ctrl.trap; nullify := annul; tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt; nalign_d := r.m.nalign or r.m.result(2); if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then if (werr and holdn) = '1' then trap := '1'; tt := TT_DSEX; werr := '0'; if op = LDST then nullify := '1'; end if; end if; end if; if ((annul or trap) /= '1') then case op is when FMT2 => case op2 is when FBFCC => if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if; when CBCCC => if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if; when others => null; end case; when FMT3 => case op3 is when WRPSR => if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if; when UDIV | SDIV | UDIVCC | SDIVCC => if true then if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if; end if; when JMPL | RETT => if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if; when TADDCCTV | TSUBCCTV => if (notag = 0) and (r.m.icc(1) = '1') then trap := '1'; tt := TT_TAG; end if; when FLUSH => iflush := '1'; when FPOP1 | FPOP2 => if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if; when CPOP1 | CPOP2 => if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if; when others => null; end case; when LDST => if r.m.ctrl.cnt = "00" then case op3 is when LDDF | STDF | STDFQ => if FPEN then if nalign_d = '1' then trap := '1'; tt := TT_UNALA; nullify := '1'; elsif (fpo.exc and r.m.ctrl.pv) = '1' then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if; end if; when LDDC | STDC | STDCQ => if false then if nalign_d = '1' then trap := '1'; tt := TT_UNALA; nullify := '1'; elsif ((cpo.exc and r.m.ctrl.pv) = '1') then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if; end if; when LDD | ISTD | LDDA | STDA => if r.m.result(2 downto 0) /= "000" then trap := '1'; tt := TT_UNALA; nullify := '1'; end if; when LDF | LDFSR | STFSR | STF => if FPEN and (r.m.nalign = '1') then trap := '1'; tt := TT_UNALA; nullify := '1'; elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1') then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if; when LDC | LDCSR | STCSR | STC => if false and (r.m.nalign = '1') then trap := '1'; tt := TT_UNALA; nullify := '1'; elsif false and ((cpo.exc and r.m.ctrl.pv) = '1') then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if; when LD | LDA | ST | STA | SWAP | SWAPA => if r.m.result(1 downto 0) /= "00" then trap := '1'; tt := TT_UNALA; nullify := '1'; end if; when LDUH | LDUHA | LDSH | LDSHA | STH | STHA => if r.m.result(0) /= '0' then trap := '1'; tt := TT_UNALA; nullify := '1'; end if; when others => null; end case; for i in 1 to NWP loop if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and (((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000")) then trap := '1'; tt := TT_WATCH; nullify := '1'; end if; end loop; end if; when others => null; end case; end if; if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if; trapout := trap; werrout := werr; end; procedure irq_trap(r : in registers; ir : in irestart_register; irl : in std_logic_vector(3 downto 0); annul : in std_ulogic; pv : in std_ulogic; trap : in std_ulogic; tt : in std_logic_vector(5 downto 0); nullify : in std_ulogic; irqen : out std_ulogic; irqen2 : out std_ulogic; nullify2 : out std_ulogic; trap2, ipend : out std_ulogic; tt2 : out std_logic_vector(5 downto 0)) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable pend : std_ulogic; begin nullify2 := nullify; trap2 := trap; tt2 := tt; op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19); irqen := '1'; irqen2 := r.m.irqen; if (annul or trap) = '0' then if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if; end if; if (irl = "1111") or (irl > r.w.s.pil) then pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd; else pend := '0'; end if; ipend := pend; if ((not annul) and pv and (not trap) and pend) = '1' then trap2 := '1'; tt2 := "01" & irl; if op = LDST then nullify2 := '1'; end if; end if; end; procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is begin intack := '0'; if r.x.rstate = trap then if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if; end if; end; -- write special registers procedure sp_write (r : registers; wpr : watchpoint_registers; s : out special_register_type; vwpr : out watchpoint_registers) is variable op : std_logic_vector(1 downto 0); variable op2 : std_logic_vector(2 downto 0); variable op3 : std_logic_vector(5 downto 0); variable rd : std_logic_vector(4 downto 0); variable i : integer range 0 to 3; begin op := r.x.ctrl.inst(31 downto 30); op2 := r.x.ctrl.inst(24 downto 22); op3 := r.x.ctrl.inst(24 downto 19); s := r.w.s; rd := r.x.ctrl.inst(29 downto 25); vwpr := wpr; case op is when FMT3 => case op3 is when WRY => if rd = "00000" then s.y := r.x.result; elsif false and (rd = "10010") then s.asr18 := r.x.result; elsif (rd = "10001") then s.dwt := r.x.result(14); if (svt = 1) then s.svt := r.x.result(13); end if; elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31 case rd(2 downto 0) is when "000" => vwpr(0).addr := r.x.result(31 downto 2); vwpr(0).exec := r.x.result(0); when "001" => vwpr(0).mask := r.x.result(31 downto 2); vwpr(0).load := r.x.result(1); vwpr(0).store := r.x.result(0); when "010" => vwpr(1).addr := r.x.result(31 downto 2); vwpr(1).exec := r.x.result(0); when "011" => vwpr(1).mask := r.x.result(31 downto 2); vwpr(1).load := r.x.result(1); vwpr(1).store := r.x.result(0); when "100" => vwpr(2).addr := r.x.result(31 downto 2); vwpr(2).exec := r.x.result(0); when "101" => vwpr(2).mask := r.x.result(31 downto 2); vwpr(2).load := r.x.result(1); vwpr(2).store := r.x.result(0); when "110" => vwpr(3).addr := r.x.result(31 downto 2); vwpr(3).exec := r.x.result(0); when others => -- "111" vwpr(3).mask := r.x.result(31 downto 2); vwpr(3).load := r.x.result(1); vwpr(3).store := r.x.result(0); end case; end if; when WRPSR => s.cwp := r.x.result(3-1 downto 0); s.icc := r.x.result(23 downto 20); s.ec := r.x.result(13); if FPEN then s.ef := r.x.result(12); end if; s.pil := r.x.result(11 downto 8); s.s := r.x.result(7); s.ps := r.x.result(6); s.et := r.x.result(5); when WRWIM => s.wim := r.x.result(8-1 downto 0); when WRTBR => s.tba := r.x.result(31 downto 12); when SAVE => if (not true) and (r.w.s.cwp = "000") then s.cwp := "111"; else s.cwp := r.w.s.cwp - 1 ; end if; when RESTORE => if (not true) and (r.w.s.cwp = "111") then s.cwp := "000"; else s.cwp := r.w.s.cwp + 1; end if; when RETT => if (not true) and (r.w.s.cwp = "111") then s.cwp := "000"; else s.cwp := r.w.s.cwp + 1; end if; s.s := r.w.s.ps; s.et := '1'; when others => null; end case; when others => null; end case; if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if; if r.x.ctrl.wy = '1' then s.y := r.x.y; end if; if false and (r.x.mac = '1') then s.asr18 := mulo.result(31 downto 0); s.y := mulo.result(63 downto 32); end if; end; function npc_find (r : registers) return std_logic_vector is variable npc : std_logic_vector(2 downto 0); begin npc := "011"; if r.m.ctrl.pv = '1' then npc := "000"; elsif r.e.ctrl.pv = '1' then npc := "001"; elsif r.a.ctrl.pv = '1' then npc := "010"; elsif r.d.pv = '1' then npc := "011"; elsif 2 /= 0 then npc := "100"; end if; return(npc); end; function npc_gen (r : registers) return word is variable npc : std_logic_vector(31 downto 0); begin npc := r.a.ctrl.pc(31 downto 2) & "00"; case r.x.npc is when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2); when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2); when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2); when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2); when others => if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if; end case; return(npc); end; procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word; icc : out std_logic_vector(3 downto 0)) is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); begin op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19); result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in; case op is when FMT3 => case op3 is when UMUL | SMUL => if true then result := mulo.result(31 downto 0); y := mulo.result(63 downto 32); end if; when UMULCC | SMULCC => if true then result := mulo.result(31 downto 0); icc := mulo.icc; y := mulo.result(63 downto 32); end if; when UMAC | SMAC => if false and not false then result := mulo.result(31 downto 0); asr18 := mulo.result(31 downto 0); y := mulo.result(63 downto 32); end if; when UDIV | SDIV => if true then result := divo.result(31 downto 0); end if; when UDIVCC | SDIVCC => if true then result := divo.result(31 downto 0); icc := divo.icc; end if; when others => null; end case; when others => null; end case; end; function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is variable op : std_logic_vector(1 downto 0); variable op3 : std_logic_vector(5 downto 0); variable rd : std_logic_vector(4 downto 0); variable pd : std_ulogic; begin op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19); rd := r.x.ctrl.inst(29 downto 25); pd := '0'; if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if; pd := pd or rp.pwd; end if; return(pd); end; signal dummy : std_ulogic; signal cpu_index : std_logic_vector(3 downto 0); signal disasen : std_ulogic; -- Signals used for tracking if a handler fired and which one signal dfp_trap_vector : std_logic_vector(3129 downto 0); signal or_reduce_1 : std_logic; signal dfp_delay_start : integer range 0 to 15; signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right); signal handlerTrap : std_ulogic; -- Signals that serve as shadow signals for variables used in the pairs signal V_A_ET_shadow : STD_ULOGIC; signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3); signal ICNT_shadow : STD_ULOGIC; signal EX_OP1_shadow : WORD; signal V_M_CTRL_PC_shadow : PCTYPE; signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal DE_REN1_shadow : STD_ULOGIC; signal DE_INST_shadow : WORD; signal V_A_CTRL_CNT_shadow : OP_TYPE; signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0); signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0); signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_E_ALUCIN_shadow : STD_ULOGIC; signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_A_CTRL_PV_shadow : STD_ULOGIC; signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE; signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE; signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0); signal EX_SHCNT_shadow : ASI_TYPE; signal V_M_DCI_SIZE_shadow : OP_TYPE; signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC; signal V_X_MEXC_shadow : STD_ULOGIC; signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0); signal V_A_CTRL_WY_shadow : STD_ULOGIC; signal NPC_shadow : PCTYPE; signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0); signal V_A_MULSTART_shadow : STD_ULOGIC; signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0); signal V_E_CTRL_TT_shadow : OP3_TYPE; signal DSIGN_shadow : STD_ULOGIC; signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC; signal EX_JUMP_ADDRESS_shadow : PCTYPE; signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_A_RFE1_shadow : STD_ULOGIC; signal V_W_WA_shadow : RFATYPE; signal V_X_ANNUL_ALL_shadow : STD_ULOGIC; signal EX_YMSB_shadow : STD_ULOGIC; signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0); signal VIR_ADDR_shadow : PCTYPE; signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_W_S_CWP_shadow : CWPTYPE; signal V_D_INST0_shadow : std_logic_vector(31 downto 0); signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC; signal V_X_DATA1_shadow : std_logic_vector(31 downto 0); signal VP_PWD_shadow : STD_ULOGIC; signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0); signal V_X_DATA00_shadow : STD_LOGIC; signal V_M_CTRL_RETT_shadow : STD_ULOGIC; signal V_X_CTRL_RETT_shadow : STD_ULOGIC; signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_W_S_PS_shadow : STD_ULOGIC; signal V_X_CTRL_TT_shadow : OP3_TYPE; signal V_D_STEP_shadow : STD_ULOGIC; signal V_X_CTRL_WICC_shadow : STD_ULOGIC; signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0); signal V_X_RESULT_shadow : WORD; signal V_D_CNT_shadow : OP_TYPE; signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0); signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3); signal V_W_S_EF_shadow : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0); signal V_X_DCI_SIGNED_shadow : STD_ULOGIC; signal V_M_NALIGN_shadow : STD_ULOGIC; signal XC_WREG_shadow : STD_ULOGIC; signal V_A_RFA2_shadow : RFATYPE; signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13); signal EX_OP231_shadow : STD_LOGIC; signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0); signal V_A_SU_shadow : STD_ULOGIC; signal V_E_OP2_shadow : WORD; signal EX_FORCE_A2_shadow : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_E_OP131_shadow : STD_LOGIC; signal V_X_DCI_shadow : DC_IN_TYPE; signal V_E_CTRL_WICC_shadow : STD_ULOGIC; signal EX_OP13_shadow : STD_LOGIC; signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_E_CTRL_INST_shadow : WORD; signal V_E_CTRL_LD_shadow : STD_ULOGIC; signal V_M_SU_shadow : STD_ULOGIC; signal V_E_SARI_shadow : STD_ULOGIC; signal V_E_ET_shadow : STD_ULOGIC; signal V_M_CTRL_PV_shadow : STD_ULOGIC; signal VDSU_CRDY2_shadow : STD_LOGIC; signal MUL_OP2_shadow : WORD; signal XC_EXCEPTION_shadow : STD_ULOGIC; signal V_E_OP1_shadow : WORD; signal VP_ERROR_shadow : STD_ULOGIC; signal V_M_DCI_SIGNED_shadow : STD_ULOGIC; signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal MUL_OP231_shadow : STD_LOGIC; signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_M_DCI_shadow : DC_IN_TYPE; signal EX_OP23_shadow : STD_LOGIC; signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0); signal V_X_CTRL_TRAP_shadow : STD_ULOGIC; signal V_A_DIVSTART_shadow : STD_ULOGIC; signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0); signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0); signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5); signal V_X_CTRL_CNT_shadow : OP_TYPE; signal V_E_YMSB_shadow : STD_ULOGIC; signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11); signal V_A_RFE2_shadow : STD_ULOGIC; signal V_E_OP13_shadow : STD_LOGIC; signal V_A_CWP_shadow : CWPTYPE; signal ME_SIZE_shadow : OP_TYPE; signal V_X_MAC_shadow : STD_ULOGIC; signal V_M_CTRL_INST_shadow : WORD; signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_A_CTRL_INST20_shadow : STD_LOGIC; signal DE_REN2_shadow : STD_ULOGIC; signal V_E_CTRL_PV_shadow : STD_ULOGIC; signal V_E_MAC_shadow : STD_ULOGIC; signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0); signal EX_ADD_RES3_shadow : STD_LOGIC; signal V_X_CTRL_INST_shadow : WORD; signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_W_S_ET_shadow : STD_ULOGIC; signal V_M_CTRL_CNT_shadow : OP_TYPE; signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC; signal DE_INST19_shadow : STD_LOGIC; signal XC_HALT_shadow : STD_ULOGIC; signal V_E_OP231_shadow : STD_LOGIC; signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_M_CTRL_WICC_shadow : STD_ULOGIC; signal V_M_CTRL_WREG_shadow : STD_ULOGIC; signal V_W_S_S_shadow : STD_ULOGIC; signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_E_CWP_shadow : CWPTYPE; signal V_A_STEP_shadow : STD_ULOGIC; signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0); signal V_A_CTRL_TRAP_shadow : STD_ULOGIC; signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_M_CTRL_TRAP_shadow : STD_ULOGIC; signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_X_INTACK_shadow : STD_ULOGIC; signal SIDLE_shadow : STD_ULOGIC; signal V_A_CTRL_RETT_shadow : STD_ULOGIC; signal V_X_DATA03_shadow : STD_LOGIC; signal V_A_CTRL_INST19_shadow : STD_LOGIC; signal V_W_S_SVT_shadow : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_X_LADDR_shadow : OP_TYPE; signal V_W_S_DWT_shadow : STD_ULOGIC; signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0); signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0); signal V_M_MUL_shadow : STD_ULOGIC; signal V_E_SU_shadow : STD_ULOGIC; signal V_M_Y31_shadow : STD_LOGIC; signal V_E_OP23_shadow : STD_LOGIC; signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0); signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_E_CTRL_TRAP_shadow : STD_ULOGIC; signal V_X_DEBUG_shadow : STD_ULOGIC; signal V_M_DCI_LOCK_shadow : STD_ULOGIC; signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_X_CTRL_WREG_shadow : STD_ULOGIC; signal V_E_CTRL_INST24_shadow : STD_LOGIC; signal V_D_MEXC_shadow : STD_ULOGIC; signal V_W_RESULT_shadow : WORD; signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC; signal EX_OP131_shadow : STD_LOGIC; signal V_D_INST1_shadow : std_logic_vector(31 downto 0); signal V_W_EXCEPT_shadow : STD_ULOGIC; signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0); signal ME_LADDR_shadow : OP_TYPE; signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_E_CTRL_RETT_shadow : STD_ULOGIC; signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0); signal V_X_CTRL_PV_shadow : STD_ULOGIC; signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0); signal V_M_MAC_shadow : STD_ULOGIC; signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0); signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_D_CWP_shadow : CWPTYPE; signal DE_INST20_shadow : STD_LOGIC; signal V_D_ANNUL_shadow : STD_ULOGIC; signal EX_OP2_shadow : WORD; signal EX_SARI_shadow : STD_ULOGIC; signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2); signal V_X_DCI_SIZE_shadow : OP_TYPE; signal V_M_Y_shadow : WORD; signal V_X_CTRL_PC_shadow : PCTYPE; signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0); signal V_A_CTRL_PC_shadow : PCTYPE; signal V_A_JMPL_shadow : STD_ULOGIC; signal V_E_CTRL_PC_shadow : PCTYPE; signal V_E_CTRL_INST20_shadow : STD_LOGIC; signal V_E_CTRL_WREG_shadow : STD_ULOGIC; signal V_A_CTRL_WREG_shadow : STD_ULOGIC; signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE; signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0); signal V_X_DATA0_shadow : std_logic_vector(31 downto 0); signal V_E_CTRL_INST19_shadow : STD_LOGIC; signal ME_SIGNED_shadow : STD_ULOGIC; signal V_W_WREG_shadow : STD_ULOGIC; signal V_D_PC_shadow : PCTYPE; signal VFPI_D_ANNUL_shadow : STD_ULOGIC; signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0); signal V_E_CTRL_CNT_shadow : OP_TYPE; signal V_F_PC_shadow : PCTYPE; signal V_X_DATA031_shadow : STD_LOGIC; signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0); signal V_M_CTRL_TT_shadow : OP3_TYPE; signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE; signal V_A_CTRL_INST24_shadow : STD_LOGIC; signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2); signal V_X_NERROR_shadow : STD_ULOGIC; signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0); signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4); signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3); signal V_F_BRANCH_shadow : STD_ULOGIC; signal V_A_CTRL_WICC_shadow : STD_ULOGIC; signal V_A_CTRL_LD_shadow : STD_ULOGIC; signal V_A_CTRL_TT_shadow : OP3_TYPE; signal V_M_CTRL_LD_shadow : STD_ULOGIC; signal V_E_SHCNT_shadow : ASI_TYPE; signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12); signal V_A_CTRL_INST_shadow : WORD; signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0); signal VIR_PWD_shadow : STD_ULOGIC; signal XC_RESULT_shadow : WORD; signal V_A_RFA1_shadow : RFATYPE; signal V_E_JMPL_shadow : STD_ULOGIC; signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0); signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0); signal DE_INST24_shadow : STD_LOGIC; signal XC_TRAP_shadow : STD_ULOGIC; signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0); signal XC_TRAP_ADDRESS_shadow : PCTYPE; -- Intermediate value holding signal declarations signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC; signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2); signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0); signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal ICO_MEXC_intermed_4 : STD_ULOGIC; signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_DATA00_intermed_2 : STD_LOGIC; signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC; signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC; signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC; signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2); signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC; signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC; signal RPIN_PWD_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12); signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0); signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0); signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2); signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC; signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0); signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4); signal RIN_D_STEP_intermed_1 : STD_ULOGIC; signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0); signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4); signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC; signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2); signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4); signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0); signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal RIN_M_Y31_intermed_1 : STD_LOGIC; signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_E_YMSB_intermed_1 : STD_ULOGIC; signal R_X_DATA031_intermed_2 : STD_LOGIC; signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC; signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0); signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2); signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0); signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2); signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2); signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12); signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5); signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0); signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC; signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12); signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC; signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC; signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0); signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0); signal RIN_A_ET_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal DBGI_STEP_intermed_1 : STD_ULOGIC; signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC; signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12); signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0); signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC; signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0); signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0); signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2); signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC; signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC; signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0); signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0); signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC; signal RIN_X_DCI_intermed_1 : DC_IN_TYPE; signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0); signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0); signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0); signal ICO_MEXC_intermed_1 : STD_ULOGIC; signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC; signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0); signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0); signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC; signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0); signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11); signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC; signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0); signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0); signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4); signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0); signal RIN_W_S_ET_intermed_1 : STD_ULOGIC; signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2); signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0); signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0); signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC; signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC; signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2); signal DCO_DATA00_intermed_2 : STD_LOGIC; signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0); signal V_E_SU_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC; signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12); signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC; signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0); signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC; signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0); signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0); signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC; signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0); signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2); signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC; signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0); signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0); signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0); signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC; signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0); signal ICO_MEXC_intermed_3 : STD_ULOGIC; signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0); signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC; signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2); signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC; signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC; signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0); signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2); signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC; signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2); signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC; signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4); signal RIN_E_OP13_intermed_1 : STD_LOGIC; signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0); signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC; signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC; signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0); signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE; signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal R_M_Y31_intermed_2 : STD_LOGIC; signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2); signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC; signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4); signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0); signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0); signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC; signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0); signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_X_DATA031_intermed_1 : STD_LOGIC; signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2); signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC; signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13); signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC; signal R_X_DATA031_intermed_1 : STD_LOGIC; signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0); signal RIN_E_SARI_intermed_1 : STD_ULOGIC; signal R_M_Y31_intermed_1 : STD_LOGIC; signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal DE_INST24_shadow_intermed_2 : STD_LOGIC; signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC; signal DE_INST20_shadow_intermed_3 : STD_LOGIC; signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0); signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC; signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0); signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2); signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0); signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0); signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0); signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC; signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0); signal V_E_OP131_shadow_intermed_1 : STD_LOGIC; signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12); signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC; signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC; signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC; signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12); signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC; signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12); signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC; signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC; signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC; signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC; signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0); signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC; signal DE_INST24_shadow_intermed_1 : STD_LOGIC; signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2); signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0); signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC; signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC; signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC; signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0); signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12); signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0); signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2); signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC; signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC; signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0); signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0); signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC; signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC; signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC; signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0); signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2); signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC; signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4); signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC; signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal RIN_X_NERROR_intermed_1 : STD_ULOGIC; signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal ICO_MEXC_intermed_5 : STD_ULOGIC; signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0); signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC; signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC; signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3); signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2); signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0); signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC; signal R_E_MAC_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0); signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC; signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC; signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC; signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE; signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC; signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC; signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC; signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0); signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0); signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2); signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal DCO_DATA031_intermed_1 : STD_LOGIC; signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC; signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC; signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0); signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC; signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0); signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC; signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0); signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal RPIN_ERROR_intermed_1 : STD_ULOGIC; signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal R_W_S_S_intermed_1 : STD_ULOGIC; signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4); signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2); signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0); signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2); signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2); signal RIN_E_SU_intermed_1 : STD_ULOGIC; signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC; signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0); signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE; signal R_D_MEXC_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC; signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC; signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC; signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC; signal RIN_W_S_PS_intermed_1 : STD_ULOGIC; signal R_D_MEXC_intermed_3 : STD_ULOGIC; signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0); signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0); signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC; signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC; signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0); signal RIN_E_OP23_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC; signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4); signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC; signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4); signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC; signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC; signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12); signal VP_PWD_shadow_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC; signal RP_ERROR_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0); signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal RIN_E_JMPL_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal V_A_SU_shadow_intermed_1 : STD_ULOGIC; signal RIN_A_RFE2_intermed_1 : STD_ULOGIC; signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0); signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC; signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2); signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0); signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0); signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC; signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC; signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC; signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0); signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2); signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC; signal RIN_X_MEXC_intermed_1 : STD_ULOGIC; signal RIN_D_MEXC_intermed_4 : STD_ULOGIC; signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2); signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0); signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC; signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0); signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0); signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC; signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0); signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0); signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC; signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0); signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC; signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC; signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2); signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC; signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE; signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC; signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0); signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC; signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC; signal DCO_DATA031_intermed_2 : STD_LOGIC; signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC; signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC; signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0); signal DE_INST24_shadow_intermed_3 : STD_LOGIC; signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0); signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0); signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE; signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0); signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC; signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4); signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC; signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC; signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0); signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0); signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2); signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal DSUR_CRDY2_intermed_1 : STD_LOGIC; signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0); signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal RIN_X_DATA031_intermed_2 : STD_LOGIC; signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0); signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal DE_INST19_shadow_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0); signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0); signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC; signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0); signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12); signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12); signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC; signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12); signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0); signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4); signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4); signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3); signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC; signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0); signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2); signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0); signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC; signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC; signal RIN_W_WREG_intermed_1 : STD_ULOGIC; signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4); signal R_D_ANNUL_intermed_1 : STD_ULOGIC; signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0); signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC; signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC; signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2); signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0); signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC; signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC; signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC; signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2); signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2); signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0); signal DSUIN_CRDY2_intermed_1 : STD_LOGIC; signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC; signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0); signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0); signal DE_INST19_shadow_intermed_3 : STD_LOGIC; signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC; signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC; signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal IRIN_PWD_intermed_1 : STD_ULOGIC; signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC; signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC; signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0); signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2); signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2); signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2); signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_X_DATA03_intermed_1 : STD_LOGIC; signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0); signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0); signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0); signal RIN_X_MAC_intermed_1 : STD_ULOGIC; signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0); signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0); signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12); signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2); signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC; signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal V_E_OP23_shadow_intermed_1 : STD_LOGIC; signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2); signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2); signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC; signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0); signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC; signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC; signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2); signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0); signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC; signal RIN_X_DATA03_intermed_2 : STD_LOGIC; signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0); signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC; signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal DE_INST19_shadow_intermed_2 : STD_LOGIC; signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC; signal RIN_D_MEXC_intermed_5 : STD_ULOGIC; signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2); signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2); signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC; signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2); signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC; signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0); signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal R_A_SU_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0); signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC; signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal RIN_A_JMPL_intermed_1 : STD_ULOGIC; signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC; signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0); signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC; signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0); signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC; signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0); signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal DSUR_CRDY2_intermed_2 : STD_LOGIC; signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0); signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0); signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal RIN_M_SU_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC; signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0); signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal RIN_X_DATA00_intermed_3 : STD_LOGIC; signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_OP131_intermed_1 : STD_LOGIC; signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0); signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC; signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0); signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2); signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC; signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE; signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC; signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2); signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal V_A_ET_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC; signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC; signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC; signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_X_DATA00_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4); signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0); signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC; signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC; signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC; signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0); signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0); signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC; signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC; signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0); signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2); signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0); signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC; signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0); signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0); signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC; signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE; signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC; signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0); signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2); signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC; signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC; signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC; signal RIN_E_MAC_intermed_1 : STD_ULOGIC; signal R_X_DATA00_intermed_2 : STD_LOGIC; signal RIN_E_MAC_intermed_2 : STD_ULOGIC; signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0); signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2); signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4); signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0); signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC; signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0); signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2); signal DE_INST20_shadow_intermed_1 : STD_LOGIC; signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0); signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12); signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4); signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0); signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC; signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0); signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC; signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC; signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal V_E_OP13_shadow_intermed_1 : STD_LOGIC; signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC; signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2); signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0); signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2); signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0); signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0); signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC; signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC; signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC; signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2); signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC; signal R_D_MEXC_intermed_2 : STD_ULOGIC; signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2); signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2); signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0); signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0); signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4); signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC; signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2); signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0); signal DE_INST20_shadow_intermed_2 : STD_LOGIC; signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0); signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0); signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC; signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12); signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12); signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0); signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal RIN_X_INTACK_intermed_1 : STD_ULOGIC; signal RIN_E_OP231_intermed_1 : STD_LOGIC; signal RIN_X_DATA031_intermed_3 : STD_LOGIC; signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4); signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC; signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_E_ET_intermed_1 : STD_ULOGIC; signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC; signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC; signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal ICO_MEXC_intermed_2 : STD_ULOGIC; signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC; signal RIN_A_STEP_intermed_1 : STD_ULOGIC; signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4); signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0); signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4); signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0); signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2); signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC; signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC; signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12); signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC; signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0); signal RIN_M_MUL_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC; signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0); signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2); signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0); signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0); signal DCO_DATA03_intermed_1 : STD_LOGIC; signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0); signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC; signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC; signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC; signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE; signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE; signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0); signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC; signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3); signal RIN_D_MEXC_intermed_1 : STD_ULOGIC; signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0); signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0); signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0); signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0); signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC; signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0); signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0); signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC; signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC; signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC; signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC; signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0); signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0); signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0); signal RIN_D_MEXC_intermed_3 : STD_ULOGIC; signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC; signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0); signal DSUIN_CRDY2_intermed_2 : STD_LOGIC; signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0); signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0); signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC; signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC; signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0); signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0); signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0); signal RIN_W_S_S_intermed_2 : STD_ULOGIC; signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0); signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC; signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2); signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0); signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE; signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0); signal RIN_A_SU_intermed_2 : STD_ULOGIC; signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0); signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2); signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2); signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC; signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4); signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC; signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0); signal R_D_MEXC_intermed_4 : STD_ULOGIC; signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0); signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2); signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12); signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC; signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE; signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12); signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2); signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2); signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC; signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0); signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4); signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0); signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0); signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12); signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0); signal RIN_W_S_S_intermed_1 : STD_ULOGIC; signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0); signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12); signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC; signal R_X_DATA03_intermed_1 : STD_LOGIC; signal RIN_M_DCI_intermed_1 : DC_IN_TYPE; signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0); signal RIN_W_S_EF_intermed_1 : STD_ULOGIC; signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0); signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC; signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0); signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0); signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0); signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11); signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC; signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC; signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC; signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC; signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0); signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12); signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3); signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0); signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12); signal DCO_MEXC_intermed_1 : STD_ULOGIC; signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0); signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0); signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC; signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12); signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2); signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0); signal RIN_A_SU_intermed_1 : STD_ULOGIC; signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal V_E_OP231_shadow_intermed_1 : STD_LOGIC; signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC; signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0); signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12); signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2); signal RPIN_ERROR_intermed_2 : STD_ULOGIC; signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0); signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC; signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC; signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0); signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0); signal DCO_DATA00_intermed_1 : STD_LOGIC; signal V_M_Y31_shadow_intermed_1 : STD_LOGIC; signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2); signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC; signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0); signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2); signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2); signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC; signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0); signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12); signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2); signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0); signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC; signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC; signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2); signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC; signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0); signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0); signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2); signal RIN_D_MEXC_intermed_2 : STD_ULOGIC; signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4); signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal V_A_SU_shadow_intermed_2 : STD_ULOGIC; signal V_M_Y31_shadow_intermed_2 : STD_LOGIC; signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0); signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC; signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC; signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC; signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2); signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC; signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC; signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0); signal RIN_A_RFE1_intermed_1 : STD_ULOGIC; signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2); signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4); signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12); signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC; signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2); signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC; signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0); signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2); signal R_X_DATA00_intermed_1 : STD_LOGIC; signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC; signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2); signal R_X_DATA03_intermed_2 : STD_LOGIC; signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4); signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0); signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC; signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE; signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0); signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4); signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2); signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2); signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0); signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2); signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC; signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0); signal RIN_M_MAC_intermed_1 : STD_ULOGIC; signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0); signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4); signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2); signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC; signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2); signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC; signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13); signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0); signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0); signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12); signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2); signal RIN_M_Y31_intermed_2 : STD_LOGIC; signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0); signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2); signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0); signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2); signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0); signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0); signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC; signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0); signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0); signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0); signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC; signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0); begin comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp) variable v : registers; variable vp : pwd_register_type; variable vwpr : watchpoint_registers; variable vdsu : dsu_registers; variable npc : std_logic_vector(31 downto 2); variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0); variable de_rs2, de_rd : std_logic_vector(4 downto 0); variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic; variable de_cwp, de_cwp2 : cwptype; variable de_inull : std_ulogic; variable de_ren1, de_ren2 : std_ulogic; variable de_wcwp : std_ulogic; variable de_inst : word; variable de_branch_address : pctype; variable de_icc : std_logic_vector(3 downto 0); variable de_fbranch, de_cbranch : std_ulogic; variable de_rs1mod : std_ulogic; variable ra_op1, ra_op2 : word; variable ra_div : std_ulogic; variable ex_jump, ex_link_pc : std_ulogic; variable ex_jump_address : pctype; variable ex_add_res : std_logic_vector(32 downto 0); variable ex_shift_res, ex_logic_res, ex_misc_res : word; variable ex_edata, ex_edata2 : word; variable ex_dci : dc_in_type; variable ex_force_a2, ex_load, ex_ymsb : std_ulogic; variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word; variable ex_shcnt : std_logic_vector(4 downto 0); variable ex_dsuen : std_ulogic; variable ex_ldbp2 : std_ulogic; variable ex_sari : std_ulogic; variable me_inull, me_nullify, me_nullify2 : std_ulogic; variable me_iflush : std_ulogic; variable me_newtt : std_logic_vector(5 downto 0); variable me_asr18 : word; variable me_signed : std_ulogic; variable me_size, me_laddr : std_logic_vector(1 downto 0); variable me_icc : std_logic_vector(3 downto 0); variable xc_result : word; variable xc_df_result : word; variable xc_waddr : std_logic_vector(9 downto 0); variable xc_exception, xc_wreg : std_ulogic; variable xc_trap_address : pctype; variable xc_vectt : std_logic_vector(7 downto 0); variable xc_trap : std_ulogic; variable xc_fpexack : std_ulogic; variable xc_rstn, xc_halt : std_ulogic; -- variable wr_rf1_data, wr_rf2_data : word; variable diagdata : word; variable tbufi : tracebuf_in_type; variable dbgm : std_ulogic; variable fpcdbgwr : std_ulogic; variable vfpi : fpc_in_type; variable dsign : std_ulogic; variable pwrd, sidle : std_ulogic; variable vir : irestart_register; variable icnt : std_ulogic; variable tbufcntx : std_logic_vector(7-1 downto 0); begin v := r; vwpr := wpr; vdsu := dsur; vp := rp; xc_fpexack := '0'; sidle := '0'; fpcdbgwr := '0'; vir := ir; xc_rstn := rstn; ----------------------------------------------------------------------- -- WRITE STAGE ----------------------------------------------------------------------- -- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2; -- if irfwt = 0 then -- if r.w.wreg = '1' then -- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if; -- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if; -- end if; -- end if; ----------------------------------------------------------------------- -- EXCEPTION STAGE ----------------------------------------------------------------------- xc_exception := '0'; xc_halt := '0'; icnt := '0'; xc_waddr := "0000000000"; xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0); xc_trap := r.x.mexc or r.x.ctrl.trap; v.x.nerror := rp.error; if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX; elsif r.x.ctrl.tt = TT_TICC then xc_vectt := '1' & r.x.result(6 downto 0); else xc_vectt := "00" & r.x.ctrl.tt; end if; if r.w.s.svt = '0' then xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt; else xc_trap_address(31 downto 4) := r.w.s.tba & "00000000"; end if; xc_trap_address(3 downto 2) := "00"; xc_wreg := '0'; v.x.annul_all := '0'; if (r.x.ctrl.ld = '1') then if (lddel = 2) then xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed); else xc_result := r.x.data(0); end if; elsif false and false and (r.x.mac = '1') then xc_result := mulo.result(31 downto 0); else xc_result := r.x.result; end if; xc_df_result := xc_result; if true then dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt); if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if; else dbgm := '0'; v.x.debug := '0'; end if; if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if; case r.x.rstate is when run => if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then icnt := holdn; end if; if dbgm = '1' then v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc; v.x.rstate := dsu1; v.x.debug := '1'; v.x.npc := npc_find(r); vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt); elsif (pwrd = '1') and (ir.pwd = '0') then v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc; v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1'; elsif (r.x.ctrl.annul or xc_trap) = '0' then xc_wreg := r.x.ctrl.wreg; sp_write (r, wpr, v.w.s, vwpr); vir.pwd := '0'; elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00"; xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s; v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap; xc_waddr := "0000000000"; xc_waddr(6 downto 0) := r.w.s.cwp & "0001"; v.x.npc := npc_find(r); fpexack(r, xc_fpexack); if r.w.s.et = '0' then -- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1'; xc_wreg := '0'; end if; end if; when trap => xc_result := npc_gen(r); xc_wreg := '1'; xc_waddr := "0000000000"; xc_waddr(6 downto 0) := r.w.s.cwp & "0010"; if (r.w.s.et = '1') then v.w.s.et := '0'; v.x.rstate := run; if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111"; else v.w.s.cwp := r.w.s.cwp - 1 ; end if; else v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1'; end if; when dsu1 => xc_exception := '1'; v.x.annul_all := '1'; xc_trap_address(31 downto 2) := r.f.pc; if true or false or (smp /= 0) then xc_trap_address(31 downto 2) := ir.addr; vir.addr := npc_gen(r)(31 downto 2); v.x.rstate := dsu2; end if; if true then v.x.debug := r.x.debug; end if; when dsu2 => xc_exception := '1'; v.x.annul_all := '1'; xc_trap_address(31 downto 2) := r.f.pc; if true or false or (smp /= 0) then sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug; if true then if dbgi.reset = '1' then if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if; vp.error := '0'; end if; if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if; diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr); xc_halt := dbgi.halt; end if; if r.x.ipend = '1' then vp.pwd := '0'; end if; if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0'; xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0'; vir.pwd := '1'; end if; if (smp /= 0) and (irqi.rst = '1') then vp.pwd := '0'; vp.error := '0'; end if; end if; when others => end case; irq_intack(r, holdn, v.x.intack); itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi); vdsu.tbufcnt := tbufcntx; v.w.except := xc_exception; v.w.result := xc_result; if (r.x.rstate = dsu2) then v.w.except := '0'; end if; v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn; rfi.wdata <= xc_result; rfi.waddr <= xc_waddr; rfi.wren <= (xc_wreg and holdn) and not dco.scanen; irqo.intack <= r.x.intack and holdn; irqo.irl <= r.w.s.tt(3 downto 0); irqo.pwd <= rp.pwd; irqo.fpen <= r.w.s.ef; dbgo.halt <= xc_halt; dbgo.pwd <= rp.pwd; dbgo.idle <= sidle; dbgo.icnt <= icnt; dci.intack <= r.x.intack and holdn; if (xc_rstn = '0') then v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0'; v.w.s.ef := '0'; -- needed for AX if need_extra_sync_reset(fabtech) /= 0 then v.w.s.cwp := "000"; v.w.s.icc := "0000"; end if; v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0'; vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0'; v.x.nerror := '0'; if svt = 1 then v.w.s.tt := "00000000"; end if; if true then if (dbgi.dsuen and dbgi.dbreak) = '1' then v.x.rstate := dsu1; v.x.debug := '1'; end if; end if; if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then v.x.rstate := dsu1; vp.pwd := '1'; end if; end if; if not FPEN then v.w.s.ef := '0'; end if; ----------------------------------------------------------------------- -- MEMORY STAGE ----------------------------------------------------------------------- v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci; v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul; v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0); v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all; mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc); mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt); me_newtt := v.x.ctrl.tt; irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt); if (r.m.ctrl.ld or not dco.mds) = '1' then for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop; v.x.set := dco.set(0 downto 0); if dco.mds = '0' then me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed; else me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed; end if; if lddel /= 2 then v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed); end if; end if; v.x.mexc := dco.mexc; v.x.icc := me_icc; v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all; if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then v.w.s.asr18 := me_asr18; end if; if (r.x.rstate = dsu2) then me_nullify2 := '0'; v.x.set := dco.set(0 downto 0); end if; dci.maddress <= r.m.result; dci.msu <= r.m.su; dci.esu <= r.e.su; dci.enaddr <= r.m.dci.enaddr; dci.asi <= r.m.dci.asi; dci.size <= r.m.dci.size; dci.nullify <= me_nullify2; dci.lock <= r.m.dci.lock and not r.m.ctrl.annul; dci.read <= r.m.dci.read; dci.write <= r.m.dci.write; dci.flush <= me_iflush; dci.dsuen <= r.m.dci.dsuen; dbgo.ipend <= v.x.ipend; ----------------------------------------------------------------------- -- EXECUTE STAGE ----------------------------------------------------------------------- v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2; v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul; v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all; ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt; v.e.cwp := r.a.cwp; ex_sari := r.e.sari; v.m.su := r.e.su; if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if; if lddel = 1 then if r.e.ldbp1 = '1' then ex_op1 := r.x.data(0); ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20); end if; if r.e.ldbp2 = '1' then ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0); mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0); if r.e.invop2 = '1' then ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt; end if; end if; end if; ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin); if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0'; else v.m.nalign := '1'; end if; dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load ); ex_jump_address := ex_add_res(32 downto 3); logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y); ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari); misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata); ex_add_res(3):= ex_add_res(3) or ex_force_a2; alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz); dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci); fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result); cwp_ex(r, v.m.wcwp); v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all; v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all; v.m.mac := r.e.mac; if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if; dci.eenaddr <= v.m.dci.enaddr; dci.eaddress <= ex_add_res(32 downto 1); dci.edata <= ex_edata2; ----------------------------------------------------------------------- -- REGFILE STAGE ----------------------------------------------------------------------- v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl; v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all; v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul; v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all; v.e.su := r.a.su; v.e.et := r.a.et; v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all; exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt); op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1); op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2); alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2); cin_gen(r, v.m.icc(0), v.e.alucin); ----------------------------------------------------------------------- -- DECODE STAGE ----------------------------------------------------------------------- if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set)); else de_inst := r.d.inst(0); end if; de_icc := r.m.icc; v.a.cwp := r.d.cwp; su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et); wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy); cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp); rs1_gen(r, de_inst, v.a.rs1, de_rs1mod); de_rs2 := de_inst(4 downto 0); de_raddr1 := "0000000000"; de_raddr2 := "0000000000"; if true then if de_rs1mod = '1' then regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0)); else regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0)); end if; else regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0)); end if; regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0)); v.a.rfa1 := de_raddr1(7 downto 0); v.a.rfa2 := de_raddr2(7 downto 0); rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd); regaddr(de_cwp, de_rd, v.a.ctrl.rd); fpbranch(de_inst, fpo.cc, de_fbranch); fpbranch(de_inst, cpo.cc, de_cbranch); v.a.imm := imm_data(r, de_inst); lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex); ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart); cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp); v.d.inull := ra_inull_gen(r, v); op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1); op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2); de_branch_address := branch_address(de_inst, r.d.pc); v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all; v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul; v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul; v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul; v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul; v.a.ctrl.trap := r.d.mexc; v.a.ctrl.tt := "000000"; v.a.ctrl.inst := de_inst; v.a.ctrl.pc := r.d.pc; v.a.ctrl.cnt := r.d.cnt; v.a.step := r.d.step; if holdn = '0' then de_raddr1(7 downto 0) := r.a.rfa1; de_raddr2(7 downto 0) := r.a.rfa2; de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2; else de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2; end if; if true then if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1'; end if; v.d.step := dbgi.step and not r.d.annul; end if; rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2; rfi.ren1 <= de_ren1 and not dco.scanen; rfi.ren2 <= de_ren2 and not dco.scanen; rfi.diag <= dco.testen & "000"; ici.inull <= de_inull; ici.flush <= me_iflush; if (xc_rstn = '0') then v.d.cnt := "00"; if need_extra_sync_reset(fabtech) /= 0 then v.d.cwp := "000"; end if; end if; ----------------------------------------------------------------------- -- FETCH STAGE ----------------------------------------------------------------------- npc := r.f.pc; if (xc_rstn = '0') then v.f.pc := "000000000000000000000000000000"; v.f.branch := '0'; if false then v.f.pc(31 downto 12) := irqi.rstvec; else v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20); end if; elsif xc_exception = '1' then -- exception v.f.branch := '1'; v.f.pc := xc_trap_address; npc := v.f.pc; -- elsif (not ra_inull and de_hold_pc) = '1' then elsif de_hold_pc = '1' then v.f.pc := r.f.pc; v.f.branch := r.f.branch; if ex_jump = '1' then v.f.pc := ex_jump_address; v.f.branch := '1'; npc := v.f.pc; end if; elsif ex_jump = '1' then v.f.pc := ex_jump_address; v.f.branch := '1'; npc := v.f.pc; elsif de_branch = '1' then v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1'; npc := v.f.pc; else v.f.branch := '0'; v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer npc := v.f.pc; end if; ici.dpc <= r.d.pc(31 downto 2) & "00"; ici.fpc <= r.f.pc(31 downto 2) & "00"; ici.rpc <= npc(31 downto 2) & "00"; ici.fbranch <= r.f.branch; ici.rbranch <= v.f.branch; ici.su <= v.a.su; ici.fline <= "00000000000000000000000000000"; ici.flushl <= '0'; if (ico.mds and de_hold_pc) = '0' then for i in 0 to 2-1 loop v.d.inst(i) := ico.data(i); -- latch instruction end loop; v.d.set := ico.set(0 downto 0); -- latch instruction v.d.mexc := ico.mexc; -- latch instruction end if; ----------------------------------------------------------------------- ----------------------------------------------------------------------- if true then -- DSU diagnostic read diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata); diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy); end if; ----------------------------------------------------------------------- -- OUTPUTS ----------------------------------------------------------------------- rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir; muli.start <= r.a.mulstart and not r.a.ctrl.annul; muli.signed <= r.e.ctrl.inst(19); muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1; muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2; muli.mac <= r.e.ctrl.inst(24); if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0); else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if; muli.acc(31 downto 0) <= r.w.s.asr18; muli.flush <= r.x.annul_all; divi.start <= r.a.divstart and not r.a.ctrl.annul; divi.signed <= r.e.ctrl.inst(19); divi.flush <= r.x.annul_all; divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1; divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2; if (r.a.divstart and not r.a.ctrl.annul) = '1' then dsign := r.a.ctrl.inst(19); else dsign := r.e.ctrl.inst(19); end if; divi.y <= (r.m.y(31) and dsign) & r.m.y; rpin <= vp; if true then dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2); dbgo.data <= diagdata; if true then tbi <= tbufi; else tbi.addr <= (others => '0'); tbi.data <= (others => '0'); tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000"; end if; else dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0'; dbgo.dsumode <= '0'; tbi.addr <= (others => '0'); tbi.data <= (others => '0'); tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000"; end if; dbgo.error <= dummy and not r.x.nerror; -- pragma translate_off if FPEN then -- pragma translate_on vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst; vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc; vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2); vfpi.d.pv := r.d.pv; vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2); vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap; vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv; vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2); vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul; vfpi.e.pv := r.e.ctrl.pv; vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2); vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul; vfpi.m.pv := r.m.ctrl.pv; vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2); vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap; vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result; if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable; else vfpi.dbg.enable := '0'; end if; vfpi.dbg.write := fpcdbgwr; vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access vfpi.dbg.addr := dbgi.daddr(6 downto 2); vfpi.dbg.data := dbgi.ddata; fpi <= vfpi; cpi <= vfpi; -- dummy, just to kill some warnings ... -- pragma translate_off end if; -- pragma translate_on -- Assignments to be moved with variables -- These assignments must be moved to process COMB/ V_A_ET_shadow <= V.A.ET; EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 ); ICNT_shadow <= ICNT; EX_OP1_shadow <= EX_OP1; V_M_CTRL_PC_shadow <= V.M.CTRL.PC; V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 ); DE_REN1_shadow <= DE_REN1; DE_INST_shadow <= DE_INST; V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT; V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 ); V_W_S_TT_shadow <= V.W.S.TT; V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 ); EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 ); V_E_ALUCIN_shadow <= V.E.ALUCIN; V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 ); V_A_CTRL_PV_shadow <= V.A.CTRL.PV; V_E_CTRL_shadow <= V.E.CTRL; V_M_CTRL_shadow <= V.M.CTRL; V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 ); EX_SHCNT_shadow <= EX_SHCNT; V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE; V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL; V_X_MEXC_shadow <= V.X.MEXC; TBUFCNTX_shadow <= TBUFCNTX; V_A_CTRL_WY_shadow <= V.A.CTRL.WY; NPC_shadow <= NPC; V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 ); V_A_MULSTART_shadow <= V.A.MULSTART; XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 ); V_E_CTRL_TT_shadow <= V.E.CTRL.TT; DSIGN_shadow <= DSIGN; V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL; EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS; V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 ); V_A_RFE1_shadow <= V.A.RFE1; V_W_WA_shadow <= V.W.WA; V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL; EX_YMSB_shadow <= EX_YMSB; EX_ADD_RES_shadow <= EX_ADD_RES; VIR_ADDR_shadow <= VIR.ADDR; EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 ); V_W_S_CWP_shadow <= V.W.S.CWP; V_D_INST0_shadow <= V.D.INST ( 0 ); V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL; V_X_DATA1_shadow <= V.X.DATA ( 1 ); VP_PWD_shadow <= VP.PWD; V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 ); V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 ); V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT; V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT; V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 ); V_W_S_PS_shadow <= V.W.S.PS; V_X_CTRL_TT_shadow <= V.X.CTRL.TT; V_D_STEP_shadow <= V.D.STEP; V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC; VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 ); V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 ); V_X_RESULT_shadow <= V.X.RESULT; V_D_CNT_shadow <= V.D.CNT; XC_VECTT_shadow <= XC_VECTT; EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 ); V_W_S_EF_shadow <= V.W.S.EF; V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 ); V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 ); V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED; V_M_NALIGN_shadow <= V.M.NALIGN; XC_WREG_shadow <= XC_WREG; V_A_RFA2_shadow <= V.A.RFA2; V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 ); EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 ); EX_OP231_shadow <= EX_OP2( 31 ); XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 ); V_X_ICC_shadow <= V.X.ICC; V_A_SU_shadow <= V.A.SU; V_E_OP2_shadow <= V.E.OP2; EX_FORCE_A2_shadow <= EX_FORCE_A2; V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 ); V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 ); V_E_OP131_shadow <= V.E.OP1( 31 ); V_X_DCI_shadow <= V.X.DCI; V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC; EX_OP13_shadow <= EX_OP1( 3 ); V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 ); V_E_CTRL_INST_shadow <= V.E.CTRL.INST; V_E_CTRL_LD_shadow <= V.E.CTRL.LD; V_M_SU_shadow <= V.M.SU; V_E_SARI_shadow <= V.E.SARI; V_E_ET_shadow <= V.E.ET; V_M_CTRL_PV_shadow <= V.M.CTRL.PV; VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 ); MUL_OP2_shadow <= MUL_OP2; XC_EXCEPTION_shadow <= XC_EXCEPTION; V_E_OP1_shadow <= V.E.OP1; VP_ERROR_shadow <= VP.ERROR; V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED; V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 ); MUL_OP231_shadow <= MUL_OP2 ( 31 ); XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 ); V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 ); V_M_DCI_shadow <= V.M.DCI; EX_OP23_shadow <= EX_OP2( 3 ); V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 ); V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP; V_A_DIVSTART_shadow <= V.A.DIVSTART; V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); VDSU_TT_shadow <= VDSU.TT; EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 ); V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT; V_E_YMSB_shadow <= V.E.YMSB; EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 ); V_A_RFE2_shadow <= V.A.RFE2; V_E_OP13_shadow <= V.E.OP1( 3 ); V_A_CWP_shadow <= V.A.CWP; ME_SIZE_shadow <= ME_SIZE; V_X_MAC_shadow <= V.X.MAC; V_M_CTRL_INST_shadow <= V.M.CTRL.INST; VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 ); V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 ); DE_REN2_shadow <= DE_REN2; V_E_CTRL_PV_shadow <= V.E.CTRL.PV; V_E_MAC_shadow <= V.E.MAC; V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 ); EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 ); V_X_CTRL_INST_shadow <= V.X.CTRL.INST; V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 ); V_W_S_ET_shadow <= V.W.S.ET; V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT; V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL; DE_INST19_shadow <= DE_INST( 19 ); XC_HALT_shadow <= XC_HALT; V_E_OP231_shadow <= V.E.OP2( 31 ); V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 ); VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 ); V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC; V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG; V_W_S_S_shadow <= V.W.S.S; V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 ); V_E_CWP_shadow <= V.E.CWP; V_A_STEP_shadow <= V.A.STEP; V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 ); V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP; NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 ); V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP; V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 ); V_X_INTACK_shadow <= V.X.INTACK; SIDLE_shadow <= SIDLE; V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT; V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 ); V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 ); V_W_S_SVT_shadow <= V.W.S.SVT; V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 ); V_X_LADDR_shadow <= V.X.LADDR; V_W_S_DWT_shadow <= V.W.S.DWT; EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 ); V_W_S_TBA_shadow <= V.W.S.TBA; XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 ); V_M_MUL_shadow <= V.M.MUL; V_E_SU_shadow <= V.E.SU; V_M_Y31_shadow <= V.M.Y ( 31 ); V_E_OP23_shadow <= V.E.OP2( 3 ); V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 ); DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 ); V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 ); V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP; V_X_DEBUG_shadow <= V.X.DEBUG; V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK; V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 ); V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG; V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 ); V_D_MEXC_shadow <= V.D.MEXC; V_W_RESULT_shadow <= V.W.RESULT; VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE; EX_OP131_shadow <= EX_OP1 ( 31 ); V_D_INST1_shadow <= V.D.INST ( 1 ); V_W_EXCEPT_shadow <= V.W.EXCEPT; V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 ); ME_LADDR_shadow <= ME_LADDR; V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 ); V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT; XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 ); V_X_CTRL_PV_shadow <= V.X.CTRL.PV; V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 ); V_M_MAC_shadow <= V.M.MAC; V_D_SET_shadow <= V.D.SET; VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 ); V_D_CWP_shadow <= V.D.CWP; DE_INST20_shadow <= DE_INST( 20 ); V_D_ANNUL_shadow <= V.D.ANNUL; EX_OP2_shadow <= EX_OP2; EX_SARI_shadow <= EX_SARI; V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 ); V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE; V_M_Y_shadow <= V.M.Y; V_X_CTRL_PC_shadow <= V.X.CTRL.PC; V_X_SET_shadow <= V.X.SET; V_A_CTRL_PC_shadow <= V.A.CTRL.PC; V_A_JMPL_shadow <= V.A.JMPL; V_E_CTRL_PC_shadow <= V.E.CTRL.PC; V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 ); V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG; V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG; V_A_CTRL_shadow <= V.A.CTRL; V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 ); V_X_DATA0_shadow <= V.X.DATA ( 0 ); V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 ); ME_SIGNED_shadow <= ME_SIGNED; V_W_WREG_shadow <= V.W.WREG; V_D_PC_shadow <= V.D.PC; VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL; DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 ); V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT; V_F_PC_shadow <= V.F.PC; V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 ); V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 ); V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 ); V_M_CTRL_TT_shadow <= V.M.CTRL.TT; V_X_CTRL_shadow <= V.X.CTRL; V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 ); XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 ); V_X_NERROR_shadow <= V.X.NERROR; V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 ); V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 ); EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 ); EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 ); V_F_BRANCH_shadow <= V.F.BRANCH; V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC; V_A_CTRL_LD_shadow <= V.A.CTRL.LD; V_A_CTRL_TT_shadow <= V.A.CTRL.TT; V_M_CTRL_LD_shadow <= V.M.CTRL.LD; V_E_SHCNT_shadow <= V.E.SHCNT; XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 ); V_A_CTRL_INST_shadow <= V.A.CTRL.INST; V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 ); VIR_PWD_shadow <= VIR.PWD; XC_RESULT_shadow <= XC_RESULT; V_A_RFA1_shadow <= V.A.RFA1; V_E_JMPL_shadow <= V.E.JMPL; V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 ); ME_ICC_shadow <= ME_ICC; DE_INST24_shadow <= DE_INST( 24 ); XC_TRAP_shadow <= XC_TRAP; VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT; XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS; end process; dfp_delay : process(clk) begin if(clk'event and clk = '1')then RPIN_ERROR_intermed_1 <= RPIN.ERROR; VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow; V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow; RIN_W_S_S_intermed_1 <= RIN.W.S.S; V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow; V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1; V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow; RIN_W_S_PS_intermed_1 <= RIN.W.S.PS; R_W_S_S_intermed_1 <= R.W.S.S; RIN_W_S_S_intermed_1 <= RIN.W.S.S; RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1; DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4; R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4; V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow; V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3; V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow; R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG; R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1; RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1; RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2; RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG; RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1; V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow; V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1; V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2; RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1; V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2; V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3; R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG; R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1; R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2; RIN_X_INTACK_intermed_1 <= RIN.X.INTACK; V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1; V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2; R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1; R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2; V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2; R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3; R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4; RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4; V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2; R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 ); R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2; R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 ); RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3; V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2; RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1; RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2; V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow; V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1; R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 ); R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3; RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4; V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow; XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow; XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1; RIN_X_INTACK_intermed_1 <= RIN.X.INTACK; V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1; RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 ); R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK; V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow; V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL; R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL; V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 ); DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1; R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1; R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 ); R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 ); R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 ); R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 ); R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 ); RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 ); R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ); V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; RIN_A_RFE1_intermed_1 <= RIN.A.RFE1; V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow; RIN_A_RFE2_intermed_1 <= RIN.A.RFE2; V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 ); IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5; R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 ); R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 ); IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 ); V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 ); V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; RIN_E_OP1_intermed_1 <= RIN.E.OP1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow; RIN_E_OP2_intermed_1 <= RIN.E.OP2; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow; DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2; V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow; V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2; V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2; RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 ); RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1; R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 ); R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 ); RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 ); V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 ); V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; RIN_E_OP1_intermed_1 <= RIN.E.OP1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow; RIN_E_OP2_intermed_1 <= RIN.E.OP2; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow; DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 ); RIN_M_Y_intermed_1 <= RIN.M.Y; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1; V_M_Y_shadow_intermed_1 <= V_M_Y_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 ); RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_M_Y31_intermed_1 <= R.M.Y( 31 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 ); V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1; V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 ); RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1; R_M_Y31_intermed_1 <= R.M.Y( 31 ); R_M_Y31_intermed_2 <= R_M_Y31_intermed_1; VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow; VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1; DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 ); VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow; DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 ); DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1; DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 ); DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1; VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow; VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1; RIN_X_NERROR_intermed_1 <= RIN.X.NERROR; RPIN_ERROR_intermed_1 <= RPIN.ERROR; RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1; V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow; RP_ERROR_intermed_1 <= RP.ERROR; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1; R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 ); RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3; RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1; V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow; R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3; XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 ); RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 ); DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 ); V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 ); RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1; R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 ); DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 ); RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1; R_M_Y31_intermed_1 <= R.M.Y( 31 ); VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow; DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 ); DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1; DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow; DCO_DATA1_intermed_1 <= DCO.DATA ( 1 ); V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow; V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1; RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 ); R_X_DATA1_intermed_1 <= R.X.DATA( 1 ); R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1; RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 ); RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5; RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4; RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5; V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow; V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2; R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1; IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2; V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2; V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1; XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow; XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1; R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 ); R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3; RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4; IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 ); IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1; R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1; R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6; V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5; V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4; V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 ); RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5; R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4; R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3; R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2; RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6; RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7; VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow; VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1; VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2; V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3; V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4; ICO_DATA0_intermed_1 <= ICO.DATA ( 0 ); RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 ); V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow; V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1; R_D_INST0_intermed_1 <= R.D.INST( 0 ); R_D_INST0_intermed_2 <= R_D_INST0_intermed_1; RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 ); RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1; V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow; V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow; V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1; RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 ); RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 ); RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1; V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow; R_D_INST1_intermed_1 <= R.D.INST( 1 ); R_D_INST1_intermed_2 <= R_D_INST1_intermed_1; ICO_DATA1_intermed_1 <= ICO.DATA ( 1 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1; V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow; R_X_DATA1_intermed_1 <= R.X.DATA( 1 ); RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 ); RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4; V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow; XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow; R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3; IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 ); RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6; VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow; VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3; V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow; R_D_INST0_intermed_1 <= R.D.INST( 0 ); RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 ); RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1; V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow; RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 ); RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1; R_D_INST1_intermed_1 <= R.D.INST( 1 ); V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 ); R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1; RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1; DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_F_PC_intermed_1 <= RIN.F.PC; EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow; XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow; EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow; V_F_PC_shadow_intermed_1 <= V_F_PC_shadow; RIN_A_RFE1_intermed_1 <= RIN.A.RFE1; V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow; RIN_A_RFE2_intermed_1 <= RIN.A.RFE2; V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow; V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow; RIN_E_OP2_intermed_1 <= RIN.E.OP2; RIN_E_OP1_intermed_1 <= RIN.E.OP1; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN; DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2; R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1; RIN_E_YMSB_intermed_1 <= RIN.E.YMSB; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow; RIN_E_OP1_intermed_1 <= RIN.E.OP1; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow; RIN_E_OP2_intermed_1 <= RIN.E.OP2; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ); V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1; V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 ); V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 ); V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 ); R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2; R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 ); RIN_E_SARI_intermed_1 <= RIN.E.SARI; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 ); RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow; V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1; RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED; RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1; R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED; V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow; RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED; RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE; RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1; V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow; V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1; R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE; V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow; RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1; V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2; RIN_X_LADDR_intermed_1 <= RIN.X.LADDR; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1; V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 ); R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_X_RESULT_intermed_1 <= RIN.X.RESULT; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 ); R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4; R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4; V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow; V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3; V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow; R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG; R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1; RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1; RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2; RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG; RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1; V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow; V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1; V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2; RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1; V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2; V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3; R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG; R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1; R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2; V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2; V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2; V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow; V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3; R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT; RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow; V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1; RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP; V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow; V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow; V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1; V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2; V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3; V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow; V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow; V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1; V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2; V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3; V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4; R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP; R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1; R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2; RIN_X_MEXC_intermed_1 <= RIN.X.MEXC; RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP; RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1; R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP; ICO_MEXC_intermed_1 <= ICO.MEXC; ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1; ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2; ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3; ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4; R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP; R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1; RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP; RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1; RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2; RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3; V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow; V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1; V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2; RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP; RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1; RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1; RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2; RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3; RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4; R_D_MEXC_intermed_1 <= R.D.MEXC; R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1; R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2; R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3; DCO_MEXC_intermed_1 <= DCO.MEXC; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow; RPIN_PWD_intermed_1 <= RPIN.PWD; V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow; VP_PWD_shadow_intermed_1 <= VP_PWD_shadow; RPIN_ERROR_intermed_1 <= RPIN.ERROR; RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG; VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow; RIN_X_NERROR_intermed_1 <= RIN.X.NERROR; RPIN_ERROR_intermed_1 <= RPIN.ERROR; V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow; V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3; V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1; V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2; IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 ); R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2; R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT; RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 ); VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow; VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2; R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3; R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4; RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3; RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4; RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3; R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4; R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5; RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 ); RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1; RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow; V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2; RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2; V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3; V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4; V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5; V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 ); R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow; V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1; IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 ); IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow; V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2; V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3; XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow; R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 ); R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1; R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2; RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4; RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5; RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2; RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3; RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4; EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow; RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3; V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4; V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1; R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2; R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3; R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4; R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4; V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6; VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow; VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4; RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5; RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6; R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 ); R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1; R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1; R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2; V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4; RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 ); RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1; RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3; R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4; V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow; V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1; V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3; IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 ); IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1; EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow; EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow; RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3; RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4; RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5; XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow; V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3; V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4; V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5; IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 ); V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow; V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1; V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2; V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3; R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 ); R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2; RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3; RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4; RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 ); RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG; RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1; RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2; RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3; RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1; RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2; RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3; R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC; R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1; R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2; V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow; V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1; V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2; R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC; R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC; R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1; RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC; RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1; V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow; V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow; V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow; V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2; V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3; R_D_PC_intermed_1 <= R.D.PC; R_D_PC_intermed_2 <= R_D_PC_intermed_1; R_D_PC_intermed_3 <= R_D_PC_intermed_2; R_D_PC_intermed_4 <= R_D_PC_intermed_3; RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC; RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1; RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2; RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1; V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2; V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3; V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4; IRIN_ADDR_intermed_1 <= IRIN.ADDR; V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2; V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3; R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2; R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); DSUIN_TT_intermed_1 <= DSUIN.TT; R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2; V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow; V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3; RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT; RPIN_PWD_intermed_1 <= RPIN.PWD; IRIN_PWD_intermed_1 <= IRIN.PWD; V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2; V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3; R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2; R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2; V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow; V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); RIN_W_S_TT_intermed_1 <= RIN.W.S.TT; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3; RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT; RIN_W_S_S_intermed_1 <= RIN.W.S.S; RIN_W_S_PS_intermed_1 <= RIN.W.S.PS; V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow; RIN_W_S_S_intermed_1 <= RIN.W.S.S; RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 ); RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1; RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2; RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 ); RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1; RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 ); V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow; RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP; V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow; V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1; R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 ); R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1; V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow; V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1; V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2; V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow; V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1; V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2; V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3; R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 ); R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1; R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2; RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 ); RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1; RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2; RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3; R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 ); V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow; RIN_W_S_ET_intermed_1 <= RIN.W.S.ET; RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP; RPIN_ERROR_intermed_1 <= RPIN.ERROR; RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1; RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2; RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3; RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4; RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1; RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2; RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3; RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4; R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC; R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1; R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2; R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow; V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1; V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2; V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3; EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow; XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC; R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC; R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC; R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1; R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC; RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1; RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow; V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow; V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1; V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow; V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2; V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3; V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; R_D_PC_intermed_1 <= R.D.PC; R_D_PC_intermed_2 <= R_D_PC_intermed_1; R_D_PC_intermed_3 <= R_D_PC_intermed_2; R_D_PC_intermed_4 <= R_D_PC_intermed_3; R_D_PC_intermed_5 <= R_D_PC_intermed_4; RIN_F_PC_intermed_1 <= RIN.F.PC; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC; RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1; RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2; RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3; RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC; RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1; V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2; V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3; V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4; V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; IRIN_ADDR_intermed_1 <= IRIN.ADDR; EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); V_F_PC_shadow_intermed_1 <= V_F_PC_shadow; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT; RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_X_RESULT_intermed_1 <= RIN.X.RESULT; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 ); DCO_DATA0_intermed_1 <= DCO.DATA ( 0 ); V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); RIN_W_RESULT_intermed_1 <= RIN.W.RESULT; R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow; V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1; V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow; V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1; V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2; R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 ); R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1; V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow; V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow; V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1; V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2; V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3; RIN_W_WA_intermed_1 <= RIN.W.WA; RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 ); RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1; RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2; RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3; R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 ); R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 ); R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1; R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2; RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 ); RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1; RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2; RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 ); RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 ); RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3; V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow; RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG; RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG; RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2; RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1; V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2; V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3; R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG; R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1; R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2; RIN_W_WREG_intermed_1 <= RIN.W.WREG; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3; R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4; V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow; V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1; R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG; R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1; RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2; V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow; V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1; V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2; RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT; RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT; RIN_W_S_EF_intermed_1 <= RIN.W.S.EF; RIN_E_CTRL_intermed_1 <= RIN.E.CTRL; RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1; R_E_CTRL_intermed_1 <= R.E.CTRL; RIN_X_CTRL_intermed_1 <= RIN.X.CTRL; RIN_M_CTRL_intermed_1 <= RIN.M.CTRL; V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow; V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1; RIN_A_CTRL_intermed_1 <= RIN.A.CTRL; RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1; RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2; V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow; V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow; V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1; V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2; R_A_CTRL_intermed_1 <= R.A.CTRL; R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1; V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow; RIN_M_DCI_intermed_1 <= RIN.M.DCI; RIN_X_DCI_intermed_1 <= RIN.X.DCI; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT; V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL; V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow; V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1; V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow; V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1; V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2; RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT; RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1; RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1; R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT; RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1; V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow; V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT; V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow; R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT; R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1; R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL; V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow; V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1; RIN_M_MAC_intermed_1 <= RIN.M.MAC; RIN_E_MAC_intermed_1 <= RIN.E.MAC; RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1; R_E_MAC_intermed_1 <= R.E.MAC; V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow; RIN_X_MAC_intermed_1 <= RIN.X.MAC; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1; RIN_X_LADDR_intermed_1 <= RIN.X.LADDR; RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 ); RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL; RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow; V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL; V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3; R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2; R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT; R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2; V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow; V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3; RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT; V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow; V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1; RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 ); R_X_DATA0_intermed_1 <= R.X.DATA( 0 ); RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 ); RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1; V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow; V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1; RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 ); R_X_DATA1_intermed_1 <= R.X.DATA( 1 ); RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 ); RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1; RIN_X_SET_intermed_1 <= RIN.X.SET; V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow; V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1; R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE; RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE; RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE; RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1; RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED; RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1; R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED; RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED; V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow; V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1; RIN_X_MEXC_intermed_1 <= RIN.X.MEXC; RIN_X_ICC_intermed_1 <= RIN.X.ICC; R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC; R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow; V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1; V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow; V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1; V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC; RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1; RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC; R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC; RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1; RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; RIN_E_CTRL_intermed_1 <= RIN.E.CTRL; RIN_M_CTRL_intermed_1 <= RIN.M.CTRL; V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow; RIN_A_CTRL_intermed_1 <= RIN.A.CTRL; RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1; V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow; V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1; R_A_CTRL_intermed_1 <= R.A.CTRL; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow; V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow; V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1; RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT; RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT; V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1; R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow; RIN_E_CWP_intermed_1 <= RIN.E.CWP; V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow; RIN_D_CWP_intermed_1 <= RIN.D.CWP; RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1; RIN_A_CWP_intermed_1 <= RIN.A.CWP; V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow; V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1; R_D_CWP_intermed_1 <= R.D.CWP; R_A_SU_intermed_1 <= R.A.SU; RIN_A_SU_intermed_1 <= RIN.A.SU; RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1; V_E_SU_shadow_intermed_1 <= V_E_SU_shadow; V_A_SU_shadow_intermed_1 <= V_A_SU_shadow; V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1; RIN_M_SU_intermed_1 <= RIN.M.SU; RIN_E_SU_intermed_1 <= RIN.E.SU; RIN_M_MUL_intermed_1 <= RIN.M.MUL; RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 ); R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 ); RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 ); V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow; V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow; V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL; R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow; V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow; V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC; RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC; RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow; RIN_M_MAC_intermed_1 <= RIN.M.MAC; RIN_E_MAC_intermed_1 <= RIN.E.MAC; R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD; R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1; RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD; RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1; RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2; V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow; V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1; R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD; RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD; RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1; RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD; V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow; V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1; V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2; RIN_E_CTRL_intermed_1 <= RIN.E.CTRL; RIN_A_CTRL_intermed_1 <= RIN.A.CTRL; V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow; RIN_E_JMPL_intermed_1 <= RIN.E.JMPL; RIN_A_JMPL_intermed_1 <= RIN.A.JMPL; V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow; RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; RIN_A_SU_intermed_1 <= RIN.A.SU; V_A_SU_shadow_intermed_1 <= V_A_SU_shadow; RIN_E_SU_intermed_1 <= RIN.E.SU; RIN_E_ET_intermed_1 <= RIN.E.ET; RIN_A_ET_intermed_1 <= RIN.A.ET; V_A_ET_shadow_intermed_1 <= V_A_ET_shadow; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; RIN_D_CWP_intermed_1 <= RIN.D.CWP; RIN_A_CWP_intermed_1 <= RIN.A.CWP; V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow; RIN_A_RFA1_intermed_1 <= RIN.A.RFA1; V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow; DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 ); RIN_A_RFA1_intermed_1 <= RIN.A.RFA1; RIN_A_RFA2_intermed_1 <= RIN.A.RFA2; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY; ICO_MEXC_intermed_1 <= ICO.MEXC; RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP; V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST; RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; RIN_D_CNT_intermed_1 <= RIN.D.CNT; V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow; RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT; R_D_ANNUL_intermed_1 <= R.D.ANNUL; RIN_D_STEP_intermed_1 <= RIN.D.STEP; V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow; V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1; DBGI_STEP_intermed_1 <= DBGI.STEP; V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow; RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL; RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1; RIN_A_STEP_intermed_1 <= RIN.A.STEP; RIN_D_STEP_intermed_1 <= RIN.D.STEP; V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow; RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL; RIN_D_CNT_intermed_1 <= RIN.D.CNT; EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow; RIN_F_PC_intermed_1 <= RIN.F.PC; EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow; RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 ); RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4; V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow; V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1; XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow; R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3; IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6; VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow; VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 ); VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 ); IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 ); R_D_INST0_intermed_1 <= R.D.INST( 0 ); V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow; V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1; RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 ); RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1; RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 ); R_D_INST1_intermed_1 <= R.D.INST( 1 ); V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow; V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1; RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 ); RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1; RIN_D_SET_intermed_1 <= RIN.D.SET; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow; R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow; V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 ); R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 ); V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1; V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 ); R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 ); V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4; V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3; IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6; VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow; VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6; EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow; RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5; VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow; VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1; XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3; EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow; IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow; V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow; V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1; V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow; V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1; V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2; R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 ); R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1; V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow; V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1; V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2; V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3; RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 ); RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1; RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2; RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3; R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 ); R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 ); R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1; R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2; RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 ); RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1; RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2; RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 ); RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 ); RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1; RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP; V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow; V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1; V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2; V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3; ICO_MEXC_intermed_1 <= ICO.MEXC; ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1; ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2; ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3; ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4; R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP; R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1; RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP; RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1; RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2; RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3; V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow; V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1; V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2; RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP; RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1; RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2; R_D_MEXC_intermed_1 <= R.D.MEXC; R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1; R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2; R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3; V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow; V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1; V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow; V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1; V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2; V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3; V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4; R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP; R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1; R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2; RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP; RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1; R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1; RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2; RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3; RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 ); V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow; V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1; RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 ); RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1; R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 ); RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1; RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2; RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3; RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1; RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2; RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3; R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC; R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1; R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2; V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow; V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1; V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2; R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC; R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC; R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1; RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC; RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1; V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow; V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow; V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2; V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3; R_D_PC_intermed_1 <= R.D.PC; R_D_PC_intermed_2 <= R_D_PC_intermed_1; R_D_PC_intermed_3 <= R_D_PC_intermed_2; R_D_PC_intermed_4 <= R_D_PC_intermed_3; RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC; RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1; RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2; RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1; V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2; V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3; V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4; RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL; RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1; RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2; RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3; RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4; R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL; R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1; R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2; R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3; R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL; R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1; R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2; R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3; RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG; RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG; RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG; RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1; RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2; RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3; V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow; V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1; V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2; V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3; R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG; R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1; R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2; V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow; V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1; V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2; V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3; R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG; RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL; RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1; RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2; RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3; RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4; V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow; V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1; R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG; R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow; V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1; V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2; V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3; RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG; RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1; RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2; V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow; V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1; V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1; R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 ); RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1; V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow; V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1; R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3; XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow; V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1; RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1; R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 ); RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1; R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 ); RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 ); V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow; V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1; RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 ); RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1; DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 ); R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 ); V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2; V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow; V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 ); RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 ); V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2; V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow; V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 ); RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 ); R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 ); DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1; V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 ); R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2; R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 ); RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2; R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 ); DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 ); V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow; V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1; RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 ); RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1; R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2; RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1; V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow; V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1; DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 ); RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 ); R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1; RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 ); RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2; R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 ); R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2; V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow; V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 ); V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 ); RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 ); V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow; V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1; RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 ); RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1; R_M_Y31_intermed_1 <= R.M.Y( 31 ); DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 ); VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow; VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1; DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 ); DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1; DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; DE_INST_shadow_intermed_1 <= DE_INST_shadow; DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1; V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow; V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1; RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST; RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1; RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST; R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST; RIN_D_CNT_intermed_1 <= RIN.D.CNT; RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1; RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2; V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow; V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1; R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT; V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow; V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1; V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2; R_D_CNT_intermed_1 <= R.D.CNT; R_D_CNT_intermed_2 <= R_D_CNT_intermed_1; RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT; RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1; RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT; V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow; V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1; ICO_MEXC_intermed_1 <= ICO.MEXC; ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1; ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2; RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP; RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1; RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP; R_D_MEXC_intermed_1 <= R.D.MEXC; R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1; V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow; V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1; V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2; R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1; RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2; R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV; RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV; V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow; V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1; RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV; RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST; DE_INST_shadow_intermed_1 <= DE_INST_shadow; DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1; DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2; V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow; V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1; V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2; V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow; V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1; RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST; RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1; RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2; RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST; RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST; RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1; R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST; R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1; V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow; V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1; RIN_D_CNT_intermed_1 <= RIN.D.CNT; RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1; RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2; RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3; V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow; V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1; V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2; R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT; R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1; V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow; V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1; V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2; V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3; R_D_CNT_intermed_1 <= R.D.CNT; R_D_CNT_intermed_2 <= R_D_CNT_intermed_1; R_D_CNT_intermed_3 <= R_D_CNT_intermed_2; R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT; RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT; RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1; RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2; RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT; RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT; RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1; V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow; V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1; V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2; ICO_MEXC_intermed_1 <= ICO.MEXC; ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1; ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2; ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3; R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP; RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP; RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1; RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2; V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow; V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1; RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP; RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1; R_D_MEXC_intermed_1 <= R.D.MEXC; R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1; R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2; V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow; V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1; V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2; V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3; R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP; R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1; RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP; RIN_D_MEXC_intermed_1 <= RIN.D.MEXC; RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1; RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2; RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3; V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow; V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1; R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV; R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV; R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1; RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV; RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1; RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV; V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow; V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1; V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2; RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV; RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1; RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2; R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST; R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1; R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST; DE_INST_shadow_intermed_1 <= DE_INST_shadow; DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1; DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2; DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3; V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow; V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1; V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2; V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3; V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow; V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1; V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2; RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST; RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST; RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1; RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2; RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3; RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST; RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1; RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST; RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1; RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2; V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow; V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1; R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST; R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1; R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2; V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow; V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1; V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2; RIN_D_CNT_intermed_1 <= RIN.D.CNT; RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1; RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2; RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3; RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4; R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT; V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow; V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1; V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2; V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3; R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT; R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1; R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2; V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow; V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1; V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2; V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3; V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4; R_D_CNT_intermed_1 <= R.D.CNT; R_D_CNT_intermed_2 <= R_D_CNT_intermed_1; R_D_CNT_intermed_3 <= R_D_CNT_intermed_2; R_D_CNT_intermed_4 <= R_D_CNT_intermed_3; R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT; R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1; RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT; RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT; RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1; RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2; RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3; RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT; RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1; RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT; RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1; RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2; V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow; V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1; V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow; V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1; V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2; R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV; R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV; R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1; R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV; R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1; R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2; RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV; RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1; RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2; RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV; RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV; RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1; V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow; V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1; V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2; V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3; V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow; V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1; RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV; RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1; RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2; RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3; V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow; V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1; RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 ); DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1; R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 ); DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 ); V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1; RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 ); DE_INST19_shadow_intermed_1 <= DE_INST19_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1; V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2; IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 ); VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow; VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1; RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3; RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4; RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2; R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3; R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3; R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4; R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5; RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 ); RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1; RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4; V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5; V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2; V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3; V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2; RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3; R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 ); R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1; IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 ); IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow; V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2; V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3; R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 ); R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1; R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2; XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4; RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5; RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2; RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3; RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4; EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3; V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4; V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1; R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2; R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3; V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3; RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2; R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3; R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4; RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 ); RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4; V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2; V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2; R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 ); IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 ); V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow; V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2; R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 ); R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4; RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2; RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3; V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1; R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3; R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4; R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4; V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6; VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow; VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4; RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5; RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6; R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 ); R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1; R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1; R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2; V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4; RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 ); RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1; RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3; R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4; V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow; V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1; V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3; IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 ); IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1; EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow; EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow; RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3; RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4; RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5; XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3; V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4; V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5; IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 ); V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow; V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1; V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2; V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3; R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 ); R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2; RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3; RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4; RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3; R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4; V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4; RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5; R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 ); R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1; R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1; R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2; V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2; V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3; RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 ); RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3; V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow; V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2; IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3; RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3; V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4; V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow; V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1; V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2; R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2; RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3; RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 ); RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1; RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2; RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 ); RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1; RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 ); V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow; V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1; R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 ); R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1; V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow; V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1; V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2; V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow; V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1; V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2; V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3; R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 ); R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1; R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2; RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 ); RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1; RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2; RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3; R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 ); V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow; V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2; R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1; R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT; RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2; R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD; RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD; RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1; RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD; V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow; V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4; EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow; RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3; EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow; XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3; IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6; VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow; VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3; V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow; R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow; V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1; R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2; RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1; R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3; XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow; V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1; DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 ); R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 ); RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3; IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 ); V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow; V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2; R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1; RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4; V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4; RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5; RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 ); RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1; IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 ); V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3; R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4; R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 ); R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3; RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3; V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow; V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1; V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2; R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2; RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3; V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow; V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1; V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow; V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1; V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2; IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 ); VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow; VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1; RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3; RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4; RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2; R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3; R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3; R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4; R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5; RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 ); RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1; RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2; EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4; V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5; V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2; V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3; V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2; RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3; R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 ); R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1; IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 ); IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow; V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2; V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3; R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 ); R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1; R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4; RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5; RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2; RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3; RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4; EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3; V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4; V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1; R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2; R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3; R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4; R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4; V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5; V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6; VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow; VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4; RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5; RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6; R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 ); R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1; R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1; R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2; R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2; V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3; V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4; RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 ); RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1; RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3; R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4; V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow; V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1; V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3; IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 ); IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1; EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow; EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow; RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3; RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4; RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5; V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3; V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4; V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5; IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 ); V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow; V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1; V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2; V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3; R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 ); R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2; RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3; RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4; RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 ); V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow; V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1; R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 ); V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow; V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1; V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2; RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 ); RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1; RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2; R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 ); R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1; RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 ); RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1; RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 ); RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1; RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2; RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1; RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2; R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC; R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1; V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow; V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1; R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC; RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC; V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow; V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1; V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2; R_D_PC_intermed_1 <= R.D.PC; R_D_PC_intermed_2 <= R_D_PC_intermed_1; R_D_PC_intermed_3 <= R_D_PC_intermed_2; RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC; RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1; V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2; V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3; RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 ); V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2; V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow; V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1; R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1; RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1; V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow; V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1; DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 ); RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 ); DE_INST20_shadow_intermed_1 <= DE_INST20_shadow; R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1; V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow; V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1; DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 ); RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 ); DE_INST24_shadow_intermed_1 <= DE_INST24_shadow; RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3; RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 ); V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1; V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow; V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1; R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4; R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2; RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3; V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow; V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2; RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 ); RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1; RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 ); R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 ); V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow; V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1; V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow; V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1; V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2; R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 ); R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1; RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 ); RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1; RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2; RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT; RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1; R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT; RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT; V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow; V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow; V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1; R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 ); RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1; RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ); R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1; RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1; V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow; V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2; RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2; R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 ); V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3; RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4; V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow; V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow; V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1; RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 ); RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1; R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 ); RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 ); RIN_D_PC_intermed_1 <= RIN.D.PC; RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1; RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2; RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC; RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1; R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC; V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow; V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1; R_D_PC_intermed_1 <= R.D.PC; R_D_PC_intermed_2 <= R_D_PC_intermed_1; RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC; V_D_PC_shadow_intermed_1 <= V_D_PC_shadow; V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1; V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2; V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow; V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1; V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2; RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 ); RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1; RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2; V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow; V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1; R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 ); R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1; RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1; R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 ); RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 ); RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3; V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow; V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1; RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2; R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 ); R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3; R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 ); V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow; V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1; RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1; RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 ); V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow; V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1; R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 ); RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 ); RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1; R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2; R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 ); RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 ); V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow; V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2; V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow; V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1; R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1; RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3; RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1; R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2; RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 ); V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow; V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2; R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1; V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow; V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1; RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 ); R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 ); RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1; V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow; V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1; RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 ); V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2; V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow; V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1; R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1; RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2; RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 ); R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 ); V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow; V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1; RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 ); RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1; R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 ); V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow; V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1; RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 ); RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1; RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 ); V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow; V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1; RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 ); R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 ); RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1; end if; end process; dfp_trap_vector(0) <= '1' when (RP.ERROR /= '1') else '0'; dfp_trap_vector(1) <= '1' when (RP.ERROR /= '0') else '0'; dfp_trap_vector(2) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0'; dfp_trap_vector(3) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0'; dfp_trap_vector(4) <= '1' when (R.W.S.S /= V_W_S_S_shadow_intermed_1) else '0'; dfp_trap_vector(5) <= '1' when (R.W.S.S /= '1') else '0'; dfp_trap_vector(6) <= '1' when (R.W.S.S /= RIN_W_S_S_intermed_1) else '0'; dfp_trap_vector(7) <= '1' when (R.W.S.PS /= V_W_S_S_shadow_intermed_2) else '0'; dfp_trap_vector(8) <= '1' when (R.W.S.PS /= V_W_S_PS_shadow_intermed_1) else '0'; dfp_trap_vector(9) <= '1' when (R.W.S.PS /= '1') else '0'; dfp_trap_vector(10) <= '1' when (R.W.S.PS /= RIN_W_S_PS_intermed_1) else '0'; dfp_trap_vector(11) <= '1' when (R.W.S.PS /= R_W_S_S_intermed_1) else '0'; dfp_trap_vector(12) <= '1' when (R.W.S.PS /= RIN_W_S_S_intermed_2) else '0'; dfp_trap_vector(13) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= R_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(14) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(15) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(16) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(17) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(18) <= '1' when (R.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(19) <= '1' when (R.X.DATA ( 0 ) /= R_X_DATA0_intermed_2) else '0'; dfp_trap_vector(20) <= '1' when (R.X.DATA ( 0 ) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(21) <= '1' when (R.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(22) <= '1' when (R.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(23) <= '1' when (R.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(24) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(25) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(26) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(27) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(28) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(29) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(30) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(31) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(32) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(33) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(34) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(35) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(36) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(37) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(38) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(39) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(40) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(41) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(42) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(43) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(44) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(45) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(46) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(47) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(48) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(49) <= '1' when (R.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(50) <= '1' when (RFI.WREN /= DCO.SCANEN) else '0'; dfp_trap_vector(51) <= '1' when (RFI.WREN /= V_X_ANNUL_ALL_shadow_intermed_4) else '0'; dfp_trap_vector(52) <= '1' when (RFI.WREN /= RIN_A_CTRL_ANNUL_intermed_5) else '0'; dfp_trap_vector(53) <= '1' when (RFI.WREN /= R_M_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(54) <= '1' when (RFI.WREN /= R.X.CTRL.WREG) else '0'; dfp_trap_vector(55) <= '1' when (RFI.WREN /= R_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(56) <= '1' when (RFI.WREN /= RIN_X_ANNUL_ALL_intermed_5) else '0'; dfp_trap_vector(57) <= '1' when (RFI.WREN /= V_M_CTRL_WREG_shadow_intermed_2) else '0'; dfp_trap_vector(58) <= '1' when (RFI.WREN /= R_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(59) <= '1' when (RFI.WREN /= HOLDN) else '0'; dfp_trap_vector(60) <= '1' when (RFI.WREN /= V_X_CTRL_WREG_shadow_intermed_1) else '0'; dfp_trap_vector(61) <= '1' when (RFI.WREN /= R_E_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(62) <= '1' when (RFI.WREN /= RIN_X_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(63) <= '1' when (RFI.WREN /= '1') else '0'; dfp_trap_vector(64) <= '1' when (RFI.WREN /= '0') else '0'; dfp_trap_vector(65) <= '1' when (RFI.WREN /= XC_WREG_shadow) else '0'; dfp_trap_vector(66) <= '1' when (RFI.WREN /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0'; dfp_trap_vector(67) <= '1' when (RFI.WREN /= RIN_E_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(68) <= '1' when (RFI.WREN /= RIN_M_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(69) <= '1' when (RFI.WREN /= V_E_CTRL_WREG_shadow_intermed_3) else '0'; dfp_trap_vector(70) <= '1' when (RFI.WREN /= RIN_A_CTRL_WREG_intermed_4) else '0'; dfp_trap_vector(71) <= '1' when (RFI.WREN /= V_A_CTRL_WREG_shadow_intermed_4) else '0'; dfp_trap_vector(72) <= '1' when (RFI.WREN /= R_A_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(73) <= '1' when (IRQO.INTACK /= RIN_X_INTACK_intermed_1) else '0'; dfp_trap_vector(74) <= '1' when (IRQO.INTACK /= V_X_INTACK_shadow_intermed_1) else '0'; dfp_trap_vector(75) <= '1' when (IRQO.INTACK /= HOLDN) else '0'; dfp_trap_vector(76) <= '1' when (IRQO.INTACK /= R.X.INTACK) else '0'; dfp_trap_vector(77) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(78) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_M_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(79) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(80) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(81) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0'; dfp_trap_vector(82) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_A_CTRL_TT3DOWNTO0_intermed_5) else '0'; dfp_trap_vector(83) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_A_CTRL_TT3DOWNTO0_intermed_6) else '0'; dfp_trap_vector(84) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4) else '0'; dfp_trap_vector(85) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_6) else '0'; dfp_trap_vector(86) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0'; dfp_trap_vector(87) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_W_S_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(88) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(89) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_E_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(90) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(91) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(92) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0'; dfp_trap_vector(93) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(94) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_M_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(95) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(96) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(97) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= R_X_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(98) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= RIN_E_CTRL_TT3DOWNTO0_intermed_5) else '0'; dfp_trap_vector(99) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(100) <= '1' when (R.W.S.TT ( 3 DOWNTO 0 ) /= XC_VECTT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(101) <= '1' when (DCI.INTACK /= RIN_X_INTACK_intermed_1) else '0'; dfp_trap_vector(102) <= '1' when (DCI.INTACK /= V_X_INTACK_shadow_intermed_1) else '0'; dfp_trap_vector(103) <= '1' when (DCI.INTACK /= HOLDN) else '0'; dfp_trap_vector(104) <= '1' when (DCI.INTACK /= R.X.INTACK) else '0'; dfp_trap_vector(105) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(106) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(107) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(108) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(109) <= '1' when (R.M.RESULT ( 1 DOWNTO 0 ) /= R_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(110) <= '1' when (DCI.LOCK /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(111) <= '1' when (DCI.LOCK /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(112) <= '1' when (DCI.LOCK /= RIN_E_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(113) <= '1' when (DCI.LOCK /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(114) <= '1' when (DCI.LOCK /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(115) <= '1' when (DCI.LOCK /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(116) <= '1' when (DCI.LOCK /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(117) <= '1' when (DCI.LOCK /= R.M.CTRL.ANNUL) else '0'; dfp_trap_vector(118) <= '1' when (DCI.LOCK /= RIN_M_DCI_LOCK_intermed_1) else '0'; dfp_trap_vector(119) <= '1' when (DCI.LOCK /= '1') else '0'; dfp_trap_vector(120) <= '1' when (DCI.LOCK /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(121) <= '1' when (DCI.LOCK /= '0') else '0'; dfp_trap_vector(122) <= '1' when (DCI.LOCK /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0'; dfp_trap_vector(123) <= '1' when (DCI.LOCK /= RIN_M_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(124) <= '1' when (DCI.LOCK /= R.M.DCI.LOCK) else '0'; dfp_trap_vector(125) <= '1' when (DCI.LOCK /= R_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(126) <= '1' when (DCI.LOCK /= V_M_DCI_LOCK_shadow_intermed_1) else '0'; dfp_trap_vector(127) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(128) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(129) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(130) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(131) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(132) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= DCO_DATA031_intermed_2) else '0'; dfp_trap_vector(133) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_2) else '0'; dfp_trap_vector(134) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_2) else '0'; dfp_trap_vector(135) <= '1' when (R.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(136) <= '1' when (R.E.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(137) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(138) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(139) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(140) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(141) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(142) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(143) <= '1' when (R.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(144) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(145) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(146) <= '1' when (R.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(147) <= '1' when (R.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(148) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(149) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(150) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(151) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(152) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_E_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(153) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_3) else '0'; dfp_trap_vector(154) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(155) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(156) <= '1' when (R.E.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_3) else '0'; dfp_trap_vector(157) <= '1' when (R.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_3) else '0'; dfp_trap_vector(158) <= '1' when (R.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(159) <= '1' when (R.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(160) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(161) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(162) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= DCO_DATA00_intermed_2) else '0'; dfp_trap_vector(163) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(164) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_1) else '0'; dfp_trap_vector(165) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(166) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_2) else '0'; dfp_trap_vector(167) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(168) <= '1' when (R.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_2) else '0'; dfp_trap_vector(169) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(170) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(171) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(172) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(173) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(174) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(175) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(176) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(177) <= '1' when (R.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(178) <= '1' when (RFI.REN1 /= DCO.SCANEN) else '0'; dfp_trap_vector(179) <= '1' when (RFI.REN1 /= RIN_A_RFE1_intermed_1) else '0'; dfp_trap_vector(180) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0'; dfp_trap_vector(181) <= '1' when (RFI.REN1 /= V_A_RFE1_shadow_intermed_1) else '0'; dfp_trap_vector(182) <= '1' when (RFI.REN1 /= R.A.RFE1) else '0'; dfp_trap_vector(183) <= '1' when (RFI.REN1 /= '1') else '0'; dfp_trap_vector(184) <= '1' when (RFI.REN2 /= DCO.SCANEN) else '0'; dfp_trap_vector(185) <= '1' when (RFI.REN2 /= RIN_A_RFE2_intermed_1) else '0'; dfp_trap_vector(186) <= '1' when (RFI.REN2 /= V_A_RFE2_shadow_intermed_1) else '0'; dfp_trap_vector(187) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0'; dfp_trap_vector(188) <= '1' when (RFI.REN2 /= R.A.RFE2) else '0'; dfp_trap_vector(189) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0'; dfp_trap_vector(190) <= '1' when (RFI.DIAG /= "0000") else '0'; dfp_trap_vector(191) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(192) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(193) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(194) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(195) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(196) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(197) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(198) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_8) else '0'; dfp_trap_vector(199) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(200) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_8) else '0'; dfp_trap_vector(201) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0'; dfp_trap_vector(202) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(203) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(204) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(205) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(206) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= IRIN_ADDR31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(207) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(208) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(209) <= '1' when (R.F.PC ( 2 DOWNTO 2 ) /= "1") else '0'; dfp_trap_vector(210) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(211) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(212) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(213) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= IR_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(214) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(215) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= R_F_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(216) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(217) <= '1' when (R.F.PC ( 31 DOWNTO 2 ) /= VIR_ADDR31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(218) <= '1' when (ICI.DPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(219) <= '1' when (ICI.DPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(220) <= '1' when (ICI.DPC /= x"00000000") else '0'; dfp_trap_vector(221) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(222) <= '1' when (ICI.DPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(223) <= '1' when (ICI.DPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(224) <= '1' when (ICI.DPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(225) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(226) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(227) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(228) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(229) <= '1' when (R.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(230) <= '1' when (ICI.FPC(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(231) <= '1' when (ICI.FPC(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(232) <= '1' when (ICI.FPC(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(233) <= '1' when (ICI.FPC(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(234) <= '1' when (ICI.FPC(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(235) <= '1' when (ICI.FPC(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(236) <= '1' when (ICI.FPC(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(237) <= '1' when (ICI.FPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(238) <= '1' when (ICI.FPC(31 downto 2) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(239) <= '1' when (ICI.FPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(240) <= '1' when (ICI.FPC(31 downto 2) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0'; dfp_trap_vector(241) <= '1' when (ICI.FPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(242) <= '1' when (ICI.FPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(243) <= '1' when (ICI.FPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(244) <= '1' when (ICI.FPC(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(245) <= '1' when (ICI.FPC /= X"00000000") else '0'; dfp_trap_vector(246) <= '1' when (ICI.FPC(31 downto 2) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(247) <= '1' when (ICI.FPC(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(248) <= '1' when (ICI.FPC(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(249) <= '1' when (ICI.FPC(0) /= '1') else '0'; dfp_trap_vector(250) <= '1' when (ICI.FPC(31 downto 2) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(251) <= '1' when (ICI.FPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(252) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(253) <= '1' when (ICI.FPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(254) <= '1' when (ICI.FPC(31 downto 2) /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(255) <= '1' when (ICI.FPC(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(256) <= '1' when (ICI.FPC(31 downto 2) /= R_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(257) <= '1' when (ICI.FPC(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(258) <= '1' when (ICI.FPC(31 downto 2) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(259) <= '1' when (ICI.RPC(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(260) <= '1' when (ICI.RPC(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(261) <= '1' when (ICI.RPC(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(262) <= '1' when (ICI.RPC(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(263) <= '1' when (ICI.RPC(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(264) <= '1' when (ICI.RPC(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(265) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0'; dfp_trap_vector(266) <= '1' when (ICI.RPC(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(267) <= '1' when (ICI.RPC(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(268) <= '1' when (ICI.RPC(31 downto 2) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(269) <= '1' when (ICI.RPC(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(270) <= '1' when (ICI.RPC(31 downto 2) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(271) <= '1' when (ICI.RPC(31 downto 2) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(272) <= '1' when (ICI.RPC(31 downto 2) /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(273) <= '1' when (ICI.RPC(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(274) <= '1' when (ICI.RPC /= X"00000000") else '0'; dfp_trap_vector(275) <= '1' when (ICI.RPC(31 downto 2) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(276) <= '1' when (ICI.RPC(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(277) <= '1' when (ICI.RPC(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(278) <= '1' when (ICI.RPC(31 downto 2) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(279) <= '1' when (ICI.RPC(31 downto 2) /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(280) <= '1' when (ICI.RPC(31 downto 2) /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(281) <= '1' when (ICI.RPC(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(282) <= '1' when (ICI.RPC(31 downto 2) /= R.F.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(283) <= '1' when (ICI.RPC(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(284) <= '1' when (ICI.RPC(31 downto 2) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(285) <= '1' when (ICI.FLUSHL /= '0') else '0'; dfp_trap_vector(286) <= '1' when (MULI.START /= R.A.MULSTART) else '0'; dfp_trap_vector(287) <= '1' when (MULI.START /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(288) <= '1' when (MULI.START /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(289) <= '1' when (MULI.START /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(290) <= '1' when (MULI.START /= V_A_MULSTART_shadow_intermed_1) else '0'; dfp_trap_vector(291) <= '1' when (MULI.START /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(292) <= '1' when (MULI.START /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(293) <= '1' when (MULI.START /= RIN_A_MULSTART_intermed_1) else '0'; dfp_trap_vector(294) <= '1' when (MULI.START /= '1') else '0'; dfp_trap_vector(295) <= '1' when (MULI.START /= '0') else '0'; dfp_trap_vector(296) <= '1' when (MULI.START /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(297) <= '1' when (MULI.OP1(31) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(298) <= '1' when (MULI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(299) <= '1' when (MULI.OP1(19) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(300) <= '1' when (MULI.OP1(31) /= RIN_E_OP131_intermed_1) else '0'; dfp_trap_vector(301) <= '1' when (MULI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(302) <= '1' when (MULI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(303) <= '1' when (MULI.OP1(31) /= V_E_OP131_shadow_intermed_1) else '0'; dfp_trap_vector(304) <= '1' when (MULI.OP1(31) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(305) <= '1' when (MULI.OP1(31) /= R.E.OP1( 31 )) else '0'; dfp_trap_vector(306) <= '1' when (MULI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(307) <= '1' when (MULI.OP1(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0'; dfp_trap_vector(308) <= '1' when (MULI.OP1(31) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(309) <= '1' when (MULI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(310) <= '1' when (MULI.OP1(31) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(311) <= '1' when (MULI.OP1(31 downto 0) /= RIN_E_OP1_intermed_1) else '0'; dfp_trap_vector(312) <= '1' when (MULI.OP1(19) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(313) <= '1' when (MULI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(314) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0'; dfp_trap_vector(315) <= '1' when (MULI.OP1(31) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(316) <= '1' when (MULI.OP1(31) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(317) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0'; dfp_trap_vector(318) <= '1' when (MULI.OP1(19) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(319) <= '1' when (MULI.OP1(31 downto 0) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(320) <= '1' when (MULI.OP1(31 downto 0) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(321) <= '1' when (MULI.OP1(19) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(322) <= '1' when (MULI.OP1(19) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(323) <= '1' when (MULI.OP1(19) /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(324) <= '1' when (MULI.OP1(19) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(325) <= '1' when (MULI.OP1(19) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(326) <= '1' when (MULI.OP1(31) /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(327) <= '1' when (MULI.OP1(31 downto 0) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(328) <= '1' when (MULI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(329) <= '1' when (MULI.OP1(19) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(330) <= '1' when (MULI.OP1(31 downto 0) /= R.E.OP1) else '0'; dfp_trap_vector(331) <= '1' when (MULI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(332) <= '1' when (MULI.OP2(31) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(333) <= '1' when (MULI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(334) <= '1' when (MULI.OP2(19) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(335) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0'; dfp_trap_vector(336) <= '1' when (MULI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(337) <= '1' when (MULI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(338) <= '1' when (MULI.OP2(31) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(339) <= '1' when (MULI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(340) <= '1' when (MULI.OP2(31) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(341) <= '1' when (MULI.OP2(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0'; dfp_trap_vector(342) <= '1' when (MULI.OP2(31 downto 0) /= RIN_E_OP2_intermed_1) else '0'; dfp_trap_vector(343) <= '1' when (MULI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(344) <= '1' when (MULI.OP2(31) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(345) <= '1' when (MULI.OP2(31) /= EX_OP231_shadow) else '0'; dfp_trap_vector(346) <= '1' when (MULI.OP2(19) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(347) <= '1' when (MULI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(348) <= '1' when (MULI.OP2(31 downto 0) /= EX_OP2_shadow) else '0'; dfp_trap_vector(349) <= '1' when (MULI.OP2(31) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(350) <= '1' when (MULI.OP2(31) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(351) <= '1' when (MULI.OP2(19) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(352) <= '1' when (MULI.OP2(31 downto 0) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(353) <= '1' when (MULI.OP2(31 downto 0) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(354) <= '1' when (MULI.OP2(19) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(355) <= '1' when (MULI.OP2(31) /= RIN_E_OP231_intermed_1) else '0'; dfp_trap_vector(356) <= '1' when (MULI.OP2(31) /= R.E.OP2( 31 )) else '0'; dfp_trap_vector(357) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0'; dfp_trap_vector(358) <= '1' when (MULI.OP2(19) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(359) <= '1' when (MULI.OP2(19) /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(360) <= '1' when (MULI.OP2(19) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(361) <= '1' when (MULI.OP2(31 downto 0) /= R.E.OP2) else '0'; dfp_trap_vector(362) <= '1' when (MULI.OP2(19) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(363) <= '1' when (MULI.OP2(31) /= V_E_OP231_shadow_intermed_1) else '0'; dfp_trap_vector(364) <= '1' when (MULI.OP2(31) /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(365) <= '1' when (MULI.OP2(31 downto 0) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(366) <= '1' when (MULI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(367) <= '1' when (MULI.OP2(19) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(368) <= '1' when (MULI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(369) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_3) else '0'; dfp_trap_vector(370) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(371) <= '1' when (R.E.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_3) else '0'; dfp_trap_vector(372) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(373) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(374) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(375) <= '1' when (R.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(376) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_3) else '0'; dfp_trap_vector(377) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(378) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_E_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(379) <= '1' when (R.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(380) <= '1' when (R.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(381) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0'; dfp_trap_vector(382) <= '1' when (DIVI.START /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(383) <= '1' when (DIVI.START /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(384) <= '1' when (DIVI.START /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(385) <= '1' when (DIVI.START /= RIN_A_DIVSTART_intermed_1) else '0'; dfp_trap_vector(386) <= '1' when (DIVI.START /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(387) <= '1' when (DIVI.START /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(388) <= '1' when (DIVI.START /= V_A_DIVSTART_shadow_intermed_1) else '0'; dfp_trap_vector(389) <= '1' when (DIVI.START /= '1') else '0'; dfp_trap_vector(390) <= '1' when (DIVI.START /= '0') else '0'; dfp_trap_vector(391) <= '1' when (DIVI.START /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(392) <= '1' when (DIVI.OP1(31) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(393) <= '1' when (DIVI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(394) <= '1' when (DIVI.OP1(19) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(395) <= '1' when (DIVI.OP1(31) /= RIN_E_OP131_intermed_1) else '0'; dfp_trap_vector(396) <= '1' when (DIVI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(397) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(398) <= '1' when (DIVI.OP1(31) /= V_E_OP131_shadow_intermed_1) else '0'; dfp_trap_vector(399) <= '1' when (DIVI.OP1(31) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(400) <= '1' when (DIVI.OP1(31) /= R.E.OP1( 31 )) else '0'; dfp_trap_vector(401) <= '1' when (DIVI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(402) <= '1' when (DIVI.OP1(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0'; dfp_trap_vector(403) <= '1' when (DIVI.OP1(31) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(404) <= '1' when (DIVI.OP1(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(405) <= '1' when (DIVI.OP1(31) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(406) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_E_OP1_intermed_1) else '0'; dfp_trap_vector(407) <= '1' when (DIVI.OP1(19) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(408) <= '1' when (DIVI.OP1(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(409) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0'; dfp_trap_vector(410) <= '1' when (DIVI.OP1(31) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(411) <= '1' when (DIVI.OP1(31) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(412) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0'; dfp_trap_vector(413) <= '1' when (DIVI.OP1(19) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(414) <= '1' when (DIVI.OP1(31 downto 0) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(415) <= '1' when (DIVI.OP1(31 downto 0) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(416) <= '1' when (DIVI.OP1(19) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(417) <= '1' when (DIVI.OP1(19) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(418) <= '1' when (DIVI.OP1(19) /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(419) <= '1' when (DIVI.OP1(19) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(420) <= '1' when (DIVI.OP1(19) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(421) <= '1' when (DIVI.OP1(31) /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(422) <= '1' when (DIVI.OP1(31 downto 0) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(423) <= '1' when (DIVI.OP1(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(424) <= '1' when (DIVI.OP1(19) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(425) <= '1' when (DIVI.OP1(31 downto 0) /= R.E.OP1) else '0'; dfp_trap_vector(426) <= '1' when (DIVI.OP1(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(427) <= '1' when (DIVI.OP2(31) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(428) <= '1' when (DIVI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(429) <= '1' when (DIVI.OP2(19) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(430) <= '1' when (DIVI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(431) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(432) <= '1' when (DIVI.OP2(31) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(433) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0'; dfp_trap_vector(434) <= '1' when (DIVI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(435) <= '1' when (DIVI.OP2(31) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(436) <= '1' when (DIVI.OP2(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0'; dfp_trap_vector(437) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_E_OP2_intermed_1) else '0'; dfp_trap_vector(438) <= '1' when (DIVI.OP2(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(439) <= '1' when (DIVI.OP2(31) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(440) <= '1' when (DIVI.OP2(19) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(441) <= '1' when (DIVI.OP2(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(442) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0'; dfp_trap_vector(443) <= '1' when (DIVI.OP2(31) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(444) <= '1' when (DIVI.OP2(31) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(445) <= '1' when (DIVI.OP2(19) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(446) <= '1' when (DIVI.OP2(31 downto 0) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(447) <= '1' when (DIVI.OP2(31 downto 0) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(448) <= '1' when (DIVI.OP2(19) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(449) <= '1' when (DIVI.OP2(31) /= RIN_E_OP231_intermed_1) else '0'; dfp_trap_vector(450) <= '1' when (DIVI.OP2(31) /= R.E.OP2( 31 )) else '0'; dfp_trap_vector(451) <= '1' when (DIVI.OP2(19) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(452) <= '1' when (DIVI.OP2(19) /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(453) <= '1' when (DIVI.OP2(19) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(454) <= '1' when (DIVI.OP2(31 downto 0) /= R.E.OP2) else '0'; dfp_trap_vector(455) <= '1' when (DIVI.OP2(19) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(456) <= '1' when (DIVI.OP2(31) /= V_E_OP231_shadow_intermed_1) else '0'; dfp_trap_vector(457) <= '1' when (DIVI.OP2(31) /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(458) <= '1' when (DIVI.OP2(31 downto 0) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(459) <= '1' when (DIVI.OP2(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(460) <= '1' when (DIVI.OP2(19) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(461) <= '1' when (DIVI.OP2(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(462) <= '1' when (R.A.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(463) <= '1' when (R.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(464) <= '1' when (R.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(465) <= '1' when (R.A.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(466) <= '1' when (R.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(467) <= '1' when (R.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(468) <= '1' when (DIVI.Y(19) /= DE_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(469) <= '1' when (DIVI.Y(31) /= RIN_M_Y31_intermed_1) else '0'; dfp_trap_vector(470) <= '1' when (DIVI.Y(31 downto 0) /= RIN_M_Y_intermed_1) else '0'; dfp_trap_vector(471) <= '1' when (DIVI.Y(19) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(472) <= '1' when (DIVI.Y(19) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(473) <= '1' when (DIVI.Y(31) /= V_M_Y31_shadow_intermed_2) else '0'; dfp_trap_vector(474) <= '1' when (DIVI.Y(31 downto 0) /= V_M_Y_shadow_intermed_1) else '0'; dfp_trap_vector(475) <= '1' when (DIVI.Y(19) /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(476) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0'; dfp_trap_vector(477) <= '1' when (DIVI.Y(19) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(478) <= '1' when (DIVI.Y(31) /= V_M_Y31_shadow_intermed_1) else '0'; dfp_trap_vector(479) <= '1' when (DIVI.Y(19) /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(480) <= '1' when (DIVI.Y(0) /= DSIGN_shadow) else '0'; dfp_trap_vector(481) <= '1' when (DIVI.Y(31) /= RIN_M_Y31_intermed_2) else '0'; dfp_trap_vector(482) <= '1' when (DIVI.Y(19) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(483) <= '1' when (DIVI.Y(31) /= R_M_Y31_intermed_1) else '0'; dfp_trap_vector(484) <= '1' when (DIVI.Y(19) /= R.A.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(485) <= '1' when (DIVI.Y(19) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(486) <= '1' when (DIVI.Y(19) /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(487) <= '1' when (DIVI.Y(19) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(488) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0'; dfp_trap_vector(489) <= '1' when (DIVI.Y(19) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(490) <= '1' when (DIVI.Y(19) /= V_A_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(491) <= '1' when (R.M.Y ( 31 ) /= RIN_M_Y31_intermed_1) else '0'; dfp_trap_vector(492) <= '1' when (R.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_2) else '0'; dfp_trap_vector(493) <= '1' when (R.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_1) else '0'; dfp_trap_vector(494) <= '1' when (R.M.Y ( 31 ) /= RIN_M_Y31_intermed_2) else '0'; dfp_trap_vector(495) <= '1' when (R.M.Y ( 31 ) /= R_M_Y31_intermed_2) else '0'; dfp_trap_vector(496) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_2) else '0'; dfp_trap_vector(497) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0'; dfp_trap_vector(498) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0'; dfp_trap_vector(499) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0'; dfp_trap_vector(500) <= '1' when (DSUR.CRDY ( 2 ) /= DSUR_CRDY2_intermed_2) else '0'; dfp_trap_vector(501) <= '1' when (DBGO.ERROR /= VP_ERROR_shadow_intermed_2) else '0'; dfp_trap_vector(502) <= '1' when (DBGO.ERROR /= R.X.NERROR) else '0'; dfp_trap_vector(503) <= '1' when (DBGO.ERROR /= DUMMY) else '0'; dfp_trap_vector(504) <= '1' when (DBGO.ERROR /= RIN_X_NERROR_intermed_1) else '0'; dfp_trap_vector(505) <= '1' when (DBGO.ERROR /= '1') else '0'; dfp_trap_vector(506) <= '1' when (DBGO.ERROR /= '0') else '0'; dfp_trap_vector(507) <= '1' when (DBGO.ERROR /= RPIN_ERROR_intermed_2) else '0'; dfp_trap_vector(508) <= '1' when (DBGO.ERROR /= V_X_NERROR_shadow_intermed_1) else '0'; dfp_trap_vector(509) <= '1' when (DBGO.ERROR /= RP_ERROR_intermed_1) else '0'; dfp_trap_vector(510) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(511) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(512) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(513) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(514) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(515) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(516) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(517) <= '1' when (R.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(518) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(519) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(520) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(521) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(522) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(523) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(524) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(525) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(526) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(527) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(528) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(529) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(530) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(531) <= '1' when (R.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(532) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(533) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(534) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(535) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(536) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(537) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(538) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(539) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(540) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(541) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(542) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(543) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(544) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(545) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(546) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(547) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(548) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(549) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(550) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(551) <= '1' when (R.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(552) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(553) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(554) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(555) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0'; dfp_trap_vector(556) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(557) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(558) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0'; dfp_trap_vector(559) <= '1' when (RIN.X.DATA ( 0 ) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(560) <= '1' when (RIN.X.DATA ( 0 ) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(561) <= '1' when (RIN.X.DATA ( 0 ) /= DCO.DATA ( 0 )) else '0'; dfp_trap_vector(562) <= '1' when (RIN.X.DATA ( 0 ) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(563) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(564) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(565) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(566) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(567) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(568) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(569) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(570) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(571) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(572) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(573) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(574) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(575) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(576) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(577) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(578) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(579) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(580) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(581) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(582) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(583) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(584) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(585) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(586) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(587) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(588) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(589) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(590) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(591) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(592) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(593) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(594) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(595) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0'; dfp_trap_vector(596) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0'; dfp_trap_vector(597) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0'; dfp_trap_vector(598) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(599) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_W_S_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(600) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(601) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(602) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(603) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(604) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(605) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(606) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(607) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(608) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(609) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(610) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= R.W.S.TT ( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(611) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0'; dfp_trap_vector(612) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(613) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(614) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= R.M.RESULT ( 1 DOWNTO 0 )) else '0'; dfp_trap_vector(615) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(616) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0'; dfp_trap_vector(617) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= R_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(618) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(619) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(620) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(621) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R.X.DATA ( 0 ) ( 31 )) else '0'; dfp_trap_vector(622) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(623) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(624) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(625) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(626) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0'; dfp_trap_vector(627) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0'; dfp_trap_vector(628) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(629) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(630) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= DCO.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(631) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(632) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(633) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(634) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(635) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0'; dfp_trap_vector(636) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(637) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(638) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(639) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(640) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(641) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(642) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(643) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(644) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(645) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(646) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.E.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(647) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(648) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(649) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(650) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(651) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(652) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0'; dfp_trap_vector(653) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(654) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(655) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= RIN_E_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(656) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(657) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(658) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0'; dfp_trap_vector(659) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= DCO_DATA00_intermed_1) else '0'; dfp_trap_vector(660) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(661) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R.X.DATA ( 0 ) ( 0 )) else '0'; dfp_trap_vector(662) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(663) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(664) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(665) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(666) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= DCO.DATA ( 0 )( 0 )) else '0'; dfp_trap_vector(667) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0'; dfp_trap_vector(668) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(669) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= R.X.DATA ( 0 )( 0 )) else '0'; dfp_trap_vector(670) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(671) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(672) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(673) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(674) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(675) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0'; dfp_trap_vector(676) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(677) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(678) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(679) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(680) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(681) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(682) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(683) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R.X.DATA ( 0 )( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(684) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= DCO.DATA ( 0 )( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(685) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(686) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0'; dfp_trap_vector(687) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(688) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(689) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(690) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(691) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(692) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(693) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(694) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(695) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(696) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(697) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(698) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(699) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(700) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_F_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(701) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(702) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(703) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(704) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(705) <= '1' when (RIN.F.PC ( 2 DOWNTO 2 ) /= "1") else '0'; dfp_trap_vector(706) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(707) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(708) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R.F.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(709) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(710) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(711) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= R_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(712) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(713) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(714) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(715) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(716) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= R.D.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(717) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(718) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(719) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(720) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(721) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(722) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0'; dfp_trap_vector(723) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(724) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(725) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(726) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(727) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= RIN_E_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(728) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R_E_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(729) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0'; dfp_trap_vector(730) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.E.CTRL.INST ( 24 )) else '0'; dfp_trap_vector(731) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= DE_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(732) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(733) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(734) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(735) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(736) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0'; dfp_trap_vector(737) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow_intermed_1) else '0'; dfp_trap_vector(738) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0'; dfp_trap_vector(739) <= '1' when (RIN.M.Y ( 31 ) /= RIN_M_Y31_intermed_2) else '0'; dfp_trap_vector(740) <= '1' when (RIN.M.Y ( 31 ) /= R_M_Y31_intermed_1) else '0'; dfp_trap_vector(741) <= '1' when (RIN.M.Y ( 31 ) /= R.M.Y ( 31 )) else '0'; dfp_trap_vector(742) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0'; dfp_trap_vector(743) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0'; dfp_trap_vector(744) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_2) else '0'; dfp_trap_vector(745) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUR.CRDY ( 2 )) else '0'; dfp_trap_vector(746) <= '1' when (DSUIN.CRDY ( 2 ) /= DSUR_CRDY2_intermed_1) else '0'; dfp_trap_vector(747) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(748) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(749) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(750) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(751) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(752) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(753) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(754) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(755) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(756) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(757) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(758) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(759) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(760) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(761) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(762) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(763) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(764) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(765) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(766) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(767) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(768) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(769) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(770) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(771) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(772) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(773) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0'; dfp_trap_vector(774) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(775) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(776) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(777) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(778) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(779) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(780) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(781) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(782) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(783) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(784) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(785) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(786) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(787) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(788) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(789) <= '1' when (R.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_1) else '0'; dfp_trap_vector(790) <= '1' when (R.X.DATA ( 1 ) /= DCO_DATA1_intermed_1) else '0'; dfp_trap_vector(791) <= '1' when (R.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_2) else '0'; dfp_trap_vector(792) <= '1' when (R.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_1) else '0'; dfp_trap_vector(793) <= '1' when (R.X.DATA ( 1 ) /= R_X_DATA1_intermed_2) else '0'; dfp_trap_vector(794) <= '1' when (R.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_2) else '0'; dfp_trap_vector(795) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(796) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(797) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_A_CTRL_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(798) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_E_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(799) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(800) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_M_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(801) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= IRIN_ADDR31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(802) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(803) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2) else '0'; dfp_trap_vector(804) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(805) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_F_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(806) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_M_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(807) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= IR_ADDR31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(808) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_X_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(809) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_D_PC31DOWNTO12_shadow_intermed_8) else '0'; dfp_trap_vector(810) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_7) else '0'; dfp_trap_vector(811) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(812) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2) else '0'; dfp_trap_vector(813) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(814) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_D_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(815) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_A_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(816) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= R_E_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(817) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_X_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(818) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= RIN_D_PC31DOWNTO12_intermed_8) else '0'; dfp_trap_vector(819) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= VIR_ADDR31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(820) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(821) <= '1' when (R.F.PC ( 31 DOWNTO 12 ) /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(822) <= '1' when (R.D.INST ( 0 ) /= ICO_DATA0_intermed_1) else '0'; dfp_trap_vector(823) <= '1' when (R.D.INST ( 0 ) /= RIN_D_INST0_intermed_1) else '0'; dfp_trap_vector(824) <= '1' when (R.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_2) else '0'; dfp_trap_vector(825) <= '1' when (R.D.INST ( 0 ) /= R_D_INST0_intermed_2) else '0'; dfp_trap_vector(826) <= '1' when (R.D.INST ( 0 ) /= RIN_D_INST0_intermed_2) else '0'; dfp_trap_vector(827) <= '1' when (R.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_1) else '0'; dfp_trap_vector(828) <= '1' when (R.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_2) else '0'; dfp_trap_vector(829) <= '1' when (R.D.INST ( 1 ) /= RIN_D_INST1_intermed_1) else '0'; dfp_trap_vector(830) <= '1' when (R.D.INST ( 1 ) /= RIN_D_INST1_intermed_2) else '0'; dfp_trap_vector(831) <= '1' when (R.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_1) else '0'; dfp_trap_vector(832) <= '1' when (R.D.INST ( 1 ) /= R_D_INST1_intermed_2) else '0'; dfp_trap_vector(833) <= '1' when (R.D.INST ( 1 ) /= ICO_DATA1_intermed_1) else '0'; dfp_trap_vector(834) <= '1' when (R.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(835) <= '1' when (R.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(836) <= '1' when (R.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(837) <= '1' when (R.X.DATA ( 0 )( 31 ) /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(838) <= '1' when (R.X.DATA ( 0 )( 31 ) /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(839) <= '1' when (R.X.DATA ( 0 )( 31 ) /= R_X_DATA031_intermed_2) else '0'; dfp_trap_vector(840) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0'; dfp_trap_vector(841) <= '1' when (RIN.X.DATA ( 1 ) /= DCO.DATA ( 1 )) else '0'; dfp_trap_vector(842) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow_intermed_1) else '0'; dfp_trap_vector(843) <= '1' when (RIN.X.DATA ( 1 ) /= R_X_DATA1_intermed_1) else '0'; dfp_trap_vector(844) <= '1' when (RIN.X.DATA ( 1 ) /= R.X.DATA ( 1 )) else '0'; dfp_trap_vector(845) <= '1' when (RIN.X.DATA ( 1 ) /= RIN_X_DATA1_intermed_2) else '0'; dfp_trap_vector(846) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(847) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R.F.PC ( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(848) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(849) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(850) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(851) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(852) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= IRIN_ADDR31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(853) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(854) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0'; dfp_trap_vector(855) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(856) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(857) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(858) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= IR_ADDR31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(859) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(860) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0'; dfp_trap_vector(861) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(862) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(863) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0'; dfp_trap_vector(864) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_F_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(865) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_D_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(866) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(867) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(868) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(869) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= RIN_D_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(870) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(871) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0'; dfp_trap_vector(872) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(873) <= '1' when (RIN.D.INST ( 0 ) /= ICO.DATA ( 0 )) else '0'; dfp_trap_vector(874) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow_intermed_1) else '0'; dfp_trap_vector(875) <= '1' when (RIN.D.INST ( 0 ) /= R_D_INST0_intermed_1) else '0'; dfp_trap_vector(876) <= '1' when (RIN.D.INST ( 0 ) /= RIN_D_INST0_intermed_2) else '0'; dfp_trap_vector(877) <= '1' when (RIN.D.INST ( 0 ) /= R.D.INST ( 0 )) else '0'; dfp_trap_vector(878) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0'; dfp_trap_vector(879) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow_intermed_1) else '0'; dfp_trap_vector(880) <= '1' when (RIN.D.INST ( 1 ) /= RIN_D_INST1_intermed_2) else '0'; dfp_trap_vector(881) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0'; dfp_trap_vector(882) <= '1' when (RIN.D.INST ( 1 ) /= R_D_INST1_intermed_1) else '0'; dfp_trap_vector(883) <= '1' when (RIN.D.INST ( 1 ) /= R.D.INST ( 1 )) else '0'; dfp_trap_vector(884) <= '1' when (RIN.D.INST ( 1 ) /= ICO.DATA ( 1 )) else '0'; dfp_trap_vector(885) <= '1' when (R.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_2) else '0'; dfp_trap_vector(886) <= '1' when (R.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_1) else '0'; dfp_trap_vector(887) <= '1' when (R.X.DATA ( 0 )( 3 ) /= DCO_DATA03_intermed_1) else '0'; dfp_trap_vector(888) <= '1' when (R.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_1) else '0'; dfp_trap_vector(889) <= '1' when (R.X.DATA ( 0 )( 3 ) /= R_X_DATA03_intermed_2) else '0'; dfp_trap_vector(890) <= '1' when (R.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(891) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow_intermed_1) else '0'; dfp_trap_vector(892) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0'; dfp_trap_vector(893) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= DCO.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(894) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= R.X.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(895) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= R_X_DATA03_intermed_1) else '0'; dfp_trap_vector(896) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(897) <= '1' when (R.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(898) <= '1' when (R.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(899) <= '1' when (R.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(900) <= '1' when (R.A.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(901) <= '1' when (R.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(902) <= '1' when (R.A.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(903) <= '1' when (R.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_1) else '0'; dfp_trap_vector(904) <= '1' when (R.X.DATA ( 0 )( 0 ) /= DCO_DATA00_intermed_1) else '0'; dfp_trap_vector(905) <= '1' when (R.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(906) <= '1' when (R.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(907) <= '1' when (R.X.DATA ( 0 )( 0 ) /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(908) <= '1' when (R.X.DATA ( 0 )( 0 ) /= R_X_DATA00_intermed_2) else '0'; dfp_trap_vector(909) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(910) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= R_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(911) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= DCO_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(912) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(913) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= RIN_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(914) <= '1' when (R.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(915) <= '1' when (R.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(916) <= '1' when (R.A.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(917) <= '1' when (R.A.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(918) <= '1' when (R.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(919) <= '1' when (R.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(920) <= '1' when (R.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(921) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0'; dfp_trap_vector(922) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(923) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(924) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= DE_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(925) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(926) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(927) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(928) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= DE_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(929) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(930) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0'; dfp_trap_vector(931) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(932) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0'; dfp_trap_vector(933) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(934) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(935) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(936) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(937) <= '1' when (R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(938) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(939) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(940) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(941) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(942) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0'; dfp_trap_vector(943) <= '1' when (NPC_shadow /= RIN_F_PC_intermed_1) else '0'; dfp_trap_vector(944) <= '1' when (NPC_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(945) <= '1' when (NPC_shadow /= XC_TRAP_ADDRESS_shadow_intermed_1) else '0'; dfp_trap_vector(946) <= '1' when (NPC_shadow /= R.F.PC) else '0'; dfp_trap_vector(947) <= '1' when (NPC_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0'; dfp_trap_vector(948) <= '1' when (NPC_shadow /= "000000000000000000000000000000") else '0'; dfp_trap_vector(949) <= '1' when (NPC_shadow /= V_F_PC_shadow_intermed_1) else '0'; dfp_trap_vector(950) <= '1' when (DE_REN1_shadow /= RIN_A_RFE1_intermed_1) else '0'; dfp_trap_vector(951) <= '1' when (DE_REN1_shadow /= V_A_RFE1_shadow_intermed_1) else '0'; dfp_trap_vector(952) <= '1' when (DE_REN1_shadow /= R.A.RFE1) else '0'; dfp_trap_vector(953) <= '1' when (DE_REN1_shadow /= '1') else '0'; dfp_trap_vector(954) <= '1' when (DE_REN2_shadow /= RIN_A_RFE2_intermed_1) else '0'; dfp_trap_vector(955) <= '1' when (DE_REN2_shadow /= V_A_RFE2_shadow_intermed_1) else '0'; dfp_trap_vector(956) <= '1' when (DE_REN2_shadow /= R.A.RFE2) else '0'; dfp_trap_vector(957) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(958) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(959) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_E_OP1_shadow_intermed_1) else '0'; dfp_trap_vector(960) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_E_OP2_shadow_intermed_1) else '0'; dfp_trap_vector(961) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_E_OP2_intermed_1) else '0'; dfp_trap_vector(962) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_E_OP1_intermed_1) else '0'; dfp_trap_vector(963) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(964) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= EX_OP1_shadow) else '0'; dfp_trap_vector(965) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= EX_OP2_shadow) else '0'; dfp_trap_vector(966) <= '1' when (EX_ADD_RES_shadow(0) /= V_E_ALUCIN_shadow_intermed_1) else '0'; dfp_trap_vector(967) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(968) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(969) <= '1' when (EX_ADD_RES_shadow(0) /= R.E.ALUCIN) else '0'; dfp_trap_vector(970) <= '1' when (EX_ADD_RES_shadow(0) /= RIN_E_ALUCIN_intermed_1) else '0'; dfp_trap_vector(971) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= X"00000001") else '0'; dfp_trap_vector(972) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.E.OP2) else '0'; dfp_trap_vector(973) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(974) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(975) <= '1' when (EX_ADD_RES_shadow(31 downto 0) /= R.E.OP1) else '0'; dfp_trap_vector(976) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(977) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_1) else '0'; dfp_trap_vector(978) <= '1' when (EX_YMSB_shadow /= DCO_DATA00_intermed_1) else '0'; dfp_trap_vector(979) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(980) <= '1' when (EX_YMSB_shadow /= R.X.DATA ( 0 ) ( 0 )) else '0'; dfp_trap_vector(981) <= '1' when (EX_YMSB_shadow /= V_E_YMSB_shadow_intermed_1) else '0'; dfp_trap_vector(982) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_1) else '0'; dfp_trap_vector(983) <= '1' when (EX_YMSB_shadow /= V_X_DATA00_shadow_intermed_3) else '0'; dfp_trap_vector(984) <= '1' when (EX_YMSB_shadow /= R.E.YMSB) else '0'; dfp_trap_vector(985) <= '1' when (EX_YMSB_shadow /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(986) <= '1' when (EX_YMSB_shadow /= RIN_X_DATA00_intermed_3) else '0'; dfp_trap_vector(987) <= '1' when (EX_YMSB_shadow /= R_X_DATA00_intermed_2) else '0'; dfp_trap_vector(988) <= '1' when (EX_YMSB_shadow /= RIN_E_YMSB_intermed_1) else '0'; dfp_trap_vector(989) <= '1' when (EX_OP1_shadow /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(990) <= '1' when (EX_OP1_shadow /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(991) <= '1' when (EX_OP1_shadow /= V_E_OP1_shadow_intermed_1) else '0'; dfp_trap_vector(992) <= '1' when (EX_OP1_shadow /= RIN_E_OP1_intermed_1) else '0'; dfp_trap_vector(993) <= '1' when (EX_OP1_shadow /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(994) <= '1' when (EX_OP1_shadow /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(995) <= '1' when (EX_OP1_shadow /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(996) <= '1' when (EX_OP1_shadow /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(997) <= '1' when (EX_OP1_shadow /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(998) <= '1' when (EX_OP1_shadow /= R.E.OP1) else '0'; dfp_trap_vector(999) <= '1' when (EX_OP2_shadow /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(1000) <= '1' when (EX_OP2_shadow /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1001) <= '1' when (EX_OP2_shadow /= V_E_OP2_shadow_intermed_1) else '0'; dfp_trap_vector(1002) <= '1' when (EX_OP2_shadow /= RIN_E_OP2_intermed_1) else '0'; dfp_trap_vector(1003) <= '1' when (EX_OP2_shadow /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(1004) <= '1' when (EX_OP2_shadow /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1005) <= '1' when (EX_OP2_shadow /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(1006) <= '1' when (EX_OP2_shadow /= R.E.OP2) else '0'; dfp_trap_vector(1007) <= '1' when (EX_OP2_shadow /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(1008) <= '1' when (EX_OP2_shadow /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(1009) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1010) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(1011) <= '1' when (EX_SHCNT_shadow /= R.E.SHCNT) else '0'; dfp_trap_vector(1012) <= '1' when (EX_SHCNT_shadow /= R_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1013) <= '1' when (EX_SHCNT_shadow /= V_E_SHCNT_shadow_intermed_1) else '0'; dfp_trap_vector(1014) <= '1' when (EX_SHCNT_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1015) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1016) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1017) <= '1' when (EX_SHCNT_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1018) <= '1' when (EX_SHCNT_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1019) <= '1' when (EX_SHCNT_shadow /= RIN_E_SHCNT_intermed_1) else '0'; dfp_trap_vector(1020) <= '1' when (EX_SHCNT_shadow /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(1021) <= '1' when (EX_SHCNT_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1022) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(1023) <= '1' when (EX_SARI_shadow /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(1024) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(1025) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(1026) <= '1' when (EX_SARI_shadow /= R.E.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(1027) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(1028) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(1029) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(1030) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_3) else '0'; dfp_trap_vector(1031) <= '1' when (EX_SARI_shadow /= R.X.DATA ( 0 ) ( 31 )) else '0'; dfp_trap_vector(1032) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(1033) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_3) else '0'; dfp_trap_vector(1034) <= '1' when (EX_SARI_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(1035) <= '1' when (EX_SARI_shadow /= V_E_SARI_shadow_intermed_1) else '0'; dfp_trap_vector(1036) <= '1' when (EX_SARI_shadow /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1037) <= '1' when (EX_SARI_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(1038) <= '1' when (EX_SARI_shadow /= R_X_DATA031_intermed_2) else '0'; dfp_trap_vector(1039) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(1040) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(1041) <= '1' when (EX_SARI_shadow /= R_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(1042) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(1043) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST20_intermed_3) else '0'; dfp_trap_vector(1044) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(1045) <= '1' when (EX_SARI_shadow /= R.E.SARI) else '0'; dfp_trap_vector(1046) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(1047) <= '1' when (EX_SARI_shadow /= V_E_CTRL_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(1048) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1049) <= '1' when (EX_SARI_shadow /= DE_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(1050) <= '1' when (EX_SARI_shadow /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(1051) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1052) <= '1' when (EX_SARI_shadow /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(1053) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST20_shadow_intermed_3) else '0'; dfp_trap_vector(1054) <= '1' when (EX_SARI_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(1055) <= '1' when (EX_SARI_shadow /= RIN_E_SARI_intermed_1) else '0'; dfp_trap_vector(1056) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(1057) <= '1' when (EX_SARI_shadow /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(1058) <= '1' when (EX_SARI_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(1059) <= '1' when (EX_SARI_shadow /= R_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(1060) <= '1' when (EX_SARI_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(1061) <= '1' when (ME_SIGNED_shadow /= V_M_DCI_SIGNED_shadow_intermed_2) else '0'; dfp_trap_vector(1062) <= '1' when (ME_SIGNED_shadow /= RIN_M_DCI_SIGNED_intermed_2) else '0'; dfp_trap_vector(1063) <= '1' when (ME_SIGNED_shadow /= R_M_DCI_SIGNED_intermed_1) else '0'; dfp_trap_vector(1064) <= '1' when (ME_SIGNED_shadow /= R.X.DCI.SIGNED) else '0'; dfp_trap_vector(1065) <= '1' when (ME_SIGNED_shadow /= V_X_DCI_SIGNED_shadow_intermed_1) else '0'; dfp_trap_vector(1066) <= '1' when (ME_SIGNED_shadow /= RIN_X_DCI_SIGNED_intermed_1) else '0'; dfp_trap_vector(1067) <= '1' when (ME_SIZE_shadow /= R.X.DCI.SIZE) else '0'; dfp_trap_vector(1068) <= '1' when (ME_SIZE_shadow /= RIN_M_DCI_SIZE_intermed_2) else '0'; dfp_trap_vector(1069) <= '1' when (ME_SIZE_shadow /= V_M_DCI_SIZE_shadow_intermed_2) else '0'; dfp_trap_vector(1070) <= '1' when (ME_SIZE_shadow /= R_M_DCI_SIZE_intermed_1) else '0'; dfp_trap_vector(1071) <= '1' when (ME_SIZE_shadow /= V_X_DCI_SIZE_shadow_intermed_1) else '0'; dfp_trap_vector(1072) <= '1' when (ME_SIZE_shadow /= RIN_X_DCI_SIZE_intermed_1) else '0'; dfp_trap_vector(1073) <= '1' when (ME_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(1074) <= '1' when (ME_LADDR_shadow /= RIN_X_LADDR_intermed_1) else '0'; dfp_trap_vector(1075) <= '1' when (ME_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1076) <= '1' when (ME_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1077) <= '1' when (ME_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1078) <= '1' when (ME_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1079) <= '1' when (ME_LADDR_shadow /= V_X_LADDR_shadow_intermed_1) else '0'; dfp_trap_vector(1080) <= '1' when (ME_LADDR_shadow /= R.X.LADDR) else '0'; dfp_trap_vector(1081) <= '1' when (ME_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1082) <= '1' when (XC_RESULT_shadow /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(1083) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1084) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1085) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1086) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1087) <= '1' when (XC_RESULT_shadow /= RIN_X_RESULT_intermed_1) else '0'; dfp_trap_vector(1088) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1089) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1090) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1091) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1092) <= '1' when (XC_RESULT_shadow /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1093) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1094) <= '1' when (XC_RESULT_shadow /= V_X_RESULT_shadow_intermed_1) else '0'; dfp_trap_vector(1095) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1096) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1097) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1098) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1099) <= '1' when (XC_RESULT_shadow /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(1100) <= '1' when (XC_RESULT_shadow /= R.X.RESULT) else '0'; dfp_trap_vector(1101) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1102) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1103) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1104) <= '1' when (XC_RESULT_shadow /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1105) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1106) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1107) <= '1' when (XC_RESULT_shadow /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(1108) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1109) <= '1' when (XC_RESULT_shadow /= X"00000000") else '0'; dfp_trap_vector(1110) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(1111) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1112) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1113) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1114) <= '1' when (XC_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1115) <= '1' when (XC_RESULT_shadow /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(1116) <= '1' when (XC_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1117) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1118) <= '1' when (XC_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1119) <= '1' when (XC_RESULT_shadow /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(1120) <= '1' when (XC_EXCEPTION_shadow /= '1') else '0'; dfp_trap_vector(1121) <= '1' when (XC_EXCEPTION_shadow /= '0') else '0'; dfp_trap_vector(1122) <= '1' when (XC_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0'; dfp_trap_vector(1123) <= '1' when (XC_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0'; dfp_trap_vector(1124) <= '1' when (XC_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1125) <= '1' when (XC_WREG_shadow /= R.X.CTRL.WREG) else '0'; dfp_trap_vector(1126) <= '1' when (XC_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(1127) <= '1' when (XC_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0'; dfp_trap_vector(1128) <= '1' when (XC_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0'; dfp_trap_vector(1129) <= '1' when (XC_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(1130) <= '1' when (XC_WREG_shadow /= V_X_CTRL_WREG_shadow_intermed_1) else '0'; dfp_trap_vector(1131) <= '1' when (XC_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(1132) <= '1' when (XC_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1133) <= '1' when (XC_WREG_shadow /= '1') else '0'; dfp_trap_vector(1134) <= '1' when (XC_WREG_shadow /= '0') else '0'; dfp_trap_vector(1135) <= '1' when (XC_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0'; dfp_trap_vector(1136) <= '1' when (XC_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(1137) <= '1' when (XC_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(1138) <= '1' when (XC_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0'; dfp_trap_vector(1139) <= '1' when (XC_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0'; dfp_trap_vector(1140) <= '1' when (XC_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0'; dfp_trap_vector(1141) <= '1' when (XC_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(1142) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(1143) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0'; dfp_trap_vector(1144) <= '1' when (XC_VECTT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1145) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0'; dfp_trap_vector(1146) <= '1' when (XC_VECTT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1147) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1148) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(1149) <= '1' when (XC_VECTT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1150) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1151) <= '1' when (XC_VECTT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0'; dfp_trap_vector(1152) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1153) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1154) <= '1' when (XC_VECTT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1155) <= '1' when (XC_VECTT_shadow /= "00000000") else '0'; dfp_trap_vector(1156) <= '1' when (XC_VECTT_shadow /= "00001001") else '0'; dfp_trap_vector(1157) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1158) <= '1' when (XC_VECTT_shadow /= X"00") else '0'; dfp_trap_vector(1159) <= '1' when (XC_VECTT_shadow /= X"01") else '0'; dfp_trap_vector(1160) <= '1' when (XC_VECTT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0'; dfp_trap_vector(1161) <= '1' when (XC_VECTT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1162) <= '1' when (XC_VECTT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1163) <= '1' when (XC_VECTT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(1164) <= '1' when (XC_TRAP_shadow /= R.X.CTRL.TRAP) else '0'; dfp_trap_vector(1165) <= '1' when (XC_TRAP_shadow /= V_M_CTRL_TRAP_shadow_intermed_2) else '0'; dfp_trap_vector(1166) <= '1' when (XC_TRAP_shadow /= RIN_X_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(1167) <= '1' when (XC_TRAP_shadow /= V_X_CTRL_TRAP_shadow_intermed_1) else '0'; dfp_trap_vector(1168) <= '1' when (XC_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_4) else '0'; dfp_trap_vector(1169) <= '1' when (XC_TRAP_shadow /= V_X_MEXC_shadow_intermed_1) else '0'; dfp_trap_vector(1170) <= '1' when (XC_TRAP_shadow /= V_D_MEXC_shadow_intermed_5) else '0'; dfp_trap_vector(1171) <= '1' when (XC_TRAP_shadow /= R_A_CTRL_TRAP_intermed_3) else '0'; dfp_trap_vector(1172) <= '1' when (XC_TRAP_shadow /= RIN_X_MEXC_intermed_1) else '0'; dfp_trap_vector(1173) <= '1' when (XC_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(1174) <= '1' when (XC_TRAP_shadow /= R_M_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(1175) <= '1' when (XC_TRAP_shadow /= ICO_MEXC_intermed_5) else '0'; dfp_trap_vector(1176) <= '1' when (XC_TRAP_shadow /= R_E_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(1177) <= '1' when (XC_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_4) else '0'; dfp_trap_vector(1178) <= '1' when (XC_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_3) else '0'; dfp_trap_vector(1179) <= '1' when (XC_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_3) else '0'; dfp_trap_vector(1180) <= '1' when (XC_TRAP_shadow /= R.X.MEXC) else '0'; dfp_trap_vector(1181) <= '1' when (XC_TRAP_shadow /= RIN_D_MEXC_intermed_5) else '0'; dfp_trap_vector(1182) <= '1' when (XC_TRAP_shadow /= R_D_MEXC_intermed_4) else '0'; dfp_trap_vector(1183) <= '1' when (XC_TRAP_shadow /= DCO_MEXC_intermed_1) else '0'; dfp_trap_vector(1184) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0'; dfp_trap_vector(1185) <= '1' when (XC_HALT_shadow /= '0') else '0'; dfp_trap_vector(1186) <= '1' when (DSIGN_shadow /= DE_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(1187) <= '1' when (DSIGN_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(1188) <= '1' when (DSIGN_shadow /= V_E_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(1189) <= '1' when (DSIGN_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(1190) <= '1' when (DSIGN_shadow /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1191) <= '1' when (DSIGN_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1192) <= '1' when (DSIGN_shadow /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1193) <= '1' when (DSIGN_shadow /= R.A.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(1194) <= '1' when (DSIGN_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(1195) <= '1' when (DSIGN_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(1196) <= '1' when (DSIGN_shadow /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(1197) <= '1' when (DSIGN_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(1198) <= '1' when (DSIGN_shadow /= V_A_CTRL_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(1199) <= '1' when (SIDLE_shadow /= VP_ERROR_shadow_intermed_1) else '0'; dfp_trap_vector(1200) <= '1' when (SIDLE_shadow /= ICO.IDLE) else '0'; dfp_trap_vector(1201) <= '1' when (SIDLE_shadow /= RPIN_PWD_intermed_1) else '0'; dfp_trap_vector(1202) <= '1' when (SIDLE_shadow /= V_X_DEBUG_shadow_intermed_1) else '0'; dfp_trap_vector(1203) <= '1' when (SIDLE_shadow /= RP.PWD) else '0'; dfp_trap_vector(1204) <= '1' when (SIDLE_shadow /= VP_PWD_shadow_intermed_1) else '0'; dfp_trap_vector(1205) <= '1' when (SIDLE_shadow /= DCO.IDLE) else '0'; dfp_trap_vector(1206) <= '1' when (SIDLE_shadow /= '1') else '0'; dfp_trap_vector(1207) <= '1' when (SIDLE_shadow /= R.X.DEBUG) else '0'; dfp_trap_vector(1208) <= '1' when (SIDLE_shadow /= '0') else '0'; dfp_trap_vector(1209) <= '1' when (SIDLE_shadow /= RPIN_ERROR_intermed_1) else '0'; dfp_trap_vector(1210) <= '1' when (SIDLE_shadow /= RP.ERROR) else '0'; dfp_trap_vector(1211) <= '1' when (SIDLE_shadow /= RIN_X_DEBUG_intermed_1) else '0'; dfp_trap_vector(1212) <= '1' when (ICNT_shadow /= HOLDN) else '0'; dfp_trap_vector(1213) <= '1' when (ICNT_shadow /= '0') else '0'; dfp_trap_vector(1214) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0'; dfp_trap_vector(1215) <= '1' when (V_X_NERROR_shadow /= R.X.NERROR) else '0'; dfp_trap_vector(1216) <= '1' when (V_X_NERROR_shadow /= RIN_X_NERROR_intermed_1) else '0'; dfp_trap_vector(1217) <= '1' when (V_X_NERROR_shadow /= '1') else '0'; dfp_trap_vector(1218) <= '1' when (V_X_NERROR_shadow /= '0') else '0'; dfp_trap_vector(1219) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0'; dfp_trap_vector(1220) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0'; dfp_trap_vector(1221) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_F_PC31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(1222) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_X_CTRL_TT_shadow_intermed_1) else '0'; dfp_trap_vector(1223) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_E_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(1224) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0'; dfp_trap_vector(1225) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_A_CTRL_TT_intermed_4) else '0'; dfp_trap_vector(1226) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(1227) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(1228) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(1229) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1230) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(11 downto 4) /= XC_VECTT_shadow) else '0'; dfp_trap_vector(1231) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1232) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(1233) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(1234) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1235) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0'; dfp_trap_vector(1236) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1237) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(1238) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(1239) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(1240) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(1241) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0'; dfp_trap_vector(1242) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000001") else '0'; dfp_trap_vector(1243) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= R.X.CTRL.TT) else '0'; dfp_trap_vector(1244) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= V_W_S_TBA_shadow_intermed_1) else '0'; dfp_trap_vector(1245) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_M_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1246) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(1247) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0'; dfp_trap_vector(1248) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0'; dfp_trap_vector(1249) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1250) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(1251) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(1252) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1253) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1254) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= R.W.S.TBA) else '0'; dfp_trap_vector(1255) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_E_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1256) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(10 downto 4) /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1257) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_M_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(1258) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(1259) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(1260) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= V_A_CTRL_TT_shadow_intermed_4) else '0'; dfp_trap_vector(1261) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(1262) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(1263) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(9 downto 4) /= RIN_X_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1264) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0001001") else '0'; dfp_trap_vector(1265) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0'; dfp_trap_vector(1266) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(1267) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(1268) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow(23 downto 4) /= RIN_W_S_TBA_intermed_1) else '0'; dfp_trap_vector(1269) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0'; dfp_trap_vector(1270) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= X"0000000") else '0'; dfp_trap_vector(1271) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(1272) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(1273) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(1274) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1275) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0'; dfp_trap_vector(1276) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1277) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1278) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1279) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1280) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1281) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(1282) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1283) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1284) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1285) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1286) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(1287) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(1288) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1289) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_F_PC3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1290) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(1291) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= "00") else '0'; dfp_trap_vector(1292) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1293) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1294) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1295) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1296) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1297) <= '1' when (V_X_ANNUL_ALL_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1298) <= '1' when (V_X_ANNUL_ALL_shadow /= '1') else '0'; dfp_trap_vector(1299) <= '1' when (V_X_ANNUL_ALL_shadow /= '0') else '0'; dfp_trap_vector(1300) <= '1' when (V_X_ANNUL_ALL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1301) <= '1' when (V_X_DEBUG_shadow /= '1') else '0'; dfp_trap_vector(1302) <= '1' when (V_X_DEBUG_shadow /= R.X.DEBUG) else '0'; dfp_trap_vector(1303) <= '1' when (V_X_DEBUG_shadow /= '0') else '0'; dfp_trap_vector(1304) <= '1' when (V_X_DEBUG_shadow /= RIN_X_DEBUG_intermed_1) else '0'; dfp_trap_vector(1305) <= '1' when (VIR_ADDR_shadow /= RIN_D_PC_intermed_5) else '0'; dfp_trap_vector(1306) <= '1' when (VIR_ADDR_shadow /= RIN_A_CTRL_PC_intermed_4) else '0'; dfp_trap_vector(1307) <= '1' when (VIR_ADDR_shadow /= R_A_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(1308) <= '1' when (VIR_ADDR_shadow /= V_E_CTRL_PC_shadow_intermed_3) else '0'; dfp_trap_vector(1309) <= '1' when (VIR_ADDR_shadow /= IR.ADDR) else '0'; dfp_trap_vector(1310) <= '1' when (VIR_ADDR_shadow /= R_M_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(1311) <= '1' when (VIR_ADDR_shadow /= R.X.CTRL.PC) else '0'; dfp_trap_vector(1312) <= '1' when (VIR_ADDR_shadow /= R_E_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(1313) <= '1' when (VIR_ADDR_shadow /= RIN_M_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(1314) <= '1' when (VIR_ADDR_shadow /= V_X_CTRL_PC_shadow_intermed_1) else '0'; dfp_trap_vector(1315) <= '1' when (VIR_ADDR_shadow /= V_M_CTRL_PC_shadow_intermed_2) else '0'; dfp_trap_vector(1316) <= '1' when (VIR_ADDR_shadow /= V_A_CTRL_PC_shadow_intermed_4) else '0'; dfp_trap_vector(1317) <= '1' when (VIR_ADDR_shadow /= R_D_PC_intermed_4) else '0'; dfp_trap_vector(1318) <= '1' when (VIR_ADDR_shadow /= RIN_E_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(1319) <= '1' when (VIR_ADDR_shadow /= RIN_X_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(1320) <= '1' when (VIR_ADDR_shadow /= V_D_PC_shadow_intermed_5) else '0'; dfp_trap_vector(1321) <= '1' when (VIR_ADDR_shadow /= IRIN_ADDR_intermed_1) else '0'; dfp_trap_vector(1322) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(1323) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0'; dfp_trap_vector(1324) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0'; dfp_trap_vector(1325) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1326) <= '1' when (VDSU_TT_shadow /= XC_VECTT_shadow) else '0'; dfp_trap_vector(1327) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1328) <= '1' when (VDSU_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1329) <= '1' when (VDSU_TT_shadow /= DSUIN_TT_intermed_1) else '0'; dfp_trap_vector(1330) <= '1' when (VDSU_TT_shadow /= X"00") else '0'; dfp_trap_vector(1331) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1332) <= '1' when (VDSU_TT_shadow /= X"01") else '0'; dfp_trap_vector(1333) <= '1' when (VDSU_TT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0'; dfp_trap_vector(1334) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1335) <= '1' when (VDSU_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1336) <= '1' when (VDSU_TT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(1337) <= '1' when (VDSU_TT_shadow /= DSUR.TT) else '0'; dfp_trap_vector(1338) <= '1' when (VDSU_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1339) <= '1' when (VDSU_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1340) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1341) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(1342) <= '1' when (VDSU_TT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1343) <= '1' when (VDSU_TT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0'; dfp_trap_vector(1344) <= '1' when (VDSU_TT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1345) <= '1' when (VDSU_TT_shadow /= "00001001") else '0'; dfp_trap_vector(1346) <= '1' when (VDSU_TT_shadow /= X"00") else '0'; dfp_trap_vector(1347) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0'; dfp_trap_vector(1348) <= '1' when (VP_PWD_shadow /= '1') else '0'; dfp_trap_vector(1349) <= '1' when (VP_PWD_shadow /= '0') else '0'; dfp_trap_vector(1350) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0'; dfp_trap_vector(1351) <= '1' when (VIR_PWD_shadow /= '1') else '0'; dfp_trap_vector(1352) <= '1' when (VIR_PWD_shadow /= '0') else '0'; dfp_trap_vector(1353) <= '1' when (VIR_PWD_shadow /= IRIN_PWD_intermed_1) else '0'; dfp_trap_vector(1354) <= '1' when (VIR_PWD_shadow /= IR.PWD) else '0'; dfp_trap_vector(1355) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_E_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(1356) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_X_CTRL_TT_shadow_intermed_1) else '0'; dfp_trap_vector(1357) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_A_CTRL_TT_intermed_4) else '0'; dfp_trap_vector(1358) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1359) <= '1' when (V_W_S_TT_shadow /= XC_VECTT_shadow) else '0'; dfp_trap_vector(1360) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1361) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1362) <= '1' when (V_W_S_TT_shadow /= "00000000") else '0'; dfp_trap_vector(1363) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1364) <= '1' when (V_W_S_TT_shadow /= X"01") else '0'; dfp_trap_vector(1365) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= R.X.CTRL.TT) else '0'; dfp_trap_vector(1366) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_M_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1367) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1368) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(1369) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1370) <= '1' when (V_W_S_TT_shadow /= R.W.S.TT) else '0'; dfp_trap_vector(1371) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1372) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_E_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1373) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_M_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(1374) <= '1' when (V_W_S_TT_shadow(6 downto 0) /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1375) <= '1' when (V_W_S_TT_shadow /= RIN_W_S_TT_intermed_1) else '0'; dfp_trap_vector(1376) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= V_A_CTRL_TT_shadow_intermed_4) else '0'; dfp_trap_vector(1377) <= '1' when (V_W_S_TT_shadow(5 downto 0) /= RIN_X_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1378) <= '1' when (V_W_S_TT_shadow /= "00001001") else '0'; dfp_trap_vector(1379) <= '1' when (V_W_S_TT_shadow /= X"00") else '0'; dfp_trap_vector(1380) <= '1' when (V_W_S_PS_shadow /= '1') else '0'; dfp_trap_vector(1381) <= '1' when (V_W_S_PS_shadow /= R.W.S.S) else '0'; dfp_trap_vector(1382) <= '1' when (V_W_S_PS_shadow /= RIN_W_S_S_intermed_1) else '0'; dfp_trap_vector(1383) <= '1' when (V_W_S_PS_shadow /= RIN_W_S_PS_intermed_1) else '0'; dfp_trap_vector(1384) <= '1' when (V_W_S_PS_shadow /= R.W.S.PS) else '0'; dfp_trap_vector(1385) <= '1' when (V_W_S_PS_shadow /= V_W_S_S_shadow_intermed_1) else '0'; dfp_trap_vector(1386) <= '1' when (V_W_S_S_shadow /= '1') else '0'; dfp_trap_vector(1387) <= '1' when (V_W_S_S_shadow /= R.W.S.S) else '0'; dfp_trap_vector(1388) <= '1' when (V_W_S_S_shadow /= RIN_W_S_S_intermed_1) else '0'; dfp_trap_vector(1389) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1390) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1391) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_X_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1392) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_X_CTRL_RD6DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1393) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= RIN_W_S_CWP_intermed_1) else '0'; dfp_trap_vector(1394) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R.X.CTRL.RD( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(1395) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000001") else '0'; dfp_trap_vector(1396) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_M_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1397) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000001") else '0'; dfp_trap_vector(1398) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1399) <= '1' when (XC_WADDR6DOWNTO0_shadow /= "0000010") else '0'; dfp_trap_vector(1400) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(1401) <= '1' when (XC_WADDR6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(1402) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1403) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= R.W.S.CWP) else '0'; dfp_trap_vector(1404) <= '1' when (XC_WADDR6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_4) else '0'; dfp_trap_vector(1405) <= '1' when (XC_WADDR6DOWNTO0_shadow /= R_M_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1406) <= '1' when (XC_WADDR6DOWNTO0_shadow(2 downto 0) /= V_W_S_CWP_shadow_intermed_1) else '0'; dfp_trap_vector(1407) <= '1' when (V_W_S_ET_shadow /= '0') else '0'; dfp_trap_vector(1408) <= '1' when (V_W_S_ET_shadow /= RIN_W_S_ET_intermed_1) else '0'; dfp_trap_vector(1409) <= '1' when (V_W_S_ET_shadow /= R.W.S.ET) else '0'; dfp_trap_vector(1410) <= '1' when (V_W_S_CWP_shadow /= RIN_W_S_CWP_intermed_1) else '0'; dfp_trap_vector(1411) <= '1' when (V_W_S_CWP_shadow /= "001") else '0'; dfp_trap_vector(1412) <= '1' when (V_W_S_CWP_shadow /= R.W.S.CWP) else '0'; dfp_trap_vector(1413) <= '1' when (VP_ERROR_shadow /= '1') else '0'; dfp_trap_vector(1414) <= '1' when (VP_ERROR_shadow /= '0') else '0'; dfp_trap_vector(1415) <= '1' when (VP_ERROR_shadow /= RP.ERROR) else '0'; dfp_trap_vector(1416) <= '1' when (VP_ERROR_shadow /= RPIN_ERROR_intermed_1) else '0'; dfp_trap_vector(1417) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC_intermed_6) else '0'; dfp_trap_vector(1418) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1419) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR_shadow_intermed_1) else '0'; dfp_trap_vector(1420) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC_intermed_5) else '0'; dfp_trap_vector(1421) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC_intermed_4) else '0'; dfp_trap_vector(1422) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(1423) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC_shadow_intermed_4) else '0'; dfp_trap_vector(1424) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(1425) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= XC_TRAP_ADDRESS_shadow_intermed_1) else '0'; dfp_trap_vector(1426) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(1427) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(1428) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR.ADDR) else '0'; dfp_trap_vector(1429) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1430) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1431) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(1432) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1433) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(1434) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(1435) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1436) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(1437) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(1438) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(1439) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(1440) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1441) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC_shadow_intermed_2) else '0'; dfp_trap_vector(1442) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1443) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1444) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(1445) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1446) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC_shadow_intermed_3) else '0'; dfp_trap_vector(1447) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1448) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC_shadow_intermed_5) else '0'; dfp_trap_vector(1449) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1450) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC_intermed_5) else '0'; dfp_trap_vector(1451) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC_intermed_1) else '0'; dfp_trap_vector(1452) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1453) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC_intermed_4) else '0'; dfp_trap_vector(1454) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(1455) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC) else '0'; dfp_trap_vector(1456) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC_shadow_intermed_6) else '0'; dfp_trap_vector(1457) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1458) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR_intermed_1) else '0'; dfp_trap_vector(1459) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0'; dfp_trap_vector(1460) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= "000000000000000000000000000000") else '0'; dfp_trap_vector(1461) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1462) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1463) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC_shadow_intermed_1) else '0'; dfp_trap_vector(1464) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1465) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1466) <= '1' when (VDSU_TBUFCNT_shadow /= DSUR.TBUFCNT) else '0'; dfp_trap_vector(1467) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0'; dfp_trap_vector(1468) <= '1' when (VDSU_TBUFCNT_shadow /= DSUIN_TBUFCNT_intermed_1) else '0'; dfp_trap_vector(1469) <= '1' when (V_W_EXCEPT_shadow /= R.W.EXCEPT) else '0'; dfp_trap_vector(1470) <= '1' when (V_W_EXCEPT_shadow /= XC_EXCEPTION_shadow) else '0'; dfp_trap_vector(1471) <= '1' when (V_W_EXCEPT_shadow /= '1') else '0'; dfp_trap_vector(1472) <= '1' when (V_W_EXCEPT_shadow /= RIN_W_EXCEPT_intermed_1) else '0'; dfp_trap_vector(1473) <= '1' when (V_W_EXCEPT_shadow /= '0') else '0'; dfp_trap_vector(1474) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1475) <= '1' when (V_W_RESULT_shadow /= RIN_X_RESULT_intermed_1) else '0'; dfp_trap_vector(1476) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1477) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(1478) <= '1' when (V_W_RESULT_shadow /= R.W.RESULT) else '0'; dfp_trap_vector(1479) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1480) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1481) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1482) <= '1' when (V_W_RESULT_shadow /= V_X_DATA0_shadow_intermed_1) else '0'; dfp_trap_vector(1483) <= '1' when (V_W_RESULT_shadow /= R.X.RESULT) else '0'; dfp_trap_vector(1484) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1485) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1486) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1487) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1488) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1489) <= '1' when (V_W_RESULT_shadow /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(1490) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(1491) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0'; dfp_trap_vector(1492) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(1493) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1494) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1495) <= '1' when (V_W_RESULT_shadow /= DCO_DATA0_intermed_1) else '0'; dfp_trap_vector(1496) <= '1' when (V_W_RESULT_shadow /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(1497) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(1498) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1499) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(1500) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1501) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1502) <= '1' when (V_W_RESULT_shadow /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1503) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1504) <= '1' when (V_W_RESULT_shadow /= V_X_RESULT_shadow_intermed_1) else '0'; dfp_trap_vector(1505) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1506) <= '1' when (V_W_RESULT_shadow /= RIN_W_RESULT_intermed_1) else '0'; dfp_trap_vector(1507) <= '1' when (V_W_RESULT_shadow /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1508) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(1509) <= '1' when (V_W_RESULT_shadow /= X"00000000") else '0'; dfp_trap_vector(1510) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(1511) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(1512) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(1513) <= '1' when (V_W_RESULT_shadow(31 downto 2) /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(1514) <= '1' when (V_W_RESULT_shadow /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(1515) <= '1' when (V_W_WA_shadow /= V_M_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1516) <= '1' when (V_W_WA_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(1517) <= '1' when (V_W_WA_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1518) <= '1' when (V_W_WA_shadow /= V_X_CTRL_RD7DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1519) <= '1' when (V_W_WA_shadow /= R.X.CTRL.RD ( 7 DOWNTO 0 )) else '0'; dfp_trap_vector(1520) <= '1' when (V_W_WA_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(1521) <= '1' when (V_W_WA_shadow /= RIN_W_WA_intermed_1) else '0'; dfp_trap_vector(1522) <= '1' when (V_W_WA_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_4) else '0'; dfp_trap_vector(1523) <= '1' when (V_W_WA_shadow /= R_M_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1524) <= '1' when (V_W_WA_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1525) <= '1' when (V_W_WA_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_3) else '0'; dfp_trap_vector(1526) <= '1' when (V_W_WA_shadow /= RIN_X_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1527) <= '1' when (V_W_WA_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1528) <= '1' when (V_W_WA_shadow /= R.W.WA) else '0'; dfp_trap_vector(1529) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0'; dfp_trap_vector(1530) <= '1' when (V_W_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0'; dfp_trap_vector(1531) <= '1' when (V_W_WREG_shadow /= R.X.CTRL.WREG) else '0'; dfp_trap_vector(1532) <= '1' when (V_W_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(1533) <= '1' when (V_W_WREG_shadow /= R.W.WREG) else '0'; dfp_trap_vector(1534) <= '1' when (V_W_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(1535) <= '1' when (V_W_WREG_shadow /= V_X_CTRL_WREG_shadow_intermed_1) else '0'; dfp_trap_vector(1536) <= '1' when (V_W_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1537) <= '1' when (V_W_WREG_shadow /= '1') else '0'; dfp_trap_vector(1538) <= '1' when (V_W_WREG_shadow /= '0') else '0'; dfp_trap_vector(1539) <= '1' when (V_W_WREG_shadow /= XC_WREG_shadow) else '0'; dfp_trap_vector(1540) <= '1' when (V_W_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(1541) <= '1' when (V_W_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0'; dfp_trap_vector(1542) <= '1' when (V_W_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0'; dfp_trap_vector(1543) <= '1' when (V_W_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(1544) <= '1' when (V_W_WREG_shadow /= RIN_W_WREG_intermed_1) else '0'; dfp_trap_vector(1545) <= '1' when (V_W_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0'; dfp_trap_vector(1546) <= '1' when (V_W_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1547) <= '1' when (V_W_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0'; dfp_trap_vector(1548) <= '1' when (V_W_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0'; dfp_trap_vector(1549) <= '1' when (V_W_WREG_shadow /= HOLDN) else '0'; dfp_trap_vector(1550) <= '1' when (V_W_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(1551) <= '1' when (V_W_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0'; dfp_trap_vector(1552) <= '1' when (V_W_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(1553) <= '1' when (V_W_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0'; dfp_trap_vector(1554) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0'; dfp_trap_vector(1555) <= '1' when (V_W_S_SVT_shadow /= '0') else '0'; dfp_trap_vector(1556) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0'; dfp_trap_vector(1557) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0'; dfp_trap_vector(1558) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0'; dfp_trap_vector(1559) <= '1' when (V_W_S_DWT_shadow /= '0') else '0'; dfp_trap_vector(1560) <= '1' when (V_W_S_EF_shadow /= '0') else '0'; dfp_trap_vector(1561) <= '1' when (V_W_S_EF_shadow /= R.W.S.EF) else '0'; dfp_trap_vector(1562) <= '1' when (V_W_S_EF_shadow /= RIN_W_S_EF_intermed_1) else '0'; dfp_trap_vector(1563) <= '1' when (V_X_CTRL_shadow /= RIN_E_CTRL_intermed_2) else '0'; dfp_trap_vector(1564) <= '1' when (V_X_CTRL_shadow /= R_E_CTRL_intermed_1) else '0'; dfp_trap_vector(1565) <= '1' when (V_X_CTRL_shadow /= RIN_X_CTRL_intermed_1) else '0'; dfp_trap_vector(1566) <= '1' when (V_X_CTRL_shadow /= R.M.CTRL) else '0'; dfp_trap_vector(1567) <= '1' when (V_X_CTRL_shadow /= RIN_M_CTRL_intermed_1) else '0'; dfp_trap_vector(1568) <= '1' when (V_X_CTRL_shadow /= V_E_CTRL_shadow_intermed_2) else '0'; dfp_trap_vector(1569) <= '1' when (V_X_CTRL_shadow /= RIN_A_CTRL_intermed_3) else '0'; dfp_trap_vector(1570) <= '1' when (V_X_CTRL_shadow /= R.X.CTRL) else '0'; dfp_trap_vector(1571) <= '1' when (V_X_CTRL_shadow /= V_M_CTRL_shadow_intermed_1) else '0'; dfp_trap_vector(1572) <= '1' when (V_X_CTRL_shadow /= V_A_CTRL_shadow_intermed_3) else '0'; dfp_trap_vector(1573) <= '1' when (V_X_CTRL_shadow /= R_A_CTRL_intermed_2) else '0'; dfp_trap_vector(1574) <= '1' when (V_X_DCI_shadow /= V_M_DCI_shadow_intermed_1) else '0'; dfp_trap_vector(1575) <= '1' when (V_X_DCI_shadow /= RIN_M_DCI_intermed_1) else '0'; dfp_trap_vector(1576) <= '1' when (V_X_DCI_shadow /= RIN_X_DCI_intermed_1) else '0'; dfp_trap_vector(1577) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0'; dfp_trap_vector(1578) <= '1' when (V_X_DCI_shadow /= R.X.DCI) else '0'; dfp_trap_vector(1579) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0'; dfp_trap_vector(1580) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(1581) <= '1' when (V_X_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1582) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_M_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1583) <= '1' when (V_X_CTRL_RETT_shadow /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1584) <= '1' when (V_X_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_3) else '0'; dfp_trap_vector(1585) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.ANNUL) else '0'; dfp_trap_vector(1586) <= '1' when (V_X_CTRL_RETT_shadow /= '1') else '0'; dfp_trap_vector(1587) <= '1' when (V_X_CTRL_RETT_shadow /= '0') else '0'; dfp_trap_vector(1588) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1589) <= '1' when (V_X_CTRL_RETT_shadow /= V_E_CTRL_RETT_shadow_intermed_2) else '0'; dfp_trap_vector(1590) <= '1' when (V_X_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_3) else '0'; dfp_trap_vector(1591) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_3) else '0'; dfp_trap_vector(1592) <= '1' when (V_X_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_3) else '0'; dfp_trap_vector(1593) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1594) <= '1' when (V_X_CTRL_RETT_shadow /= R_E_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1595) <= '1' when (V_X_CTRL_RETT_shadow /= R.X.CTRL.RETT) else '0'; dfp_trap_vector(1596) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(1597) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_2) else '0'; dfp_trap_vector(1598) <= '1' when (V_X_CTRL_RETT_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1599) <= '1' when (V_X_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0'; dfp_trap_vector(1600) <= '1' when (V_X_CTRL_RETT_shadow /= RIN_X_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1601) <= '1' when (V_X_CTRL_RETT_shadow /= V_M_CTRL_RETT_shadow_intermed_1) else '0'; dfp_trap_vector(1602) <= '1' when (V_X_CTRL_RETT_shadow /= R_A_CTRL_RETT_intermed_2) else '0'; dfp_trap_vector(1603) <= '1' when (V_X_CTRL_RETT_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1604) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0'; dfp_trap_vector(1605) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0'; dfp_trap_vector(1606) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0'; dfp_trap_vector(1607) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0'; dfp_trap_vector(1608) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0'; dfp_trap_vector(1609) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0'; dfp_trap_vector(1610) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0'; dfp_trap_vector(1611) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0'; dfp_trap_vector(1612) <= '1' when (V_X_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(1613) <= '1' when (V_X_LADDR_shadow /= RIN_X_LADDR_intermed_1) else '0'; dfp_trap_vector(1614) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0'; dfp_trap_vector(1615) <= '1' when (V_X_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(1616) <= '1' when (V_X_LADDR_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(1617) <= '1' when (V_X_LADDR_shadow /= R.X.LADDR) else '0'; dfp_trap_vector(1618) <= '1' when (V_X_LADDR_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1619) <= '1' when (V_X_LADDR_shadow /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(1620) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1621) <= '1' when (V_X_CTRL_ANNUL_shadow /= R.X.CTRL.ANNUL) else '0'; dfp_trap_vector(1622) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1623) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_M_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1624) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1625) <= '1' when (V_X_CTRL_ANNUL_shadow /= R.M.CTRL.ANNUL) else '0'; dfp_trap_vector(1626) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_X_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1627) <= '1' when (V_X_CTRL_ANNUL_shadow /= '1') else '0'; dfp_trap_vector(1628) <= '1' when (V_X_CTRL_ANNUL_shadow /= '0') else '0'; dfp_trap_vector(1629) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1630) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(1631) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1632) <= '1' when (V_X_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1633) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1634) <= '1' when (V_X_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0'; dfp_trap_vector(1635) <= '1' when (V_X_CTRL_ANNUL_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1636) <= '1' when (V_X_CTRL_TT_shadow /= V_E_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(1637) <= '1' when (V_X_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_4) else '0'; dfp_trap_vector(1638) <= '1' when (V_X_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1639) <= '1' when (V_X_CTRL_TT_shadow /= R_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1640) <= '1' when (V_X_CTRL_TT_shadow /= "000000") else '0'; dfp_trap_vector(1641) <= '1' when (V_X_CTRL_TT_shadow /= R_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1642) <= '1' when (V_X_CTRL_TT_shadow /= R.X.CTRL.TT) else '0'; dfp_trap_vector(1643) <= '1' when (V_X_CTRL_TT_shadow /= RIN_M_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(1644) <= '1' when (V_X_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(1645) <= '1' when (V_X_CTRL_TT_shadow /= V_M_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(1646) <= '1' when (V_X_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_4) else '0'; dfp_trap_vector(1647) <= '1' when (V_X_CTRL_TT_shadow /= RIN_X_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1648) <= '1' when (V_X_DATA0_shadow /= R.X.DATA ( 0 )) else '0'; dfp_trap_vector(1649) <= '1' when (V_X_DATA0_shadow /= DCO.DATA ( 0 )) else '0'; dfp_trap_vector(1650) <= '1' when (V_X_DATA0_shadow /= V_X_DATA0_shadow_intermed_2) else '0'; dfp_trap_vector(1651) <= '1' when (V_X_DATA0_shadow /= RIN_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1652) <= '1' when (V_X_DATA0_shadow /= R_X_DATA0_intermed_1) else '0'; dfp_trap_vector(1653) <= '1' when (V_X_DATA0_shadow /= RIN_X_DATA0_intermed_2) else '0'; dfp_trap_vector(1654) <= '1' when (V_X_DATA1_shadow /= DCO.DATA ( 1 )) else '0'; dfp_trap_vector(1655) <= '1' when (V_X_DATA1_shadow /= R.X.DATA ( 1 )) else '0'; dfp_trap_vector(1656) <= '1' when (V_X_DATA1_shadow /= V_X_DATA1_shadow_intermed_2) else '0'; dfp_trap_vector(1657) <= '1' when (V_X_DATA1_shadow /= RIN_X_DATA1_intermed_1) else '0'; dfp_trap_vector(1658) <= '1' when (V_X_DATA1_shadow /= R_X_DATA1_intermed_1) else '0'; dfp_trap_vector(1659) <= '1' when (V_X_DATA1_shadow /= RIN_X_DATA1_intermed_2) else '0'; dfp_trap_vector(1660) <= '1' when (V_X_SET_shadow /= RIN_X_SET_intermed_1) else '0'; dfp_trap_vector(1661) <= '1' when (V_X_SET_shadow /= DCO.SET ( 0 DOWNTO 0 )) else '0'; dfp_trap_vector(1662) <= '1' when (V_X_SET_shadow /= R.X.SET) else '0'; dfp_trap_vector(1663) <= '1' when (V_X_DCI_SIZE_shadow /= R.X.DCI.SIZE) else '0'; dfp_trap_vector(1664) <= '1' when (V_X_DCI_SIZE_shadow /= V_M_DCI_SIZE_shadow_intermed_2) else '0'; dfp_trap_vector(1665) <= '1' when (V_X_DCI_SIZE_shadow /= R_M_DCI_SIZE_intermed_1) else '0'; dfp_trap_vector(1666) <= '1' when (V_X_DCI_SIZE_shadow /= RIN_X_DCI_SIZE_intermed_1) else '0'; dfp_trap_vector(1667) <= '1' when (V_X_DCI_SIZE_shadow /= RIN_M_DCI_SIZE_intermed_2) else '0'; dfp_trap_vector(1668) <= '1' when (V_X_DCI_SIGNED_shadow /= RIN_M_DCI_SIGNED_intermed_2) else '0'; dfp_trap_vector(1669) <= '1' when (V_X_DCI_SIGNED_shadow /= R_M_DCI_SIGNED_intermed_1) else '0'; dfp_trap_vector(1670) <= '1' when (V_X_DCI_SIGNED_shadow /= RIN_X_DCI_SIGNED_intermed_1) else '0'; dfp_trap_vector(1671) <= '1' when (V_X_DCI_SIGNED_shadow /= V_M_DCI_SIGNED_shadow_intermed_2) else '0'; dfp_trap_vector(1672) <= '1' when (V_X_DCI_SIGNED_shadow /= R.X.DCI.SIGNED) else '0'; dfp_trap_vector(1673) <= '1' when (V_X_MEXC_shadow /= R.X.MEXC) else '0'; dfp_trap_vector(1674) <= '1' when (V_X_MEXC_shadow /= RIN_X_MEXC_intermed_1) else '0'; dfp_trap_vector(1675) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0'; dfp_trap_vector(1676) <= '1' when (V_X_ICC_shadow /= R.X.ICC) else '0'; dfp_trap_vector(1677) <= '1' when (V_X_ICC_shadow /= RIN_X_ICC_intermed_1) else '0'; dfp_trap_vector(1678) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0'; dfp_trap_vector(1679) <= '1' when (V_X_CTRL_WICC_shadow /= R_A_CTRL_WICC_intermed_2) else '0'; dfp_trap_vector(1680) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(1681) <= '1' when (V_X_CTRL_WICC_shadow /= V_E_CTRL_WICC_shadow_intermed_2) else '0'; dfp_trap_vector(1682) <= '1' when (V_X_CTRL_WICC_shadow /= R.M.CTRL.WICC) else '0'; dfp_trap_vector(1683) <= '1' when (V_X_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_3) else '0'; dfp_trap_vector(1684) <= '1' when (V_X_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1685) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_X_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1686) <= '1' when (V_X_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_3) else '0'; dfp_trap_vector(1687) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_2) else '0'; dfp_trap_vector(1688) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_M_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1689) <= '1' when (V_X_CTRL_WICC_shadow /= R.X.CTRL.WICC) else '0'; dfp_trap_vector(1690) <= '1' when (V_X_CTRL_WICC_shadow /= '1') else '0'; dfp_trap_vector(1691) <= '1' when (V_X_CTRL_WICC_shadow /= '0') else '0'; dfp_trap_vector(1692) <= '1' when (V_X_CTRL_WICC_shadow /= R_E_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1693) <= '1' when (V_X_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_3) else '0'; dfp_trap_vector(1694) <= '1' when (V_X_CTRL_WICC_shadow /= V_M_CTRL_WICC_shadow_intermed_1) else '0'; dfp_trap_vector(1695) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(1696) <= '1' when (V_X_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_3) else '0'; dfp_trap_vector(1697) <= '1' when (V_X_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0'; dfp_trap_vector(1698) <= '1' when (V_M_CTRL_shadow /= RIN_E_CTRL_intermed_1) else '0'; dfp_trap_vector(1699) <= '1' when (V_M_CTRL_shadow /= R.E.CTRL) else '0'; dfp_trap_vector(1700) <= '1' when (V_M_CTRL_shadow /= R.M.CTRL) else '0'; dfp_trap_vector(1701) <= '1' when (V_M_CTRL_shadow /= RIN_M_CTRL_intermed_1) else '0'; dfp_trap_vector(1702) <= '1' when (V_M_CTRL_shadow /= V_E_CTRL_shadow_intermed_1) else '0'; dfp_trap_vector(1703) <= '1' when (V_M_CTRL_shadow /= RIN_A_CTRL_intermed_2) else '0'; dfp_trap_vector(1704) <= '1' when (V_M_CTRL_shadow /= V_A_CTRL_shadow_intermed_2) else '0'; dfp_trap_vector(1705) <= '1' when (V_M_CTRL_shadow /= R_A_CTRL_intermed_1) else '0'; dfp_trap_vector(1706) <= '1' when (V_M_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0'; dfp_trap_vector(1707) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1708) <= '1' when (V_M_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1709) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_M_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1710) <= '1' when (V_M_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1711) <= '1' when (V_M_CTRL_RETT_shadow /= '1') else '0'; dfp_trap_vector(1712) <= '1' when (V_M_CTRL_RETT_shadow /= '0') else '0'; dfp_trap_vector(1713) <= '1' when (V_M_CTRL_RETT_shadow /= V_E_CTRL_RETT_shadow_intermed_1) else '0'; dfp_trap_vector(1714) <= '1' when (V_M_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_2) else '0'; dfp_trap_vector(1715) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_2) else '0'; dfp_trap_vector(1716) <= '1' when (V_M_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0'; dfp_trap_vector(1717) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1718) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0'; dfp_trap_vector(1719) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0'; dfp_trap_vector(1720) <= '1' when (V_M_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1721) <= '1' when (V_M_CTRL_RETT_shadow /= V_E_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1722) <= '1' when (V_M_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1723) <= '1' when (V_M_CTRL_RETT_shadow /= R_A_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1724) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.ANNUL) else '0'; dfp_trap_vector(1725) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1726) <= '1' when (V_M_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1727) <= '1' when (V_M_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1728) <= '1' when (V_M_CTRL_WREG_shadow /= '1') else '0'; dfp_trap_vector(1729) <= '1' when (V_M_CTRL_WREG_shadow /= '0') else '0'; dfp_trap_vector(1730) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_M_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1731) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(1732) <= '1' when (V_M_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_2) else '0'; dfp_trap_vector(1733) <= '1' when (V_M_CTRL_WREG_shadow /= R_A_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1734) <= '1' when (V_M_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0'; dfp_trap_vector(1735) <= '1' when (V_M_CTRL_WREG_shadow /= R.M.CTRL.WREG) else '0'; dfp_trap_vector(1736) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0'; dfp_trap_vector(1737) <= '1' when (V_M_CTRL_WREG_shadow /= R.E.CTRL.WREG) else '0'; dfp_trap_vector(1738) <= '1' when (V_M_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1739) <= '1' when (V_M_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1740) <= '1' when (V_M_CTRL_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_1) else '0'; dfp_trap_vector(1741) <= '1' when (V_E_CWP_shadow /= RIN_E_CWP_intermed_1) else '0'; dfp_trap_vector(1742) <= '1' when (V_E_CWP_shadow /= V_A_CWP_shadow_intermed_1) else '0'; dfp_trap_vector(1743) <= '1' when (V_E_CWP_shadow /= RIN_D_CWP_intermed_2) else '0'; dfp_trap_vector(1744) <= '1' when (V_E_CWP_shadow /= R.E.CWP) else '0'; dfp_trap_vector(1745) <= '1' when (V_E_CWP_shadow /= RIN_A_CWP_intermed_1) else '0'; dfp_trap_vector(1746) <= '1' when (V_E_CWP_shadow /= V_D_CWP_shadow_intermed_2) else '0'; dfp_trap_vector(1747) <= '1' when (V_E_CWP_shadow /= R_D_CWP_intermed_1) else '0'; dfp_trap_vector(1748) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0'; dfp_trap_vector(1749) <= '1' when (V_M_SU_shadow /= R.M.SU) else '0'; dfp_trap_vector(1750) <= '1' when (V_M_SU_shadow /= R_A_SU_intermed_1) else '0'; dfp_trap_vector(1751) <= '1' when (V_M_SU_shadow /= RIN_A_SU_intermed_2) else '0'; dfp_trap_vector(1752) <= '1' when (V_M_SU_shadow /= V_E_SU_shadow_intermed_1) else '0'; dfp_trap_vector(1753) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0'; dfp_trap_vector(1754) <= '1' when (V_M_SU_shadow /= V_A_SU_shadow_intermed_2) else '0'; dfp_trap_vector(1755) <= '1' when (V_M_SU_shadow /= RIN_M_SU_intermed_1) else '0'; dfp_trap_vector(1756) <= '1' when (V_M_SU_shadow /= RIN_E_SU_intermed_1) else '0'; dfp_trap_vector(1757) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0'; dfp_trap_vector(1758) <= '1' when (V_M_MUL_shadow /= '0') else '0'; dfp_trap_vector(1759) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0'; dfp_trap_vector(1760) <= '1' when (V_M_NALIGN_shadow /= '1') else '0'; dfp_trap_vector(1761) <= '1' when (V_M_NALIGN_shadow /= '0') else '0'; dfp_trap_vector(1762) <= '1' when (V_M_NALIGN_shadow /= RIN_M_NALIGN_intermed_1) else '0'; dfp_trap_vector(1763) <= '1' when (V_M_NALIGN_shadow /= R.M.NALIGN) else '0'; dfp_trap_vector(1764) <= '1' when (EX_ADD_RES3_shadow /= EX_OP23_shadow) else '0'; dfp_trap_vector(1765) <= '1' when (EX_ADD_RES3_shadow /= V_X_DATA03_shadow_intermed_2) else '0'; dfp_trap_vector(1766) <= '1' when (EX_ADD_RES3_shadow /= V_X_DATA03_shadow_intermed_1) else '0'; dfp_trap_vector(1767) <= '1' when (EX_ADD_RES3_shadow /= DCO_DATA03_intermed_1) else '0'; dfp_trap_vector(1768) <= '1' when (EX_ADD_RES3_shadow /= R.E.OP2( 3 )) else '0'; dfp_trap_vector(1769) <= '1' when (EX_ADD_RES3_shadow /= RIN_X_DATA03_intermed_1) else '0'; dfp_trap_vector(1770) <= '1' when (EX_ADD_RES3_shadow /= R_X_DATA03_intermed_1) else '0'; dfp_trap_vector(1771) <= '1' when (EX_ADD_RES3_shadow /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(1772) <= '1' when (EX_ADD_RES3_shadow /= RIN_E_OP23_intermed_1) else '0'; dfp_trap_vector(1773) <= '1' when (EX_ADD_RES3_shadow /= RIN_E_OP13_intermed_1) else '0'; dfp_trap_vector(1774) <= '1' when (EX_ADD_RES3_shadow /= EX_FORCE_A2_shadow) else '0'; dfp_trap_vector(1775) <= '1' when (EX_ADD_RES3_shadow /= R.X.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(1776) <= '1' when (EX_ADD_RES3_shadow /= EX_OP13_shadow) else '0'; dfp_trap_vector(1777) <= '1' when (EX_ADD_RES3_shadow /= V_E_OP23_shadow_intermed_1) else '0'; dfp_trap_vector(1778) <= '1' when (EX_ADD_RES3_shadow /= R.E.OP1( 3 )) else '0'; dfp_trap_vector(1779) <= '1' when (EX_ADD_RES3_shadow /= V_E_OP13_shadow_intermed_1) else '0'; dfp_trap_vector(1780) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1781) <= '1' when (V_M_CTRL_ANNUL_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1782) <= '1' when (V_M_CTRL_ANNUL_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1783) <= '1' when (V_M_CTRL_ANNUL_shadow /= R.M.CTRL.ANNUL) else '0'; dfp_trap_vector(1784) <= '1' when (V_M_CTRL_ANNUL_shadow /= '1') else '0'; dfp_trap_vector(1785) <= '1' when (V_M_CTRL_ANNUL_shadow /= '0') else '0'; dfp_trap_vector(1786) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_M_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1787) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1788) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1789) <= '1' when (V_M_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1790) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_E_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1791) <= '1' when (V_M_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_3) else '0'; dfp_trap_vector(1792) <= '1' when (V_M_CTRL_ANNUL_shadow /= R_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1793) <= '1' when (V_M_CTRL_WICC_shadow /= R_A_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1794) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_3) else '0'; dfp_trap_vector(1795) <= '1' when (V_M_CTRL_WICC_shadow /= V_E_CTRL_WICC_shadow_intermed_1) else '0'; dfp_trap_vector(1796) <= '1' when (V_M_CTRL_WICC_shadow /= R.M.CTRL.WICC) else '0'; dfp_trap_vector(1797) <= '1' when (V_M_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_2) else '0'; dfp_trap_vector(1798) <= '1' when (V_M_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1799) <= '1' when (V_M_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1800) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1801) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_M_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1802) <= '1' when (V_M_CTRL_WICC_shadow /= '1') else '0'; dfp_trap_vector(1803) <= '1' when (V_M_CTRL_WICC_shadow /= '0') else '0'; dfp_trap_vector(1804) <= '1' when (V_M_CTRL_WICC_shadow /= R.E.CTRL.WICC) else '0'; dfp_trap_vector(1805) <= '1' when (V_M_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_2) else '0'; dfp_trap_vector(1806) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_3) else '0'; dfp_trap_vector(1807) <= '1' when (V_M_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_2) else '0'; dfp_trap_vector(1808) <= '1' when (V_M_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1809) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0'; dfp_trap_vector(1810) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0'; dfp_trap_vector(1811) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0'; dfp_trap_vector(1812) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0'; dfp_trap_vector(1813) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0'; dfp_trap_vector(1814) <= '1' when (V_M_CTRL_LD_shadow /= R_A_CTRL_LD_intermed_2) else '0'; dfp_trap_vector(1815) <= '1' when (V_M_CTRL_LD_shadow /= RIN_A_CTRL_LD_intermed_3) else '0'; dfp_trap_vector(1816) <= '1' when (V_M_CTRL_LD_shadow /= V_E_CTRL_LD_shadow_intermed_2) else '0'; dfp_trap_vector(1817) <= '1' when (V_M_CTRL_LD_shadow /= '1') else '0'; dfp_trap_vector(1818) <= '1' when (V_M_CTRL_LD_shadow /= R_E_CTRL_LD_intermed_1) else '0'; dfp_trap_vector(1819) <= '1' when (V_M_CTRL_LD_shadow /= R.M.CTRL.LD) else '0'; dfp_trap_vector(1820) <= '1' when (V_M_CTRL_LD_shadow /= RIN_E_CTRL_LD_intermed_2) else '0'; dfp_trap_vector(1821) <= '1' when (V_M_CTRL_LD_shadow /= RIN_M_CTRL_LD_intermed_1) else '0'; dfp_trap_vector(1822) <= '1' when (V_M_CTRL_LD_shadow /= V_A_CTRL_LD_shadow_intermed_3) else '0'; dfp_trap_vector(1823) <= '1' when (V_E_CTRL_shadow /= RIN_E_CTRL_intermed_1) else '0'; dfp_trap_vector(1824) <= '1' when (V_E_CTRL_shadow /= R.E.CTRL) else '0'; dfp_trap_vector(1825) <= '1' when (V_E_CTRL_shadow /= RIN_A_CTRL_intermed_1) else '0'; dfp_trap_vector(1826) <= '1' when (V_E_CTRL_shadow /= V_A_CTRL_shadow_intermed_1) else '0'; dfp_trap_vector(1827) <= '1' when (V_E_CTRL_shadow /= R.A.CTRL) else '0'; dfp_trap_vector(1828) <= '1' when (V_E_JMPL_shadow /= RIN_E_JMPL_intermed_1) else '0'; dfp_trap_vector(1829) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0'; dfp_trap_vector(1830) <= '1' when (V_E_JMPL_shadow /= RIN_A_JMPL_intermed_1) else '0'; dfp_trap_vector(1831) <= '1' when (V_E_JMPL_shadow /= R.E.JMPL) else '0'; dfp_trap_vector(1832) <= '1' when (V_E_JMPL_shadow /= V_A_JMPL_shadow_intermed_1) else '0'; dfp_trap_vector(1833) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1834) <= '1' when (V_E_CTRL_ANNUL_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1835) <= '1' when (V_E_CTRL_ANNUL_shadow /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1836) <= '1' when (V_E_CTRL_ANNUL_shadow /= '1') else '0'; dfp_trap_vector(1837) <= '1' when (V_E_CTRL_ANNUL_shadow /= '0') else '0'; dfp_trap_vector(1838) <= '1' when (V_E_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(1839) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_E_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1840) <= '1' when (V_E_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1841) <= '1' when (V_E_CTRL_ANNUL_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1842) <= '1' when (V_E_CTRL_ANNUL_shadow /= R.E.CTRL.ANNUL) else '0'; dfp_trap_vector(1843) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1844) <= '1' when (V_E_CTRL_RETT_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1845) <= '1' when (V_E_CTRL_RETT_shadow /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1846) <= '1' when (V_E_CTRL_RETT_shadow /= '1') else '0'; dfp_trap_vector(1847) <= '1' when (V_E_CTRL_RETT_shadow /= '0') else '0'; dfp_trap_vector(1848) <= '1' when (V_E_CTRL_RETT_shadow /= V_A_CTRL_RETT_shadow_intermed_1) else '0'; dfp_trap_vector(1849) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1850) <= '1' when (V_E_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(1851) <= '1' when (V_E_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0'; dfp_trap_vector(1852) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1853) <= '1' when (V_E_CTRL_RETT_shadow /= RIN_E_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1854) <= '1' when (V_E_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1855) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0'; dfp_trap_vector(1856) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1857) <= '1' when (V_E_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1858) <= '1' when (V_E_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1859) <= '1' when (V_E_CTRL_WREG_shadow /= '1') else '0'; dfp_trap_vector(1860) <= '1' when (V_E_CTRL_WREG_shadow /= '0') else '0'; dfp_trap_vector(1861) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1862) <= '1' when (V_E_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_1) else '0'; dfp_trap_vector(1863) <= '1' when (V_E_CTRL_WREG_shadow /= R.A.CTRL.WREG) else '0'; dfp_trap_vector(1864) <= '1' when (V_E_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(1865) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1866) <= '1' when (V_E_CTRL_WREG_shadow /= R.E.CTRL.WREG) else '0'; dfp_trap_vector(1867) <= '1' when (V_E_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1868) <= '1' when (V_E_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1869) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0'; dfp_trap_vector(1870) <= '1' when (V_E_SU_shadow /= RIN_A_SU_intermed_1) else '0'; dfp_trap_vector(1871) <= '1' when (V_E_SU_shadow /= R.E.SU) else '0'; dfp_trap_vector(1872) <= '1' when (V_E_SU_shadow /= V_A_SU_shadow_intermed_1) else '0'; dfp_trap_vector(1873) <= '1' when (V_E_SU_shadow /= RIN_E_SU_intermed_1) else '0'; dfp_trap_vector(1874) <= '1' when (V_E_ET_shadow /= RIN_E_ET_intermed_1) else '0'; dfp_trap_vector(1875) <= '1' when (V_E_ET_shadow /= R.E.ET) else '0'; dfp_trap_vector(1876) <= '1' when (V_E_ET_shadow /= RIN_A_ET_intermed_1) else '0'; dfp_trap_vector(1877) <= '1' when (V_E_ET_shadow /= V_A_ET_shadow_intermed_1) else '0'; dfp_trap_vector(1878) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0'; dfp_trap_vector(1879) <= '1' when (V_E_CTRL_WICC_shadow /= R.A.CTRL.WICC) else '0'; dfp_trap_vector(1880) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_2) else '0'; dfp_trap_vector(1881) <= '1' when (V_E_CTRL_WICC_shadow /= V_A_CTRL_WICC_shadow_intermed_1) else '0'; dfp_trap_vector(1882) <= '1' when (V_E_CTRL_WICC_shadow /= R_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1883) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_E_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1884) <= '1' when (V_E_CTRL_WICC_shadow /= R_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1885) <= '1' when (V_E_CTRL_WICC_shadow /= '1') else '0'; dfp_trap_vector(1886) <= '1' when (V_E_CTRL_WICC_shadow /= '0') else '0'; dfp_trap_vector(1887) <= '1' when (V_E_CTRL_WICC_shadow /= R.E.CTRL.WICC) else '0'; dfp_trap_vector(1888) <= '1' when (V_E_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow_intermed_1) else '0'; dfp_trap_vector(1889) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_2) else '0'; dfp_trap_vector(1890) <= '1' when (V_E_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1891) <= '1' when (V_E_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1892) <= '1' when (V_A_CWP_shadow /= RIN_D_CWP_intermed_1) else '0'; dfp_trap_vector(1893) <= '1' when (V_A_CWP_shadow /= RIN_A_CWP_intermed_1) else '0'; dfp_trap_vector(1894) <= '1' when (V_A_CWP_shadow /= V_D_CWP_shadow_intermed_1) else '0'; dfp_trap_vector(1895) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0'; dfp_trap_vector(1896) <= '1' when (V_A_CWP_shadow /= R.A.CWP) else '0'; dfp_trap_vector(1897) <= '1' when (V_A_RFA1_shadow /= DBGI.DADDR ( 9 DOWNTO 2 )) else '0'; dfp_trap_vector(1898) <= '1' when (V_A_RFA1_shadow /= DE_RADDR17DOWNTO0_shadow) else '0'; dfp_trap_vector(1899) <= '1' when (V_A_RFA1_shadow /= R.A.RFA1) else '0'; dfp_trap_vector(1900) <= '1' when (V_A_RFA1_shadow /= RIN_A_RFA1_intermed_1) else '0'; dfp_trap_vector(1901) <= '1' when (DE_RADDR17DOWNTO0_shadow /= V_A_RFA1_shadow_intermed_1) else '0'; dfp_trap_vector(1902) <= '1' when (DE_RADDR17DOWNTO0_shadow /= DBGI_DADDR9DOWNTO2_intermed_1) else '0'; dfp_trap_vector(1903) <= '1' when (DE_RADDR17DOWNTO0_shadow /= R.A.RFA1) else '0'; dfp_trap_vector(1904) <= '1' when (DE_RADDR17DOWNTO0_shadow /= RIN_A_RFA1_intermed_1) else '0'; dfp_trap_vector(1905) <= '1' when (V_A_RFA2_shadow /= DE_RADDR27DOWNTO0_shadow) else '0'; dfp_trap_vector(1906) <= '1' when (V_A_RFA2_shadow /= R.A.RFA2) else '0'; dfp_trap_vector(1907) <= '1' when (V_A_RFA2_shadow /= RIN_A_RFA2_intermed_1) else '0'; dfp_trap_vector(1908) <= '1' when (V_A_CTRL_ANNUL_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1909) <= '1' when (V_A_CTRL_ANNUL_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1910) <= '1' when (V_A_CTRL_ANNUL_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1911) <= '1' when (V_A_CTRL_ANNUL_shadow /= '1') else '0'; dfp_trap_vector(1912) <= '1' when (V_A_CTRL_ANNUL_shadow /= '0') else '0'; dfp_trap_vector(1913) <= '1' when (V_A_CTRL_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1914) <= '1' when (V_A_CTRL_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1915) <= '1' when (V_A_CTRL_WICC_shadow /= R.A.CTRL.WICC) else '0'; dfp_trap_vector(1916) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1917) <= '1' when (V_A_CTRL_WICC_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1918) <= '1' when (V_A_CTRL_WICC_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1919) <= '1' when (V_A_CTRL_WICC_shadow /= '1') else '0'; dfp_trap_vector(1920) <= '1' when (V_A_CTRL_WICC_shadow /= '0') else '0'; dfp_trap_vector(1921) <= '1' when (V_A_CTRL_WICC_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1922) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1923) <= '1' when (V_A_CTRL_WICC_shadow /= RIN_A_CTRL_WICC_intermed_1) else '0'; dfp_trap_vector(1924) <= '1' when (V_A_CTRL_WICC_shadow /= V_A_CTRL_ANNUL_shadow) else '0'; dfp_trap_vector(1925) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1926) <= '1' when (V_A_CTRL_WREG_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1927) <= '1' when (V_A_CTRL_WREG_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1928) <= '1' when (V_A_CTRL_WREG_shadow /= '1') else '0'; dfp_trap_vector(1929) <= '1' when (V_A_CTRL_WREG_shadow /= '0') else '0'; dfp_trap_vector(1930) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(1931) <= '1' when (V_A_CTRL_WREG_shadow /= R.A.CTRL.WREG) else '0'; dfp_trap_vector(1932) <= '1' when (V_A_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1933) <= '1' when (V_A_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1934) <= '1' when (V_A_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow) else '0'; dfp_trap_vector(1935) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1936) <= '1' when (V_A_CTRL_RETT_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1937) <= '1' when (V_A_CTRL_RETT_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1938) <= '1' when (V_A_CTRL_RETT_shadow /= '1') else '0'; dfp_trap_vector(1939) <= '1' when (V_A_CTRL_RETT_shadow /= '0') else '0'; dfp_trap_vector(1940) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_A_CTRL_RETT_intermed_1) else '0'; dfp_trap_vector(1941) <= '1' when (V_A_CTRL_RETT_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1942) <= '1' when (V_A_CTRL_RETT_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1943) <= '1' when (V_A_CTRL_RETT_shadow /= V_A_CTRL_ANNUL_shadow) else '0'; dfp_trap_vector(1944) <= '1' when (V_A_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0'; dfp_trap_vector(1945) <= '1' when (V_A_CTRL_WY_shadow /= RIN_A_CTRL_ANNUL_intermed_1) else '0'; dfp_trap_vector(1946) <= '1' when (V_A_CTRL_WY_shadow /= R.A.CTRL.ANNUL) else '0'; dfp_trap_vector(1947) <= '1' when (V_A_CTRL_WY_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(1948) <= '1' when (V_A_CTRL_WY_shadow /= '1') else '0'; dfp_trap_vector(1949) <= '1' when (V_A_CTRL_WY_shadow /= '0') else '0'; dfp_trap_vector(1950) <= '1' when (V_A_CTRL_WY_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(1951) <= '1' when (V_A_CTRL_WY_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(1952) <= '1' when (V_A_CTRL_WY_shadow /= R.A.CTRL.WY) else '0'; dfp_trap_vector(1953) <= '1' when (V_A_CTRL_WY_shadow /= RIN_A_CTRL_WY_intermed_1) else '0'; dfp_trap_vector(1954) <= '1' when (V_A_CTRL_WY_shadow /= V_A_CTRL_ANNUL_shadow) else '0'; dfp_trap_vector(1955) <= '1' when (V_A_CTRL_TRAP_shadow /= ICO_MEXC_intermed_1) else '0'; dfp_trap_vector(1956) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(1957) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0'; dfp_trap_vector(1958) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0'; dfp_trap_vector(1959) <= '1' when (V_A_CTRL_TRAP_shadow /= R.A.CTRL.TRAP) else '0'; dfp_trap_vector(1960) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0'; dfp_trap_vector(1961) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(1962) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0'; dfp_trap_vector(1963) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0'; dfp_trap_vector(1964) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0'; dfp_trap_vector(1965) <= '1' when (V_A_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(1966) <= '1' when (V_A_CTRL_INST_shadow /= R.A.CTRL.INST) else '0'; dfp_trap_vector(1967) <= '1' when (V_A_CTRL_PC_shadow /= RIN_D_PC_intermed_1) else '0'; dfp_trap_vector(1968) <= '1' when (V_A_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(1969) <= '1' when (V_A_CTRL_PC_shadow /= R.A.CTRL.PC) else '0'; dfp_trap_vector(1970) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0'; dfp_trap_vector(1971) <= '1' when (V_A_CTRL_PC_shadow /= V_D_PC_shadow_intermed_1) else '0'; dfp_trap_vector(1972) <= '1' when (V_A_CTRL_CNT_shadow /= RIN_D_CNT_intermed_1) else '0'; dfp_trap_vector(1973) <= '1' when (V_A_CTRL_CNT_shadow /= R.A.CTRL.CNT) else '0'; dfp_trap_vector(1974) <= '1' when (V_A_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_1) else '0'; dfp_trap_vector(1975) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0'; dfp_trap_vector(1976) <= '1' when (V_A_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(1977) <= '1' when (V_A_CTRL_CNT_shadow /= "00") else '0'; dfp_trap_vector(1978) <= '1' when (V_A_STEP_shadow /= R_D_ANNUL_intermed_1) else '0'; dfp_trap_vector(1979) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0'; dfp_trap_vector(1980) <= '1' when (V_A_STEP_shadow /= V_D_ANNUL_shadow_intermed_2) else '0'; dfp_trap_vector(1981) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0'; dfp_trap_vector(1982) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0'; dfp_trap_vector(1983) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0'; dfp_trap_vector(1984) <= '1' when (V_A_STEP_shadow /= RIN_D_ANNUL_intermed_2) else '0'; dfp_trap_vector(1985) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0'; dfp_trap_vector(1986) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0'; dfp_trap_vector(1987) <= '1' when (V_D_STEP_shadow /= R.D.ANNUL) else '0'; dfp_trap_vector(1988) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0'; dfp_trap_vector(1989) <= '1' when (V_D_STEP_shadow /= V_D_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(1990) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0'; dfp_trap_vector(1991) <= '1' when (V_D_STEP_shadow /= RIN_D_ANNUL_intermed_1) else '0'; dfp_trap_vector(1992) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0'; dfp_trap_vector(1993) <= '1' when (V_D_CNT_shadow /= RIN_D_CNT_intermed_1) else '0'; dfp_trap_vector(1994) <= '1' when (V_D_CNT_shadow /= R.D.CNT) else '0'; dfp_trap_vector(1995) <= '1' when (V_D_CNT_shadow /= "00") else '0'; dfp_trap_vector(1996) <= '1' when (V_F_PC_shadow /= EX_ADD_RES32DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(1997) <= '1' when (V_F_PC_shadow /= XC_TRAP_ADDRESS_shadow) else '0'; dfp_trap_vector(1998) <= '1' when (V_F_PC_shadow /= RIN_F_PC_intermed_1) else '0'; dfp_trap_vector(1999) <= '1' when (V_F_PC_shadow /= R.F.PC) else '0'; dfp_trap_vector(2000) <= '1' when (V_F_PC_shadow /= EX_JUMP_ADDRESS_shadow_intermed_1) else '0'; dfp_trap_vector(2001) <= '1' when (V_F_PC_shadow /= "000000000000000000000000000000") else '0'; dfp_trap_vector(2002) <= '1' when (V_F_BRANCH_shadow /= RIN_F_BRANCH_intermed_1) else '0'; dfp_trap_vector(2003) <= '1' when (V_F_BRANCH_shadow /= '1') else '0'; dfp_trap_vector(2004) <= '1' when (V_F_BRANCH_shadow /= '0') else '0'; dfp_trap_vector(2005) <= '1' when (V_F_BRANCH_shadow /= R.F.BRANCH) else '0'; dfp_trap_vector(2006) <= '1' when (V_F_PC31DOWNTO12_shadow /= R.F.PC ( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(2007) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2008) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0'; dfp_trap_vector(2009) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(2010) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(2011) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2) else '0'; dfp_trap_vector(2012) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2013) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2014) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2015) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2016) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2017) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2018) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2019) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_F_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2020) <= '1' when (V_F_PC31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2021) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(2022) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2) else '0'; dfp_trap_vector(2023) <= '1' when (V_F_PC31DOWNTO12_shadow /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(2024) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2025) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2026) <= '1' when (V_F_PC31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2027) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2028) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2029) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2030) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(2031) <= '1' when (V_F_PC31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2032) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(2033) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2034) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2035) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2036) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2) else '0'; dfp_trap_vector(2037) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2038) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2039) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2040) <= '1' when (V_F_PC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2041) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2042) <= '1' when (V_F_PC31DOWNTO2_shadow(29 downto 2) /= X"0000001") else '0'; dfp_trap_vector(2043) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2044) <= '1' when (V_F_PC31DOWNTO2_shadow /= R.F.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2045) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2046) <= '1' when (V_F_PC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2047) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2048) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2049) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2050) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2051) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2052) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2053) <= '1' when (V_F_PC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2054) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2055) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2056) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2057) <= '1' when (V_F_PC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2058) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2059) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2060) <= '1' when (NPC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2061) <= '1' when (NPC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2062) <= '1' when (NPC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2063) <= '1' when (NPC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(2064) <= '1' when (NPC31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2065) <= '1' when (NPC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2066) <= '1' when (NPC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2067) <= '1' when (NPC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2068) <= '1' when (NPC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2069) <= '1' when (NPC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2070) <= '1' when (NPC31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2071) <= '1' when (NPC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2072) <= '1' when (NPC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2073) <= '1' when (NPC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2074) <= '1' when (NPC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2075) <= '1' when (NPC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2076) <= '1' when (NPC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2077) <= '1' when (NPC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2078) <= '1' when (NPC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2079) <= '1' when (NPC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2080) <= '1' when (NPC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2081) <= '1' when (NPC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2082) <= '1' when (NPC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2083) <= '1' when (NPC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2084) <= '1' when (V_D_INST0_shadow /= RIN_D_INST0_intermed_1) else '0'; dfp_trap_vector(2085) <= '1' when (V_D_INST0_shadow /= R_D_INST0_intermed_1) else '0'; dfp_trap_vector(2086) <= '1' when (V_D_INST0_shadow /= R.D.INST ( 0 )) else '0'; dfp_trap_vector(2087) <= '1' when (V_D_INST0_shadow /= ICO.DATA ( 0 )) else '0'; dfp_trap_vector(2088) <= '1' when (V_D_INST0_shadow /= V_D_INST0_shadow_intermed_2) else '0'; dfp_trap_vector(2089) <= '1' when (V_D_INST0_shadow /= RIN_D_INST0_intermed_2) else '0'; dfp_trap_vector(2090) <= '1' when (V_D_INST1_shadow /= RIN_D_INST1_intermed_1) else '0'; dfp_trap_vector(2091) <= '1' when (V_D_INST1_shadow /= R_D_INST1_intermed_1) else '0'; dfp_trap_vector(2092) <= '1' when (V_D_INST1_shadow /= R.D.INST ( 1 )) else '0'; dfp_trap_vector(2093) <= '1' when (V_D_INST1_shadow /= ICO.DATA ( 1 )) else '0'; dfp_trap_vector(2094) <= '1' when (V_D_INST1_shadow /= V_D_INST1_shadow_intermed_2) else '0'; dfp_trap_vector(2095) <= '1' when (V_D_INST1_shadow /= RIN_D_INST1_intermed_2) else '0'; dfp_trap_vector(2096) <= '1' when (V_D_SET_shadow /= ICO.SET ( 0 DOWNTO 0 )) else '0'; dfp_trap_vector(2097) <= '1' when (V_D_SET_shadow /= R.D.SET) else '0'; dfp_trap_vector(2098) <= '1' when (V_D_SET_shadow /= RIN_D_SET_intermed_1) else '0'; dfp_trap_vector(2099) <= '1' when (V_D_MEXC_shadow /= ICO.MEXC) else '0'; dfp_trap_vector(2100) <= '1' when (V_D_MEXC_shadow /= R.D.MEXC) else '0'; dfp_trap_vector(2101) <= '1' when (V_D_MEXC_shadow /= RIN_D_MEXC_intermed_1) else '0'; dfp_trap_vector(2102) <= '1' when (EX_OP131_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2103) <= '1' when (EX_OP131_shadow /= RIN_E_OP131_intermed_1) else '0'; dfp_trap_vector(2104) <= '1' when (EX_OP131_shadow /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(2105) <= '1' when (EX_OP131_shadow /= R.E.OP1( 31 )) else '0'; dfp_trap_vector(2106) <= '1' when (EX_OP131_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(2107) <= '1' when (EX_OP131_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2108) <= '1' when (EX_OP131_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(2109) <= '1' when (EX_OP131_shadow /= V_E_OP131_shadow_intermed_1) else '0'; dfp_trap_vector(2110) <= '1' when (EX_OP131_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2111) <= '1' when (EX_OP131_shadow /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(2112) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2113) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(2114) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(2115) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2116) <= '1' when (EX_OP231_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(2117) <= '1' when (EX_OP231_shadow /= RIN_E_OP231_intermed_1) else '0'; dfp_trap_vector(2118) <= '1' when (EX_OP231_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2119) <= '1' when (EX_OP231_shadow /= R.E.OP2( 31 )) else '0'; dfp_trap_vector(2120) <= '1' when (EX_OP231_shadow /= V_E_OP231_shadow_intermed_1) else '0'; dfp_trap_vector(2121) <= '1' when (EX_OP231_shadow /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(2122) <= '1' when (VFPI_D_ANNUL_shadow /= R.D.ANNUL) else '0'; dfp_trap_vector(2123) <= '1' when (VFPI_D_ANNUL_shadow /= R.X.ANNUL_ALL) else '0'; dfp_trap_vector(2124) <= '1' when (VFPI_D_ANNUL_shadow /= '1') else '0'; dfp_trap_vector(2125) <= '1' when (VFPI_D_ANNUL_shadow /= '0') else '0'; dfp_trap_vector(2126) <= '1' when (VFPI_D_ANNUL_shadow /= V_D_ANNUL_shadow_intermed_1) else '0'; dfp_trap_vector(2127) <= '1' when (VFPI_D_ANNUL_shadow /= V_X_ANNUL_ALL_shadow) else '0'; dfp_trap_vector(2128) <= '1' when (VFPI_D_ANNUL_shadow /= RIN_X_ANNUL_ALL_intermed_1) else '0'; dfp_trap_vector(2129) <= '1' when (VFPI_D_ANNUL_shadow /= RIN_D_ANNUL_intermed_1) else '0'; dfp_trap_vector(2130) <= '1' when (VFPI_DBG_ENABLE_shadow /= '0') else '0'; dfp_trap_vector(2131) <= '1' when (VFPI_DBG_ENABLE_shadow /= DBGI.DENABLE) else '0'; dfp_trap_vector(2132) <= '1' when (EX_OP13_shadow /= V_X_DATA03_shadow_intermed_2) else '0'; dfp_trap_vector(2133) <= '1' when (EX_OP13_shadow /= V_X_DATA03_shadow_intermed_1) else '0'; dfp_trap_vector(2134) <= '1' when (EX_OP13_shadow /= DCO_DATA03_intermed_1) else '0'; dfp_trap_vector(2135) <= '1' when (EX_OP13_shadow /= RIN_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2136) <= '1' when (EX_OP13_shadow /= R_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2137) <= '1' when (EX_OP13_shadow /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(2138) <= '1' when (EX_OP13_shadow /= RIN_E_OP13_intermed_1) else '0'; dfp_trap_vector(2139) <= '1' when (EX_OP13_shadow /= R.X.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(2140) <= '1' when (EX_OP13_shadow /= R.E.OP1( 3 )) else '0'; dfp_trap_vector(2141) <= '1' when (EX_OP13_shadow /= V_E_OP13_shadow_intermed_1) else '0'; dfp_trap_vector(2142) <= '1' when (EX_OP23_shadow /= V_X_DATA03_shadow_intermed_2) else '0'; dfp_trap_vector(2143) <= '1' when (EX_OP23_shadow /= V_X_DATA03_shadow_intermed_1) else '0'; dfp_trap_vector(2144) <= '1' when (EX_OP23_shadow /= DCO_DATA03_intermed_1) else '0'; dfp_trap_vector(2145) <= '1' when (EX_OP23_shadow /= R.E.OP2( 3 )) else '0'; dfp_trap_vector(2146) <= '1' when (EX_OP23_shadow /= RIN_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2147) <= '1' when (EX_OP23_shadow /= R_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2148) <= '1' when (EX_OP23_shadow /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(2149) <= '1' when (EX_OP23_shadow /= RIN_E_OP23_intermed_1) else '0'; dfp_trap_vector(2150) <= '1' when (EX_OP23_shadow /= R.X.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(2151) <= '1' when (EX_OP23_shadow /= V_E_OP23_shadow_intermed_1) else '0'; dfp_trap_vector(2152) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2153) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0'; dfp_trap_vector(2154) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(2155) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(2156) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0'; dfp_trap_vector(2157) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2158) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2159) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2160) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(2161) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2162) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2163) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_F_PC31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(2164) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2165) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(2166) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0'; dfp_trap_vector(2167) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R.F.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(2168) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2169) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2170) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2171) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2172) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2173) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(2174) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2175) <= '1' when (XC_TRAP_ADDRESS31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(2176) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow) else '0'; dfp_trap_vector(2177) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0'; dfp_trap_vector(2178) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2179) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2180) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2181) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(2182) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_F_PC31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2183) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2184) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2185) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2186) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2187) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2188) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2189) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2190) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2191) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2192) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2193) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2194) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2195) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2196) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2197) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2198) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2199) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2200) <= '1' when (XC_TRAP_ADDRESS31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2201) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2202) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2203) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2204) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(2205) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_F_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2206) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2207) <= '1' when (V_F_PC31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2208) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2209) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2210) <= '1' when (V_F_PC31DOWNTO2_shadow /= R.F.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2211) <= '1' when (V_F_PC31DOWNTO2_shadow /= VIR_ADDR31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2212) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2213) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2214) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2215) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2216) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2217) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2218) <= '1' when (V_F_PC31DOWNTO2_shadow /= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2219) <= '1' when (V_F_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2220) <= '1' when (V_F_PC31DOWNTO2_shadow /= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2221) <= '1' when (V_F_PC31DOWNTO2_shadow /= IR_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2222) <= '1' when (V_F_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2223) <= '1' when (V_F_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2224) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2225) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_1) else '0'; dfp_trap_vector(2226) <= '1' when (EX_OP231_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(2227) <= '1' when (EX_OP231_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2228) <= '1' when (EX_OP231_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(2229) <= '1' when (EX_OP231_shadow /= RIN_E_OP231_intermed_1) else '0'; dfp_trap_vector(2230) <= '1' when (EX_OP231_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2231) <= '1' when (EX_OP231_shadow /= R.E.OP2( 31 )) else '0'; dfp_trap_vector(2232) <= '1' when (EX_OP231_shadow /= V_E_OP231_shadow_intermed_1) else '0'; dfp_trap_vector(2233) <= '1' when (EX_OP231_shadow /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(2234) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_M_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2235) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2236) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2237) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R.X.CTRL.RD ( 7 DOWNTO 0 )) else '0'; dfp_trap_vector(2238) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2239) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2240) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_M_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2241) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2242) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2243) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_X_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2244) <= '1' when (V_X_CTRL_RD7DOWNTO0_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2245) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_X_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2246) <= '1' when (V_X_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_4) else '0'; dfp_trap_vector(2247) <= '1' when (V_X_CTRL_TRAP_shadow /= ICO_MEXC_intermed_5) else '0'; dfp_trap_vector(2248) <= '1' when (V_X_CTRL_TRAP_shadow /= R_E_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(2249) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_4) else '0'; dfp_trap_vector(2250) <= '1' when (V_X_CTRL_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_3) else '0'; dfp_trap_vector(2251) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_3) else '0'; dfp_trap_vector(2252) <= '1' when (V_X_CTRL_TRAP_shadow /= R_D_MEXC_intermed_4) else '0'; dfp_trap_vector(2253) <= '1' when (V_X_CTRL_TRAP_shadow /= R.X.CTRL.TRAP) else '0'; dfp_trap_vector(2254) <= '1' when (V_X_CTRL_TRAP_shadow /= V_M_CTRL_TRAP_shadow_intermed_2) else '0'; dfp_trap_vector(2255) <= '1' when (V_X_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_5) else '0'; dfp_trap_vector(2256) <= '1' when (V_X_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_3) else '0'; dfp_trap_vector(2257) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(2258) <= '1' when (V_X_CTRL_TRAP_shadow /= R_M_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2259) <= '1' when (V_X_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_5) else '0'; dfp_trap_vector(2260) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2261) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(2262) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= V_X_RESULT6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2263) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2264) <= '1' when (V_X_RESULT6DOWNTO0_shadow /= R_X_RESULT6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2265) <= '1' when (V_X_CTRL_PC_shadow /= RIN_D_PC_intermed_5) else '0'; dfp_trap_vector(2266) <= '1' when (V_X_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_4) else '0'; dfp_trap_vector(2267) <= '1' when (V_X_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(2268) <= '1' when (V_X_CTRL_PC_shadow /= V_E_CTRL_PC_shadow_intermed_3) else '0'; dfp_trap_vector(2269) <= '1' when (V_X_CTRL_PC_shadow /= R_M_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(2270) <= '1' when (V_X_CTRL_PC_shadow /= R.X.CTRL.PC) else '0'; dfp_trap_vector(2271) <= '1' when (V_X_CTRL_PC_shadow /= R_E_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(2272) <= '1' when (V_X_CTRL_PC_shadow /= RIN_M_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(2273) <= '1' when (V_X_CTRL_PC_shadow /= V_M_CTRL_PC_shadow_intermed_2) else '0'; dfp_trap_vector(2274) <= '1' when (V_X_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_4) else '0'; dfp_trap_vector(2275) <= '1' when (V_X_CTRL_PC_shadow /= R_D_PC_intermed_4) else '0'; dfp_trap_vector(2276) <= '1' when (V_X_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(2277) <= '1' when (V_X_CTRL_PC_shadow /= RIN_X_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(2278) <= '1' when (V_X_CTRL_PC_shadow /= V_D_PC_shadow_intermed_5) else '0'; dfp_trap_vector(2279) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_A_CTRL_ANNUL_intermed_5) else '0'; dfp_trap_vector(2280) <= '1' when (V_X_CTRL_WREG_shadow /= R.X.CTRL.WREG) else '0'; dfp_trap_vector(2281) <= '1' when (V_X_CTRL_WREG_shadow /= R_A_CTRL_ANNUL_intermed_4) else '0'; dfp_trap_vector(2282) <= '1' when (V_X_CTRL_WREG_shadow /= R_X_ANNUL_ALL_intermed_4) else '0'; dfp_trap_vector(2283) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_X_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(2284) <= '1' when (V_X_CTRL_WREG_shadow /= '1') else '0'; dfp_trap_vector(2285) <= '1' when (V_X_CTRL_WREG_shadow /= '0') else '0'; dfp_trap_vector(2286) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_M_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(2287) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_A_CTRL_WREG_intermed_4) else '0'; dfp_trap_vector(2288) <= '1' when (V_X_CTRL_WREG_shadow /= V_A_CTRL_WREG_shadow_intermed_4) else '0'; dfp_trap_vector(2289) <= '1' when (V_X_CTRL_WREG_shadow /= R_A_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(2290) <= '1' when (V_X_CTRL_WREG_shadow /= V_X_ANNUL_ALL_shadow_intermed_4) else '0'; dfp_trap_vector(2291) <= '1' when (V_X_CTRL_WREG_shadow /= R_M_CTRL_WREG_intermed_1) else '0'; dfp_trap_vector(2292) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_X_ANNUL_ALL_intermed_5) else '0'; dfp_trap_vector(2293) <= '1' when (V_X_CTRL_WREG_shadow /= V_M_CTRL_WREG_shadow_intermed_2) else '0'; dfp_trap_vector(2294) <= '1' when (V_X_CTRL_WREG_shadow /= R_E_CTRL_WREG_intermed_2) else '0'; dfp_trap_vector(2295) <= '1' when (V_X_CTRL_WREG_shadow /= V_A_CTRL_ANNUL_shadow_intermed_4) else '0'; dfp_trap_vector(2296) <= '1' when (V_X_CTRL_WREG_shadow /= RIN_E_CTRL_WREG_intermed_3) else '0'; dfp_trap_vector(2297) <= '1' when (V_X_CTRL_WREG_shadow /= V_E_CTRL_WREG_shadow_intermed_3) else '0'; dfp_trap_vector(2298) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2299) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2300) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2301) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2302) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2303) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2304) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2305) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2306) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2307) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2308) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R.X.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2309) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2310) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2311) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2312) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2313) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2314) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2315) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2316) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2317) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2318) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2319) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2320) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2321) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2322) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2323) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2324) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2325) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2326) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2327) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2328) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2329) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2330) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2331) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2332) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2333) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2334) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2335) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R.X.CTRL.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2336) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2337) <= '1' when (V_X_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2338) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2339) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2340) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2341) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2342) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2343) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0'; dfp_trap_vector(2344) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0'; dfp_trap_vector(2345) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2346) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2347) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2348) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2349) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2350) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2351) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2352) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_W_S_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2353) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2354) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2355) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2356) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2357) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_W_S_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2358) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2359) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2360) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R.W.S.TT ( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(2361) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(2362) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= V_M_RESULT1DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2363) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0'; dfp_trap_vector(2364) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= RIN_M_RESULT1DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2365) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= R_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2366) <= '1' when (V_M_RESULT1DOWNTO0_shadow /= RIN_M_RESULT1DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2367) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2368) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(2369) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_3) else '0'; dfp_trap_vector(2370) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_3) else '0'; dfp_trap_vector(2371) <= '1' when (V_X_DATA031_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(2372) <= '1' when (V_X_DATA031_shadow /= R.X.DATA ( 0 ) ( 31 )) else '0'; dfp_trap_vector(2373) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2374) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2375) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2376) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2377) <= '1' when (V_X_DATA031_shadow /= V_X_DATA031_shadow_intermed_2) else '0'; dfp_trap_vector(2378) <= '1' when (V_X_DATA031_shadow /= RIN_X_DATA031_intermed_2) else '0'; dfp_trap_vector(2379) <= '1' when (V_X_DATA031_shadow /= DCO_DATA031_intermed_1) else '0'; dfp_trap_vector(2380) <= '1' when (V_X_DATA031_shadow /= R_X_DATA031_intermed_1) else '0'; dfp_trap_vector(2381) <= '1' when (V_X_DATA031_shadow /= R.X.DATA ( 0 )( 31 )) else '0'; dfp_trap_vector(2382) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_3) else '0'; dfp_trap_vector(2383) <= '1' when (V_E_CTRL_INST19_shadow /= V_E_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2384) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(2385) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_3) else '0'; dfp_trap_vector(2386) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2387) <= '1' when (V_E_CTRL_INST19_shadow /= R.E.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(2388) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(2389) <= '1' when (V_E_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2390) <= '1' when (V_E_CTRL_INST19_shadow /= R_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2391) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(2392) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2393) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2394) <= '1' when (V_E_CTRL_INST20_shadow /= R.E.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(2395) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(2396) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2397) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_3) else '0'; dfp_trap_vector(2398) <= '1' when (V_E_CTRL_INST20_shadow /= V_E_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2399) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_3) else '0'; dfp_trap_vector(2400) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(2401) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2402) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2403) <= '1' when (V_E_CTRL_INST20_shadow /= R_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2404) <= '1' when (V_E_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2405) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(2406) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(2407) <= '1' when (V_X_DATA00_shadow /= R.X.DATA ( 0 ) ( 0 )) else '0'; dfp_trap_vector(2408) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_1) else '0'; dfp_trap_vector(2409) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_2) else '0'; dfp_trap_vector(2410) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(2411) <= '1' when (V_X_DATA00_shadow /= DCO_DATA00_intermed_1) else '0'; dfp_trap_vector(2412) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_3) else '0'; dfp_trap_vector(2413) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(2414) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_3) else '0'; dfp_trap_vector(2415) <= '1' when (V_X_DATA00_shadow /= R_X_DATA00_intermed_1) else '0'; dfp_trap_vector(2416) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_1) else '0'; dfp_trap_vector(2417) <= '1' when (V_X_DATA00_shadow /= DCO_DATA00_intermed_1) else '0'; dfp_trap_vector(2418) <= '1' when (V_X_DATA00_shadow /= V_X_DATA00_shadow_intermed_2) else '0'; dfp_trap_vector(2419) <= '1' when (V_X_DATA00_shadow /= R.X.DATA ( 0 )( 0 )) else '0'; dfp_trap_vector(2420) <= '1' when (V_X_DATA00_shadow /= RIN_X_DATA00_intermed_2) else '0'; dfp_trap_vector(2421) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2422) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2423) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2424) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2425) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R.X.DATA ( 0 ) ( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(2426) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2427) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2428) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2429) <= '1' when (V_X_DATA04DOWNTO0_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2430) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2431) <= '1' when (V_X_DATA04DOWNTO0_shadow /= R.X.DATA ( 0 )( 4 DOWNTO 0 )) else '0'; dfp_trap_vector(2432) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2433) <= '1' when (V_X_DATA04DOWNTO0_shadow /= V_X_DATA04DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2434) <= '1' when (V_X_DATA04DOWNTO0_shadow /= DCO_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2435) <= '1' when (V_X_DATA04DOWNTO0_shadow /= RIN_X_DATA04DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2436) <= '1' when (V_D_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2437) <= '1' when (V_D_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2438) <= '1' when (V_D_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2439) <= '1' when (V_D_PC31DOWNTO2_shadow /= R.D.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2440) <= '1' when (V_D_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2441) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(2442) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(2443) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_3) else '0'; dfp_trap_vector(2444) <= '1' when (V_E_CTRL_INST24_shadow /= R_E_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2445) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2446) <= '1' when (V_E_CTRL_INST24_shadow /= R.E.CTRL.INST ( 24 )) else '0'; dfp_trap_vector(2447) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_3) else '0'; dfp_trap_vector(2448) <= '1' when (V_E_CTRL_INST24_shadow /= V_E_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2449) <= '1' when (V_E_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2450) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(2451) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2452) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2453) <= '1' when (V_A_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2454) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2455) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(2456) <= '1' when (V_A_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(2457) <= '1' when (V_A_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2458) <= '1' when (V_A_CTRL_INST19_shadow /= R.A.CTRL.INST ( 19 )) else '0'; dfp_trap_vector(2459) <= '1' when (V_M_Y31_shadow /= RIN_M_Y31_intermed_1) else '0'; dfp_trap_vector(2460) <= '1' when (V_M_Y31_shadow /= V_M_Y31_shadow_intermed_2) else '0'; dfp_trap_vector(2461) <= '1' when (V_M_Y31_shadow /= RIN_M_Y31_intermed_2) else '0'; dfp_trap_vector(2462) <= '1' when (V_M_Y31_shadow /= R_M_Y31_intermed_1) else '0'; dfp_trap_vector(2463) <= '1' when (V_M_Y31_shadow /= R.M.Y ( 31 )) else '0'; dfp_trap_vector(2464) <= '1' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_1) else '0'; dfp_trap_vector(2465) <= '1' when (VDSU_CRDY2_shadow /= DSUR.CRDY ( 2 )) else '0'; dfp_trap_vector(2466) <= '1' when (VDSU_CRDY2_shadow /= VDSU_CRDY2_shadow_intermed_2) else '0'; dfp_trap_vector(2467) <= '1' when (VDSU_CRDY2_shadow /= DSUIN_CRDY2_intermed_2) else '0'; dfp_trap_vector(2468) <= '1' when (VDSU_CRDY2_shadow /= DSUR_CRDY2_intermed_1) else '0'; dfp_trap_vector(2469) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2470) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2471) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2472) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2473) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2474) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2475) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2476) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2477) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2478) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2479) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2480) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2481) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2482) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2483) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2484) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2485) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2486) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2487) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2488) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2489) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2490) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2491) <= '1' when (V_E_CTRL_INST_shadow /= R.E.CTRL.INST) else '0'; dfp_trap_vector(2492) <= '1' when (V_E_CTRL_INST_shadow /= DE_INST_shadow_intermed_2) else '0'; dfp_trap_vector(2493) <= '1' when (V_E_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_2) else '0'; dfp_trap_vector(2494) <= '1' when (V_E_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_2) else '0'; dfp_trap_vector(2495) <= '1' when (V_E_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2496) <= '1' when (V_E_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2497) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_D_CNT_intermed_3) else '0'; dfp_trap_vector(2498) <= '1' when (V_E_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_2) else '0'; dfp_trap_vector(2499) <= '1' when (V_E_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2500) <= '1' when (V_E_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_3) else '0'; dfp_trap_vector(2501) <= '1' when (V_E_CTRL_CNT_shadow /= R_D_CNT_intermed_2) else '0'; dfp_trap_vector(2502) <= '1' when (V_E_CTRL_CNT_shadow /= R.E.CTRL.CNT) else '0'; dfp_trap_vector(2503) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_2) else '0'; dfp_trap_vector(2504) <= '1' when (V_E_CTRL_CNT_shadow /= "00") else '0'; dfp_trap_vector(2505) <= '1' when (V_E_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2506) <= '1' when (V_E_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_2) else '0'; dfp_trap_vector(2507) <= '1' when (V_E_CTRL_TRAP_shadow /= ICO_MEXC_intermed_3) else '0'; dfp_trap_vector(2508) <= '1' when (V_E_CTRL_TRAP_shadow /= R.E.CTRL.TRAP) else '0'; dfp_trap_vector(2509) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(2510) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2511) <= '1' when (V_E_CTRL_TRAP_shadow /= R_D_MEXC_intermed_2) else '0'; dfp_trap_vector(2512) <= '1' when (V_E_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_3) else '0'; dfp_trap_vector(2513) <= '1' when (V_E_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2514) <= '1' when (V_E_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_3) else '0'; dfp_trap_vector(2515) <= '1' when (V_E_CTRL_PV_shadow /= R.E.CTRL.PV) else '0'; dfp_trap_vector(2516) <= '1' when (V_E_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2517) <= '1' when (V_E_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2518) <= '1' when (V_E_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_2) else '0'; dfp_trap_vector(2519) <= '1' when (V_E_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_2) else '0'; dfp_trap_vector(2520) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2521) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2522) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2523) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2524) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2525) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2526) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2527) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2528) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2529) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2530) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2531) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2532) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2533) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2534) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2535) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2536) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2537) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2538) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2539) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2540) <= '1' when (V_M_CTRL_INST_shadow /= R_E_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2541) <= '1' when (V_M_CTRL_INST_shadow /= R.M.CTRL.INST) else '0'; dfp_trap_vector(2542) <= '1' when (V_M_CTRL_INST_shadow /= DE_INST_shadow_intermed_3) else '0'; dfp_trap_vector(2543) <= '1' when (V_M_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_3) else '0'; dfp_trap_vector(2544) <= '1' when (V_M_CTRL_INST_shadow /= V_E_CTRL_INST_shadow_intermed_2) else '0'; dfp_trap_vector(2545) <= '1' when (V_M_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_3) else '0'; dfp_trap_vector(2546) <= '1' when (V_M_CTRL_INST_shadow /= RIN_M_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2547) <= '1' when (V_M_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_2) else '0'; dfp_trap_vector(2548) <= '1' when (V_M_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_2) else '0'; dfp_trap_vector(2549) <= '1' when (V_M_CTRL_CNT_shadow /= V_E_CTRL_CNT_shadow_intermed_2) else '0'; dfp_trap_vector(2550) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_D_CNT_intermed_4) else '0'; dfp_trap_vector(2551) <= '1' when (V_M_CTRL_CNT_shadow /= R.M.CTRL.CNT) else '0'; dfp_trap_vector(2552) <= '1' when (V_M_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_3) else '0'; dfp_trap_vector(2553) <= '1' when (V_M_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_2) else '0'; dfp_trap_vector(2554) <= '1' when (V_M_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_4) else '0'; dfp_trap_vector(2555) <= '1' when (V_M_CTRL_CNT_shadow /= R_D_CNT_intermed_3) else '0'; dfp_trap_vector(2556) <= '1' when (V_M_CTRL_CNT_shadow /= R_E_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2557) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_3) else '0'; dfp_trap_vector(2558) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_M_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2559) <= '1' when (V_M_CTRL_CNT_shadow /= "00") else '0'; dfp_trap_vector(2560) <= '1' when (V_M_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_2) else '0'; dfp_trap_vector(2561) <= '1' when (V_M_CTRL_TRAP_shadow /= V_A_CTRL_TRAP_shadow_intermed_3) else '0'; dfp_trap_vector(2562) <= '1' when (V_M_CTRL_TRAP_shadow /= ICO_MEXC_intermed_4) else '0'; dfp_trap_vector(2563) <= '1' when (V_M_CTRL_TRAP_shadow /= R_E_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2564) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_A_CTRL_TRAP_intermed_3) else '0'; dfp_trap_vector(2565) <= '1' when (V_M_CTRL_TRAP_shadow /= V_E_CTRL_TRAP_shadow_intermed_2) else '0'; dfp_trap_vector(2566) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_E_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(2567) <= '1' when (V_M_CTRL_TRAP_shadow /= R_D_MEXC_intermed_3) else '0'; dfp_trap_vector(2568) <= '1' when (V_M_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_4) else '0'; dfp_trap_vector(2569) <= '1' when (V_M_CTRL_TRAP_shadow /= R_A_CTRL_TRAP_intermed_2) else '0'; dfp_trap_vector(2570) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_M_CTRL_TRAP_intermed_1) else '0'; dfp_trap_vector(2571) <= '1' when (V_M_CTRL_TRAP_shadow /= R.M.CTRL.TRAP) else '0'; dfp_trap_vector(2572) <= '1' when (V_M_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_4) else '0'; dfp_trap_vector(2573) <= '1' when (V_M_CTRL_PV_shadow /= V_E_CTRL_PV_shadow_intermed_2) else '0'; dfp_trap_vector(2574) <= '1' when (V_M_CTRL_PV_shadow /= R.M.CTRL.PV) else '0'; dfp_trap_vector(2575) <= '1' when (V_M_CTRL_PV_shadow /= R_E_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2576) <= '1' when (V_M_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_2) else '0'; dfp_trap_vector(2577) <= '1' when (V_M_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_2) else '0'; dfp_trap_vector(2578) <= '1' when (V_M_CTRL_PV_shadow /= RIN_M_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2579) <= '1' when (V_M_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_3) else '0'; dfp_trap_vector(2580) <= '1' when (V_M_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_3) else '0'; dfp_trap_vector(2581) <= '1' when (V_X_CTRL_INST_shadow /= R_E_CTRL_INST_intermed_2) else '0'; dfp_trap_vector(2582) <= '1' when (V_X_CTRL_INST_shadow /= R_M_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2583) <= '1' when (V_X_CTRL_INST_shadow /= DE_INST_shadow_intermed_4) else '0'; dfp_trap_vector(2584) <= '1' when (V_X_CTRL_INST_shadow /= V_A_CTRL_INST_shadow_intermed_4) else '0'; dfp_trap_vector(2585) <= '1' when (V_X_CTRL_INST_shadow /= V_E_CTRL_INST_shadow_intermed_3) else '0'; dfp_trap_vector(2586) <= '1' when (V_X_CTRL_INST_shadow /= R.X.CTRL.INST) else '0'; dfp_trap_vector(2587) <= '1' when (V_X_CTRL_INST_shadow /= RIN_X_CTRL_INST_intermed_1) else '0'; dfp_trap_vector(2588) <= '1' when (V_X_CTRL_INST_shadow /= RIN_A_CTRL_INST_intermed_4) else '0'; dfp_trap_vector(2589) <= '1' when (V_X_CTRL_INST_shadow /= RIN_M_CTRL_INST_intermed_2) else '0'; dfp_trap_vector(2590) <= '1' when (V_X_CTRL_INST_shadow /= RIN_E_CTRL_INST_intermed_3) else '0'; dfp_trap_vector(2591) <= '1' when (V_X_CTRL_INST_shadow /= V_M_CTRL_INST_shadow_intermed_2) else '0'; dfp_trap_vector(2592) <= '1' when (V_X_CTRL_INST_shadow /= R_A_CTRL_INST_intermed_3) else '0'; dfp_trap_vector(2593) <= '1' when (V_X_CTRL_CNT_shadow /= V_E_CTRL_CNT_shadow_intermed_3) else '0'; dfp_trap_vector(2594) <= '1' when (V_X_CTRL_CNT_shadow /= R.X.CTRL.CNT) else '0'; dfp_trap_vector(2595) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_D_CNT_intermed_5) else '0'; dfp_trap_vector(2596) <= '1' when (V_X_CTRL_CNT_shadow /= R_M_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2597) <= '1' when (V_X_CTRL_CNT_shadow /= V_A_CTRL_CNT_shadow_intermed_4) else '0'; dfp_trap_vector(2598) <= '1' when (V_X_CTRL_CNT_shadow /= R_A_CTRL_CNT_intermed_3) else '0'; dfp_trap_vector(2599) <= '1' when (V_X_CTRL_CNT_shadow /= V_D_CNT_shadow_intermed_5) else '0'; dfp_trap_vector(2600) <= '1' when (V_X_CTRL_CNT_shadow /= R_D_CNT_intermed_4) else '0'; dfp_trap_vector(2601) <= '1' when (V_X_CTRL_CNT_shadow /= R_E_CTRL_CNT_intermed_2) else '0'; dfp_trap_vector(2602) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_X_CTRL_CNT_intermed_1) else '0'; dfp_trap_vector(2603) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_A_CTRL_CNT_intermed_4) else '0'; dfp_trap_vector(2604) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_M_CTRL_CNT_intermed_2) else '0'; dfp_trap_vector(2605) <= '1' when (V_X_CTRL_CNT_shadow /= "00") else '0'; dfp_trap_vector(2606) <= '1' when (V_X_CTRL_CNT_shadow /= RIN_E_CTRL_CNT_intermed_3) else '0'; dfp_trap_vector(2607) <= '1' when (V_X_CTRL_CNT_shadow /= V_M_CTRL_CNT_shadow_intermed_2) else '0'; dfp_trap_vector(2608) <= '1' when (V_X_CTRL_PV_shadow /= V_E_CTRL_PV_shadow_intermed_3) else '0'; dfp_trap_vector(2609) <= '1' when (V_X_CTRL_PV_shadow /= R_M_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2610) <= '1' when (V_X_CTRL_PV_shadow /= R_E_CTRL_PV_intermed_2) else '0'; dfp_trap_vector(2611) <= '1' when (V_X_CTRL_PV_shadow /= R_A_CTRL_PV_intermed_3) else '0'; dfp_trap_vector(2612) <= '1' when (V_X_CTRL_PV_shadow /= RIN_E_CTRL_PV_intermed_3) else '0'; dfp_trap_vector(2613) <= '1' when (V_X_CTRL_PV_shadow /= R.X.CTRL.PV) else '0'; dfp_trap_vector(2614) <= '1' when (V_X_CTRL_PV_shadow /= RIN_X_CTRL_PV_intermed_1) else '0'; dfp_trap_vector(2615) <= '1' when (V_X_CTRL_PV_shadow /= RIN_M_CTRL_PV_intermed_2) else '0'; dfp_trap_vector(2616) <= '1' when (V_X_CTRL_PV_shadow /= V_A_CTRL_PV_shadow_intermed_4) else '0'; dfp_trap_vector(2617) <= '1' when (V_X_CTRL_PV_shadow /= V_M_CTRL_PV_shadow_intermed_2) else '0'; dfp_trap_vector(2618) <= '1' when (V_X_CTRL_PV_shadow /= RIN_A_CTRL_PV_intermed_4) else '0'; dfp_trap_vector(2619) <= '1' when (V_E_CTRL_INST19_shadow /= V_A_CTRL_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2620) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_2) else '0'; dfp_trap_vector(2621) <= '1' when (V_E_CTRL_INST19_shadow /= RIN_E_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2622) <= '1' when (V_E_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_2) else '0'; dfp_trap_vector(2623) <= '1' when (V_E_CTRL_INST19_shadow /= R.E.CTRL.INST( 19 )) else '0'; dfp_trap_vector(2624) <= '1' when (V_E_CTRL_INST19_shadow /= R_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2625) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(2626) <= '1' when (V_E_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2627) <= '1' when (V_E_CTRL_INST20_shadow /= RIN_E_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2628) <= '1' when (V_E_CTRL_INST20_shadow /= R.E.CTRL.INST( 20 )) else '0'; dfp_trap_vector(2629) <= '1' when (V_E_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2630) <= '1' when (V_E_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2631) <= '1' when (V_E_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2632) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(2633) <= '1' when (V_E_CTRL_INST24_shadow /= RIN_E_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2634) <= '1' when (V_E_CTRL_INST24_shadow /= R.E.CTRL.INST( 24 )) else '0'; dfp_trap_vector(2635) <= '1' when (V_E_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2636) <= '1' when (V_E_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2637) <= '1' when (V_A_CTRL_INST19_shadow /= RIN_A_CTRL_INST19_intermed_1) else '0'; dfp_trap_vector(2638) <= '1' when (V_A_CTRL_INST19_shadow /= DE_INST19_shadow_intermed_1) else '0'; dfp_trap_vector(2639) <= '1' when (V_A_CTRL_INST19_shadow /= R.A.CTRL.INST( 19 )) else '0'; dfp_trap_vector(2640) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(2641) <= '1' when (V_F_PC31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2642) <= '1' when (V_F_PC31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(2643) <= '1' when (V_F_PC31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(2644) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2645) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(2646) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2647) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(2648) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2649) <= '1' when (V_F_PC31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0'; dfp_trap_vector(2650) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0'; dfp_trap_vector(2651) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0'; dfp_trap_vector(2652) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2653) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2654) <= '1' when (V_F_PC31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2655) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(2656) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2657) <= '1' when (V_F_PC31DOWNTO4_shadow /= XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(2658) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0'; dfp_trap_vector(2659) <= '1' when (V_F_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2660) <= '1' when (V_F_PC31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(2661) <= '1' when (V_F_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0'; dfp_trap_vector(2662) <= '1' when (V_F_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2663) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(2664) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= IR.ADDR( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(2665) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2666) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2667) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2668) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2669) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_6) else '0'; dfp_trap_vector(2670) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(2671) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2672) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2673) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2674) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(2675) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2676) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(2677) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2678) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0'; dfp_trap_vector(2679) <= '1' when (VIR_ADDR31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2680) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2681) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2682) <= '1' when (V_F_PC3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2683) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2684) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2685) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2686) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2687) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2688) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2689) <= '1' when (V_F_PC3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(2690) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2691) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2692) <= '1' when (V_F_PC3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2693) <= '1' when (V_F_PC3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2694) <= '1' when (V_F_PC3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(2695) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2696) <= '1' when (V_F_PC3DOWNTO2_shadow /= XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2697) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2698) <= '1' when (V_F_PC3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2699) <= '1' when (V_F_PC3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2700) <= '1' when (V_F_PC3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2701) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2702) <= '1' when (V_F_PC3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2703) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2704) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2705) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2706) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2707) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2708) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2709) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2710) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2711) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2712) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2713) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2714) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2715) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2716) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= IR.ADDR( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(2717) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2718) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2719) <= '1' when (VIR_ADDR3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2720) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2721) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2722) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_X_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2723) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R.X.CTRL.RD( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(2724) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_M_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2725) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2726) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2727) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2728) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2729) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2730) <= '1' when (V_X_CTRL_RD6DOWNTO0_shadow /= R_M_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2731) <= '1' when (V_M_CTRL_TT_shadow /= V_E_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(2732) <= '1' when (V_M_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_3) else '0'; dfp_trap_vector(2733) <= '1' when (V_M_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(2734) <= '1' when (V_M_CTRL_TT_shadow /= R.M.CTRL.TT) else '0'; dfp_trap_vector(2735) <= '1' when (V_M_CTRL_TT_shadow /= "000000") else '0'; dfp_trap_vector(2736) <= '1' when (V_M_CTRL_TT_shadow /= R_E_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(2737) <= '1' when (V_M_CTRL_TT_shadow /= RIN_M_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(2738) <= '1' when (V_M_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(2739) <= '1' when (V_M_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_3) else '0'; dfp_trap_vector(2740) <= '1' when (V_E_CTRL_LD_shadow /= R_A_CTRL_LD_intermed_1) else '0'; dfp_trap_vector(2741) <= '1' when (V_E_CTRL_LD_shadow /= RIN_A_CTRL_LD_intermed_2) else '0'; dfp_trap_vector(2742) <= '1' when (V_E_CTRL_LD_shadow /= R.E.CTRL.LD) else '0'; dfp_trap_vector(2743) <= '1' when (V_E_CTRL_LD_shadow /= RIN_E_CTRL_LD_intermed_1) else '0'; dfp_trap_vector(2744) <= '1' when (V_E_CTRL_LD_shadow /= V_A_CTRL_LD_shadow_intermed_2) else '0'; dfp_trap_vector(2745) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2746) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_7) else '0'; dfp_trap_vector(2747) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(2748) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(2749) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1) else '0'; dfp_trap_vector(2750) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_F_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2751) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2752) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2753) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(2754) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2755) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2756) <= '1' when (V_F_PC31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2757) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(2758) <= '1' when (V_F_PC31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1) else '0'; dfp_trap_vector(2759) <= '1' when (V_F_PC31DOWNTO12_shadow /= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1) else '0'; dfp_trap_vector(2760) <= '1' when (V_F_PC31DOWNTO12_shadow /= R.F.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(2761) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2762) <= '1' when (V_F_PC31DOWNTO12_shadow /= IR_ADDR31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2763) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2764) <= '1' when (V_F_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2765) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2766) <= '1' when (V_F_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_7) else '0'; dfp_trap_vector(2767) <= '1' when (V_F_PC31DOWNTO12_shadow /= VIR_ADDR31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2768) <= '1' when (V_F_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(2769) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(2770) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2771) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2772) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2773) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2774) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2775) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2776) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2777) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2778) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2779) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2780) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2781) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(2782) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(2783) <= '1' when (XC_VECTT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2784) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2785) <= '1' when (XC_VECTT3DOWNTO0_shadow /= R.X.CTRL.TT( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(2786) <= '1' when (XC_VECTT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2787) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2788) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2789) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2790) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2791) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2792) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_5) else '0'; dfp_trap_vector(2793) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5) else '0'; dfp_trap_vector(2794) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2795) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_W_S_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2796) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2797) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2798) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2799) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2800) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R.W.S.TT( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(2801) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2802) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2803) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2804) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2805) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= R_X_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2806) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2807) <= '1' when (V_W_S_TT3DOWNTO0_shadow /= XC_VECTT3DOWNTO0_shadow_intermed_1) else '0'; dfp_trap_vector(2808) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2809) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2810) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2811) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2812) <= '1' when (V_A_CTRL_PC31DOWNTO2_shadow /= R.A.CTRL.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2813) <= '1' when (V_X_DATA03_shadow /= V_X_DATA03_shadow_intermed_2) else '0'; dfp_trap_vector(2814) <= '1' when (V_X_DATA03_shadow /= DCO_DATA03_intermed_1) else '0'; dfp_trap_vector(2815) <= '1' when (V_X_DATA03_shadow /= RIN_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2816) <= '1' when (V_X_DATA03_shadow /= R_X_DATA03_intermed_1) else '0'; dfp_trap_vector(2817) <= '1' when (V_X_DATA03_shadow /= RIN_X_DATA03_intermed_2) else '0'; dfp_trap_vector(2818) <= '1' when (V_X_DATA03_shadow /= R.X.DATA ( 0 )( 3 )) else '0'; dfp_trap_vector(2819) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2820) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_6) else '0'; dfp_trap_vector(2821) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(2822) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(2823) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2824) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2825) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2826) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(2827) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= IRIN_ADDR31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2828) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(2829) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(2830) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= IR.ADDR( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(2831) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_X_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(2832) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(2833) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(2834) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_6) else '0'; dfp_trap_vector(2835) <= '1' when (VIR_ADDR31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(2836) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2837) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2838) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2839) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_X_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2840) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= IRIN_ADDR31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2841) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2842) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2843) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_M_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2844) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2845) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2846) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2847) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2848) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_X_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2849) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2850) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= IR.ADDR( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2851) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2852) <= '1' when (VIR_ADDR31DOWNTO2_shadow /= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2853) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_F_PC31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(2854) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_X_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(2855) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IR_ADDR31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2856) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R.F.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(2857) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= VIR_ADDR31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(2858) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_F_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2859) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(2860) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2861) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_6) else '0'; dfp_trap_vector(2862) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2863) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1) else '0'; dfp_trap_vector(2864) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_7) else '0'; dfp_trap_vector(2865) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_5) else '0'; dfp_trap_vector(2866) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2867) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_X_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2868) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= IRIN_ADDR31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2869) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(2870) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2871) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_7) else '0'; dfp_trap_vector(2872) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2873) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1) else '0'; dfp_trap_vector(2874) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_6) else '0'; dfp_trap_vector(2875) <= '1' when (XC_TRAP_ADDRESS31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2876) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2877) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_7) else '0'; dfp_trap_vector(2878) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= VIR_ADDR3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2879) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_7) else '0'; dfp_trap_vector(2880) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2881) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2882) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2883) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2884) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2885) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R.F.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(2886) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_X_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2887) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2888) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IRIN_ADDR3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2889) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2890) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1) else '0'; dfp_trap_vector(2891) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_6) else '0'; dfp_trap_vector(2892) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_F_PC3DOWNTO2_shadow_intermed_1) else '0'; dfp_trap_vector(2893) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_6) else '0'; dfp_trap_vector(2894) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= IR_ADDR3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2895) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2896) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= R_X_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2897) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2898) <= '1' when (XC_TRAP_ADDRESS3DOWNTO2_shadow /= RIN_F_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2899) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2900) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R_E_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2901) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2902) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2903) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R.M.CTRL.RD ( 7 DOWNTO 0 )) else '0'; dfp_trap_vector(2904) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2905) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2906) <= '1' when (V_M_CTRL_RD7DOWNTO0_shadow /= RIN_M_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2907) <= '1' when (V_M_CTRL_PC_shadow /= RIN_D_PC_intermed_4) else '0'; dfp_trap_vector(2908) <= '1' when (V_M_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_3) else '0'; dfp_trap_vector(2909) <= '1' when (V_M_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(2910) <= '1' when (V_M_CTRL_PC_shadow /= V_E_CTRL_PC_shadow_intermed_2) else '0'; dfp_trap_vector(2911) <= '1' when (V_M_CTRL_PC_shadow /= R.M.CTRL.PC) else '0'; dfp_trap_vector(2912) <= '1' when (V_M_CTRL_PC_shadow /= R_E_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(2913) <= '1' when (V_M_CTRL_PC_shadow /= RIN_M_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(2914) <= '1' when (V_M_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_3) else '0'; dfp_trap_vector(2915) <= '1' when (V_M_CTRL_PC_shadow /= R_D_PC_intermed_3) else '0'; dfp_trap_vector(2916) <= '1' when (V_M_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(2917) <= '1' when (V_M_CTRL_PC_shadow /= V_D_PC_shadow_intermed_4) else '0'; dfp_trap_vector(2918) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_M_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2919) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2920) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2921) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2922) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2923) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R.M.CTRL.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(2924) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2925) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2926) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2927) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= R_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2928) <= '1' when (V_M_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2929) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2930) <= '1' when (V_A_CTRL_INST20_shadow /= R.A.CTRL.INST ( 20 )) else '0'; dfp_trap_vector(2931) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_2) else '0'; dfp_trap_vector(2932) <= '1' when (V_A_CTRL_INST20_shadow /= V_A_CTRL_INST20_shadow_intermed_2) else '0'; dfp_trap_vector(2933) <= '1' when (V_A_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(2934) <= '1' when (V_A_CTRL_INST20_shadow /= R_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2935) <= '1' when (V_A_CTRL_INST20_shadow /= RIN_A_CTRL_INST20_intermed_1) else '0'; dfp_trap_vector(2936) <= '1' when (V_A_CTRL_INST20_shadow /= DE_INST20_shadow_intermed_1) else '0'; dfp_trap_vector(2937) <= '1' when (V_A_CTRL_INST20_shadow /= R.A.CTRL.INST( 20 )) else '0'; dfp_trap_vector(2938) <= '1' when (V_A_CTRL_INST24_shadow /= R_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2939) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_2) else '0'; dfp_trap_vector(2940) <= '1' when (V_A_CTRL_INST24_shadow /= R.A.CTRL.INST ( 24 )) else '0'; dfp_trap_vector(2941) <= '1' when (V_A_CTRL_INST24_shadow /= V_A_CTRL_INST24_shadow_intermed_2) else '0'; dfp_trap_vector(2942) <= '1' when (V_A_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(2943) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2944) <= '1' when (V_A_CTRL_INST24_shadow /= R.A.CTRL.INST( 24 )) else '0'; dfp_trap_vector(2945) <= '1' when (V_A_CTRL_INST24_shadow /= RIN_A_CTRL_INST24_intermed_1) else '0'; dfp_trap_vector(2946) <= '1' when (V_A_CTRL_INST24_shadow /= DE_INST24_shadow_intermed_1) else '0'; dfp_trap_vector(2947) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2948) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2949) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(2950) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_X_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2951) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_5) else '0'; dfp_trap_vector(2952) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(2953) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2954) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R.X.CTRL.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(2955) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(2956) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_M_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(2957) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_5) else '0'; dfp_trap_vector(2958) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(2959) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(2960) <= '1' when (V_X_CTRL_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(2961) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2962) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_5) else '0'; dfp_trap_vector(2963) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_5) else '0'; dfp_trap_vector(2964) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_M_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2965) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2966) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(2967) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_X_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(2968) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2969) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(2970) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(2971) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(2972) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(2973) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= R.X.CTRL.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(2974) <= '1' when (V_X_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(2975) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2976) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_M_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2977) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R_E_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2978) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2979) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(2980) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2981) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2982) <= '1' when (V_M_CTRL_RD6DOWNTO0_shadow /= R.M.CTRL.RD( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(2983) <= '1' when (V_E_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_2) else '0'; dfp_trap_vector(2984) <= '1' when (V_E_CTRL_TT_shadow /= R_A_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(2985) <= '1' when (V_E_CTRL_TT_shadow /= "000000") else '0'; dfp_trap_vector(2986) <= '1' when (V_E_CTRL_TT_shadow /= R.E.CTRL.TT) else '0'; dfp_trap_vector(2987) <= '1' when (V_E_CTRL_TT_shadow /= RIN_E_CTRL_TT_intermed_1) else '0'; dfp_trap_vector(2988) <= '1' when (V_E_CTRL_TT_shadow /= V_A_CTRL_TT_shadow_intermed_2) else '0'; dfp_trap_vector(2989) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(2990) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2991) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2992) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2993) <= '1' when (V_X_RESULT6DOWNTO03DOWNTO0_shadow /= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(2994) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_M_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(2995) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(2996) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_4) else '0'; dfp_trap_vector(2997) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4) else '0'; dfp_trap_vector(2998) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(2999) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3000) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(3001) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(3002) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_X_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3003) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= R.X.CTRL.TT( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(3004) <= '1' when (V_X_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(3005) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_M_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3006) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_5) else '0'; dfp_trap_vector(3007) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(3008) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(3009) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(3010) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3011) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(3012) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(3013) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3014) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R.X.CTRL.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(3015) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(3016) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_X_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3017) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_5) else '0'; dfp_trap_vector(3018) <= '1' when (V_X_CTRL_PC31DOWNTO12_shadow /= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(3019) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= R.E.CTRL.RD ( 7 DOWNTO 0 )) else '0'; dfp_trap_vector(3020) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(3021) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= RIN_A_CTRL_RD7DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3022) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= R_A_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3023) <= '1' when (V_E_CTRL_RD7DOWNTO0_shadow /= RIN_E_CTRL_RD7DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3024) <= '1' when (V_E_CTRL_PC_shadow /= RIN_D_PC_intermed_3) else '0'; dfp_trap_vector(3025) <= '1' when (V_E_CTRL_PC_shadow /= RIN_A_CTRL_PC_intermed_2) else '0'; dfp_trap_vector(3026) <= '1' when (V_E_CTRL_PC_shadow /= R_A_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(3027) <= '1' when (V_E_CTRL_PC_shadow /= R.E.CTRL.PC) else '0'; dfp_trap_vector(3028) <= '1' when (V_E_CTRL_PC_shadow /= V_A_CTRL_PC_shadow_intermed_2) else '0'; dfp_trap_vector(3029) <= '1' when (V_E_CTRL_PC_shadow /= R_D_PC_intermed_2) else '0'; dfp_trap_vector(3030) <= '1' when (V_E_CTRL_PC_shadow /= RIN_E_CTRL_PC_intermed_1) else '0'; dfp_trap_vector(3031) <= '1' when (V_E_CTRL_PC_shadow /= V_D_PC_shadow_intermed_3) else '0'; dfp_trap_vector(3032) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_D_PC31DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(3033) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_D_PC31DOWNTO2_intermed_3) else '0'; dfp_trap_vector(3034) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(3035) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_D_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3036) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_A_CTRL_PC31DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3037) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R_A_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3038) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= R.E.CTRL.PC( 31 DOWNTO 2 )) else '0'; dfp_trap_vector(3039) <= '1' when (V_E_CTRL_PC31DOWNTO2_shadow /= RIN_E_CTRL_PC31DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3040) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(3041) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(3042) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(3043) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_4) else '0'; dfp_trap_vector(3044) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(3045) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_M_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3046) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R.M.CTRL.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(3047) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_4) else '0'; dfp_trap_vector(3048) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(3049) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(3050) <= '1' when (V_M_CTRL_PC31DOWNTO4_shadow /= R_E_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3051) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(3052) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_4) else '0'; dfp_trap_vector(3053) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_4) else '0'; dfp_trap_vector(3054) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R.M.CTRL.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(3055) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_E_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3056) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(3057) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3058) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_M_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3059) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(3060) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(3061) <= '1' when (V_M_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3062) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= RIN_E_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3063) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= R.E.CTRL.RD( 6 DOWNTO 0 )) else '0'; dfp_trap_vector(3064) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(3065) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= R_A_CTRL_RD6DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3066) <= '1' when (V_E_CTRL_RD6DOWNTO0_shadow /= RIN_A_CTRL_RD6DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3067) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R.M.CTRL.TT( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(3068) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3069) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_3) else '0'; dfp_trap_vector(3070) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3) else '0'; dfp_trap_vector(3071) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= R_E_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3072) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_M_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3073) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(3074) <= '1' when (V_M_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3075) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R.M.CTRL.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(3076) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_4) else '0'; dfp_trap_vector(3077) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(3078) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(3079) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3080) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_E_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3081) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(3082) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3083) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_M_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3084) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(3085) <= '1' when (V_M_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_4) else '0'; dfp_trap_vector(3086) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(3087) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R_A_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3088) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(3089) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_3) else '0'; dfp_trap_vector(3090) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_3) else '0'; dfp_trap_vector(3091) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= RIN_E_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3092) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(3093) <= '1' when (V_E_CTRL_PC31DOWNTO4_shadow /= R.E.CTRL.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(3094) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3095) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_3) else '0'; dfp_trap_vector(3096) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_3) else '0'; dfp_trap_vector(3097) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R.E.CTRL.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(3098) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= R_A_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3099) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3100) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(3101) <= '1' when (V_E_CTRL_PC3DOWNTO2_shadow /= RIN_E_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3102) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= R_A_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3103) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= RIN_A_CTRL_TT3DOWNTO0_intermed_2) else '0'; dfp_trap_vector(3104) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2) else '0'; dfp_trap_vector(3105) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= R.E.CTRL.TT( 3 DOWNTO 0 )) else '0'; dfp_trap_vector(3106) <= '1' when (V_E_CTRL_TT3DOWNTO0_shadow /= RIN_E_CTRL_TT3DOWNTO0_intermed_1) else '0'; dfp_trap_vector(3107) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_3) else '0'; dfp_trap_vector(3108) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(3109) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R_A_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3110) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R.E.CTRL.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(3111) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3112) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_E_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3113) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_2) else '0'; dfp_trap_vector(3114) <= '1' when (V_E_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_3) else '0'; dfp_trap_vector(3115) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= RIN_A_CTRL_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3116) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= R.A.CTRL.PC( 31 DOWNTO 4 )) else '0'; dfp_trap_vector(3117) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= R_D_PC31DOWNTO4_intermed_1) else '0'; dfp_trap_vector(3118) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= V_D_PC31DOWNTO4_shadow_intermed_2) else '0'; dfp_trap_vector(3119) <= '1' when (V_A_CTRL_PC31DOWNTO4_shadow /= RIN_D_PC31DOWNTO4_intermed_2) else '0'; dfp_trap_vector(3120) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= R_D_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3121) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= V_D_PC3DOWNTO2_shadow_intermed_2) else '0'; dfp_trap_vector(3122) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= RIN_D_PC3DOWNTO2_intermed_2) else '0'; dfp_trap_vector(3123) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= R.A.CTRL.PC( 3 DOWNTO 2 )) else '0'; dfp_trap_vector(3124) <= '1' when (V_A_CTRL_PC3DOWNTO2_shadow /= RIN_A_CTRL_PC3DOWNTO2_intermed_1) else '0'; dfp_trap_vector(3125) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= V_D_PC31DOWNTO12_shadow_intermed_2) else '0'; dfp_trap_vector(3126) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= R.A.CTRL.PC( 31 DOWNTO 12 )) else '0'; dfp_trap_vector(3127) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= RIN_A_CTRL_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3128) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= R_D_PC31DOWNTO12_intermed_1) else '0'; dfp_trap_vector(3129) <= '1' when (V_A_CTRL_PC31DOWNTO12_shadow /= RIN_D_PC31DOWNTO12_intermed_2) else '0'; dfp_or_reduce : process(dfp_trap_vector) variable or_reduce_1565 : std_logic_vector(1564 downto 0); variable or_reduce_783 : std_logic_vector(782 downto 0); variable or_reduce_392 : std_logic_vector(391 downto 0); variable or_reduce_196 : std_logic_vector(195 downto 0); variable or_reduce_98 : std_logic_vector(97 downto 0); variable or_reduce_49 : std_logic_vector(48 downto 0); variable or_reduce_25 : std_logic_vector(24 downto 0); variable or_reduce_13 : std_logic_vector(12 downto 0); variable or_reduce_7 : std_logic_vector(6 downto 0); variable or_reduce_4 : std_logic_vector(3 downto 0); variable or_reduce_2 : std_logic_vector(1 downto 0); begin or_reduce_1565 := dfp_trap_vector(3129 downto 1565) OR dfp_trap_vector(1564 downto 0); or_reduce_783 := or_reduce_1565(1564 downto 782) OR ("0" & or_reduce_1565(781 downto 0)); or_reduce_392 := or_reduce_783(782 downto 391) OR ("0" & or_reduce_783(390 downto 0)); or_reduce_196 := or_reduce_392(391 downto 196) OR or_reduce_392(195 downto 0); or_reduce_98 := or_reduce_196(195 downto 98) OR or_reduce_196(97 downto 0); or_reduce_49 := or_reduce_98(97 downto 49) OR or_reduce_98(48 downto 0); or_reduce_25 := or_reduce_49(48 downto 24) OR ("0" & or_reduce_49(23 downto 0)); or_reduce_13 := or_reduce_25(24 downto 12) OR ("0" & or_reduce_25(11 downto 0)); or_reduce_7 := or_reduce_13(12 downto 6) OR ("0" & or_reduce_13(5 downto 0)); or_reduce_4 := or_reduce_7(6 downto 3) OR ("0" & or_reduce_7(2 downto 0)); or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0); or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1); end process; trap_enable_delay : process(clk) begin if(rising_edge(clk))then if(rstn = '0')then dfp_delay_start <= 15; elsif(dfp_delay_start /= 0)then dfp_delay_start <= dfp_delay_start - 1; end if; end if; end process; trap_mem : process(clk) begin if(rising_edge(clk))then if(rstn = '0')then dfp_trap_mem <= (others => '0'); elsif(dfp_delay_start = 0)then dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector; end if; end if; end process; handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0'; preg : process (sclk) begin if rising_edge(sclk) then rp <= rpin; if rstn = '0' then rp.error <= '0'; end if; end if; end process; reg : process (clk) begin if rising_edge(clk) then if (holdn = '1') then r <= rin; else r.x.ipend <= rin.x.ipend; r.m.werr <= rin.m.werr; if (holdn or ico.mds) = '0' then r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc; r.d.set <= rin.d.set; end if; if (holdn or dco.mds) = '0' then r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc; r.x.set <= rin.x.set; end if; end if; if rstn = '0' then r.w.s.s <= '1'; r.w.s.ps <= '1'; if need_extra_sync_reset(fabtech) /= 0 then r.d.inst <= (others => (others => '0')); r.x.mexc <= '0'; end if; end if; end if; end process; dsureg : process(clk) begin if rising_edge(clk) then if holdn = '1' then dsur <= dsuin; else dsur.crdy <= dsuin.crdy; end if; if holdn = '1' then ir <= irin; end if; end if; end process; dummy <= '1'; end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity echotest is port ( clk50 : in STD_LOGIC; sw : in STD_LOGIC_VECTOR (3 downto 0); ftdi_d : inout STD_LOGIC_VECTOR (7 downto 0); ftdi_rxe : in STD_LOGIC; ftdi_txe : in STD_LOGIC; ftdi_rd: out STD_LOGIC; ftdi_wr: out STD_LOGIC; ftdi_siwua: out STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0)); attribute PULLUP: string; attribute PULLUP of sw: signal is "TRUE" ); end echotest; architecture Behavioral of echotest is signal rd_wait : std_logic := '0'; signal wr_wait : std_logic := '0'; signal wr_done : std_logic := '0'; signal char : std_logic_vector(7 downto 0); begin process(clk50) variable char : std_logic_vector(7 downto 0); begin ftdi_siwua <= '1'; if rising_edge(clk50) then if (sw(0) = '1') then if (rd_wait = '1') then leds <= ftdi_d(7 downto 0); char := ftdi_d(7 downto 0); ftdi_rd <= '1'; rd_wait <= '0'; wr_wait <= '1'; elsif (wr_wait = '1') then if (ftdi_txe = '0') then ftdi_d <= char(7 downto 0); ftdi_wr <= '0'; wr_wait <= '0'; wr_done <= '1'; end if; elsif (wr_done = '1') then ftdi_wr <= '1'; wr_done <= '0'; ftdi_d <= "ZZZZZZZZ"; elsif (ftdi_rxe = '0') then ftdi_rd <= '0'; rd_wait <= '1'; end if; end if; end if; end process; end Behavioral;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0 6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy ++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7 zaL0QqT2uiy96OGZQH0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block M66qLl3QvTbyd7OZiLpiVNeM4XJubS1mfHkOvXfw1l7fIpYLHHkEKviYqsprqC4juUfqbM4jGOzs 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O 1FG6BAuoEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cusaPzk2vFOiZzK0ZhgWIEFifKmSOaQjUGDHZKCdYJFmdxLkotBPPjrVlqCOdv+nrAS98mWiWmMR /fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy TQHaRJ21xp30JAinv8c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_05_20 is end entity fg_05_20; architecture test of fg_05_20 is constant Tpd : delay_length := 2 ns; function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '0'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor op2(index) xor carry_in; carry_out := (op1(index) and op2(index)) or (carry_in and (op1(index) xor op2(index))); end loop; return result; end function "+"; function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is -- subtraction implemented by adding ((not bv2) + 1), ie -bv2 alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '1'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor (not op2(index)) xor carry_in; carry_out := (op1(index) and (not op2(index))) or (carry_in and (op1(index) xor (not op2(index)))); end loop; return result; end function "-"; type alu_function_type is (alu_pass_a, alu_add, alu_sub, alu_add_unsigned, alu_sub_unsigned, alu_and, alu_or); signal alu_function : alu_function_type := alu_pass_a; signal a, b : bit_vector(15 downto 0); signal functional_result, equivalent_result : bit_vector(15 downto 0); begin functional_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => functional_result ); begin -- code from book alu : with alu_function select result <= a + b after Tpd when alu_add | alu_add_unsigned, a - b after Tpd when alu_sub | alu_sub_unsigned, a and b after Tpd when alu_and, a or b after Tpd when alu_or, a after Tpd when alu_pass_a; -- end code from book end block functional_alu; -------------------------------------------------- equivalent_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => equivalent_result ); begin -- code from book alu : process is begin case alu_function is when alu_add | alu_add_unsigned => result <= a + b after Tpd; when alu_sub | alu_sub_unsigned => result <= a - b after Tpd; when alu_and => result <= a and b after Tpd; when alu_or => result <= a or b after Tpd; when alu_pass_a => result <= a after Tpd; end case; wait on alu_function, a, b; end process alu; -- end code from book end block equivalent_alu; -------------------------------------------------- stimulus : process is begin alu_function <= alu_add; wait for 10 ns; a <= X"000A"; wait for 10 ns; b <= X"0003"; wait for 10 ns; alu_function <= alu_sub; wait for 10 ns; alu_function <= alu_and; wait for 10 ns; alu_function <= alu_or; wait for 10 ns; alu_function <= alu_pass_a; wait for 10 ns; wait; end process stimulus; verifier : assert functional_result = equivalent_result report "Functional and equivalent models give different results"; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_05_20 is end entity fg_05_20; architecture test of fg_05_20 is constant Tpd : delay_length := 2 ns; function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '0'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor op2(index) xor carry_in; carry_out := (op1(index) and op2(index)) or (carry_in and (op1(index) xor op2(index))); end loop; return result; end function "+"; function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is -- subtraction implemented by adding ((not bv2) + 1), ie -bv2 alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '1'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor (not op2(index)) xor carry_in; carry_out := (op1(index) and (not op2(index))) or (carry_in and (op1(index) xor (not op2(index)))); end loop; return result; end function "-"; type alu_function_type is (alu_pass_a, alu_add, alu_sub, alu_add_unsigned, alu_sub_unsigned, alu_and, alu_or); signal alu_function : alu_function_type := alu_pass_a; signal a, b : bit_vector(15 downto 0); signal functional_result, equivalent_result : bit_vector(15 downto 0); begin functional_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => functional_result ); begin -- code from book alu : with alu_function select result <= a + b after Tpd when alu_add | alu_add_unsigned, a - b after Tpd when alu_sub | alu_sub_unsigned, a and b after Tpd when alu_and, a or b after Tpd when alu_or, a after Tpd when alu_pass_a; -- end code from book end block functional_alu; -------------------------------------------------- equivalent_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => equivalent_result ); begin -- code from book alu : process is begin case alu_function is when alu_add | alu_add_unsigned => result <= a + b after Tpd; when alu_sub | alu_sub_unsigned => result <= a - b after Tpd; when alu_and => result <= a and b after Tpd; when alu_or => result <= a or b after Tpd; when alu_pass_a => result <= a after Tpd; end case; wait on alu_function, a, b; end process alu; -- end code from book end block equivalent_alu; -------------------------------------------------- stimulus : process is begin alu_function <= alu_add; wait for 10 ns; a <= X"000A"; wait for 10 ns; b <= X"0003"; wait for 10 ns; alu_function <= alu_sub; wait for 10 ns; alu_function <= alu_and; wait for 10 ns; alu_function <= alu_or; wait for 10 ns; alu_function <= alu_pass_a; wait for 10 ns; wait; end process stimulus; verifier : assert functional_result = equivalent_result report "Functional and equivalent models give different results"; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity fg_05_20 is end entity fg_05_20; architecture test of fg_05_20 is constant Tpd : delay_length := 2 ns; function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '0'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor op2(index) xor carry_in; carry_out := (op1(index) and op2(index)) or (carry_in and (op1(index) xor op2(index))); end loop; return result; end function "+"; function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is -- subtraction implemented by adding ((not bv2) + 1), ie -bv2 alias op1 : bit_vector(1 to bv1'length) is bv1; alias op2 : bit_vector(1 to bv2'length) is bv2; variable result : bit_vector(1 to bv1'length); variable carry_in : bit; variable carry_out : bit := '1'; begin for index in result'reverse_range loop carry_in := carry_out; -- of previous bit result(index) := op1(index) xor (not op2(index)) xor carry_in; carry_out := (op1(index) and (not op2(index))) or (carry_in and (op1(index) xor (not op2(index)))); end loop; return result; end function "-"; type alu_function_type is (alu_pass_a, alu_add, alu_sub, alu_add_unsigned, alu_sub_unsigned, alu_and, alu_or); signal alu_function : alu_function_type := alu_pass_a; signal a, b : bit_vector(15 downto 0); signal functional_result, equivalent_result : bit_vector(15 downto 0); begin functional_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => functional_result ); begin -- code from book alu : with alu_function select result <= a + b after Tpd when alu_add | alu_add_unsigned, a - b after Tpd when alu_sub | alu_sub_unsigned, a and b after Tpd when alu_and, a or b after Tpd when alu_or, a after Tpd when alu_pass_a; -- end code from book end block functional_alu; -------------------------------------------------- equivalent_alu : block is port ( result : out bit_vector(15 downto 0) ); port map ( result => equivalent_result ); begin -- code from book alu : process is begin case alu_function is when alu_add | alu_add_unsigned => result <= a + b after Tpd; when alu_sub | alu_sub_unsigned => result <= a - b after Tpd; when alu_and => result <= a and b after Tpd; when alu_or => result <= a or b after Tpd; when alu_pass_a => result <= a after Tpd; end case; wait on alu_function, a, b; end process alu; -- end code from book end block equivalent_alu; -------------------------------------------------- stimulus : process is begin alu_function <= alu_add; wait for 10 ns; a <= X"000A"; wait for 10 ns; b <= X"0003"; wait for 10 ns; alu_function <= alu_sub; wait for 10 ns; alu_function <= alu_and; wait for 10 ns; alu_function <= alu_or; wait for 10 ns; alu_function <= alu_pass_a; wait for 10 ns; wait; end process stimulus; verifier : assert functional_result = equivalent_result report "Functional and equivalent models give different results"; end architecture test;
--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; library bitvis_vip_sbi; library bitvis_vip_uart; library bitvis_uart; library bitvis_vip_clock_generator; -- Test harness entity entity uart_vvc_demo_th is end entity; -- Test harness architecture architecture struct of uart_vvc_demo_th is -- DSP interface and general control signals signal clk : std_logic := '0'; signal arst : std_logic := '0'; -- SBI VVC signals signal cs : std_logic; signal addr : unsigned(2 downto 0); signal wr : std_logic; signal rd : std_logic; signal wdata : std_logic_vector(7 downto 0); signal rdata : std_logic_vector(7 downto 0); signal ready : std_logic; -- UART VVC signals signal uart_vvc_rx : std_logic := '1'; signal uart_vvc_tx : std_logic := '1'; constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz constant C_CLOCK_GEN : natural := 1; begin ----------------------------------------------------------------------------- -- Instantiate the concurrent procedure that initializes UVVM ----------------------------------------------------------------------------- i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine; ----------------------------------------------------------------------------- -- Instantiate DUT ----------------------------------------------------------------------------- i_uart: entity work.uart port map ( -- DSP interface and general control signals clk => clk, arst => arst, -- CPU interface cs => cs, addr => addr, wr => wr, rd => rd, wdata => wdata, rdata => rdata, -- UART signals rx_a => uart_vvc_tx, tx => uart_vvc_rx ); ----------------------------------------------------------------------------- -- SBI VVC ----------------------------------------------------------------------------- i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc generic map( GC_ADDR_WIDTH => 3, GC_DATA_WIDTH => 8, GC_INSTANCE_IDX => 1 ) port map( clk => clk, sbi_vvc_master_if.cs => cs, sbi_vvc_master_if.rena => rd, sbi_vvc_master_if.wena => wr, sbi_vvc_master_if.addr => addr, sbi_vvc_master_if.wdata => wdata, sbi_vvc_master_if.ready => ready, sbi_vvc_master_if.rdata => rdata ); ----------------------------------------------------------------------------- -- UART VVC ----------------------------------------------------------------------------- i1_uart_vvc: entity bitvis_vip_uart.uart_vvc generic map( GC_DATA_WIDTH => 8, GC_INSTANCE_IDX => 1 ) port map( uart_vvc_rx => uart_vvc_rx, uart_vvc_tx => uart_vvc_tx ); -- Static '1' ready signal for the SBI VVC ready <= '1'; -- Toggle the reset after 5 clock periods p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD; ----------------------------------------------------------------------------- -- Clock Generator VVC ----------------------------------------------------------------------------- i_clock_generator_vvc : entity bitvis_vip_clock_generator.clock_generator_vvc generic map( GC_INSTANCE_IDX => C_CLOCK_GEN, GC_CLOCK_NAME => "Clock", GC_CLOCK_PERIOD => C_CLK_PERIOD, GC_CLOCK_HIGH_TIME => C_CLK_PERIOD / 2 ) port map( clk => clk ); end struct;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity clk_div is Port ( reset : in STD_LOGIC; clkin : in STD_LOGIC; clkout : out STD_LOGIC); end clk_div; architecture behavioral of clk_div is constant CLK_PERIOD : integer := 27*10**6/2; signal cnt : integer := CLK_PERIOD; begin CLKDIV : process (clkin,reset) begin if reset = '1' then cnt <= CLK_PERIOD; clkout <= '0'; elsif clkin = '1' and clkin'event then if cnt = 0 then clkout <= '1'; cnt <= CLK_PERIOD; else clkout <= '0'; cnt <= cnt - 1; end if; end if; end process; end behavioral;
entity econcat2 is end econcat2; architecture behav of econcat2 is constant c1 : string (1 to 5) := "hello"; constant c2 : string (6 downto 1) := " world"; constant r : string := c1 & c2; begin process begin case True is when "&" (c1, c2) = "hello world" => null; when false => null; end case; wait; end process; end;
-- NEED RESULT: ARCH00076.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: One transport transaction occurred on signal asg with simple name on LHS passed -- NEED RESULT: ARCH00076: Old transactions were removed on signal asg with simple name on LHS passed -- NEED RESULT: P17: Transport transactions entirely completed passed -- NEED RESULT: P16: Transport transactions entirely completed passed -- NEED RESULT: P15: Transport transactions entirely completed passed -- NEED RESULT: P14: Transport transactions entirely completed passed -- NEED RESULT: P13: Transport transactions entirely completed passed -- NEED RESULT: P12: Transport transactions entirely completed passed -- NEED RESULT: P11: Transport transactions entirely completed passed -- NEED RESULT: P10: Transport transactions entirely completed passed -- NEED RESULT: P9: Transport transactions entirely completed passed -- NEED RESULT: P8: Transport transactions entirely completed passed -- NEED RESULT: P7: Transport transactions entirely completed passed -- NEED RESULT: P6: Transport transactions entirely completed passed -- NEED RESULT: P5: Transport transactions entirely completed passed -- NEED RESULT: P4: Transport transactions entirely completed passed -- NEED RESULT: P3: Transport transactions entirely completed passed -- NEED RESULT: P2: Transport transactions entirely completed passed -- NEED RESULT: P1: Transport transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00076 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (2) -- 8.3 (3) -- 8.3 (5) -- 8.3.1 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00076(ARCH00076) -- ENT00076_Test_Bench(ARCH00076_Test_Bench) -- -- REVISION HISTORY: -- -- 07-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00076 is port ( s_boolean : inout boolean ; s_bit : inout bit ; s_severity_level : inout severity_level ; s_character : inout character ; s_st_enum1 : inout st_enum1 ; s_integer : inout integer ; s_st_int1 : inout st_int1 ; s_time : inout time ; s_st_phys1 : inout st_phys1 ; s_real : inout real ; s_st_real1 : inout st_real1 ; s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ; s_st_arr1 : inout st_arr1 ; s_st_arr2 : inout st_arr2 ; s_st_arr3 : inout st_arr3 ) ; subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- -- procedure Proc1 ( signal s_boolean : inout boolean ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_boolean : out chk_sig_type ) is begin case counter is when 0 => s_boolean <= transport c_boolean_2 after 10 ns, c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P1" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_boolean <= transport c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (savtime + 10 ns) = Std.Standard.Now ; s_boolean <= transport c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_boolean <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- procedure Proc2 ( signal s_bit : inout bit ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_bit : out chk_sig_type ) is begin case counter is when 0 => s_bit <= transport c_bit_2 after 10 ns, c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P2" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_bit <= transport c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (savtime + 10 ns) = Std.Standard.Now ; s_bit <= transport c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_bit <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc2 ; -- procedure Proc3 ( signal s_severity_level : inout severity_level ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_severity_level : out chk_sig_type ) is begin case counter is when 0 => s_severity_level <= transport c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P3" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_severity_level <= transport c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (savtime + 10 ns) = Std.Standard.Now ; s_severity_level <= transport c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_severity_level <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc3 ; -- procedure Proc4 ( signal s_character : inout character ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_character : out chk_sig_type ) is begin case counter is when 0 => s_character <= transport c_character_2 after 10 ns, c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P4" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_character <= transport c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (savtime + 10 ns) = Std.Standard.Now ; s_character <= transport c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_character <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc4 ; -- procedure Proc5 ( signal s_st_enum1 : inout st_enum1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_enum1 : out chk_sig_type ) is begin case counter is when 0 => s_st_enum1 <= transport c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P5" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_enum1 <= transport c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_enum1 <= transport c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_enum1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc5 ; -- procedure Proc6 ( signal s_integer : inout integer ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_integer : out chk_sig_type ) is begin case counter is when 0 => s_integer <= transport c_integer_2 after 10 ns, c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P6" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_integer <= transport c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (savtime + 10 ns) = Std.Standard.Now ; s_integer <= transport c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_integer <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc6 ; -- procedure Proc7 ( signal s_st_int1 : inout st_int1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_int1 : out chk_sig_type ) is begin case counter is when 0 => s_st_int1 <= transport c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P7" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_int1 <= transport c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_int1 <= transport c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_int1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc7 ; -- procedure Proc8 ( signal s_time : inout time ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_time : out chk_sig_type ) is begin case counter is when 0 => s_time <= transport c_time_2 after 10 ns, c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P8" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_time <= transport c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (savtime + 10 ns) = Std.Standard.Now ; s_time <= transport c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_time <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc8 ; -- procedure Proc9 ( signal s_st_phys1 : inout st_phys1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_phys1 : out chk_sig_type ) is begin case counter is when 0 => s_st_phys1 <= transport c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P9" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_phys1 <= transport c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_phys1 <= transport c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_phys1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc9 ; -- procedure Proc10 ( signal s_real : inout real ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_real : out chk_sig_type ) is begin case counter is when 0 => s_real <= transport c_real_2 after 10 ns, c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P10" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_real <= transport c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (savtime + 10 ns) = Std.Standard.Now ; s_real <= transport c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_real <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc10 ; -- procedure Proc11 ( signal s_st_real1 : inout st_real1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_real1 : out chk_sig_type ) is begin case counter is when 0 => s_st_real1 <= transport c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P11" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_real1 <= transport c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_real1 <= transport c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_real1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc11 ; -- procedure Proc12 ( signal s_st_rec1 : inout st_rec1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec1 : out chk_sig_type ) is begin case counter is when 0 => s_st_rec1 <= transport c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P12" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec1 <= transport c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec1 <= transport c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc12 ; -- procedure Proc13 ( signal s_st_rec2 : inout st_rec2 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec2 : out chk_sig_type ) is begin case counter is when 0 => s_st_rec2 <= transport c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P13" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec2 <= transport c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec2 <= transport c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc13 ; -- procedure Proc14 ( signal s_st_rec3 : inout st_rec3 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_rec3 : out chk_sig_type ) is begin case counter is when 0 => s_st_rec3 <= transport c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P14" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_rec3 <= transport c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_rec3 <= transport c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_rec3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc14 ; -- procedure Proc15 ( signal s_st_arr1 : inout st_arr1 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr1 : out chk_sig_type ) is begin case counter is when 0 => s_st_arr1 <= transport c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P15" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr1 <= transport c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 <= transport c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc15 ; -- procedure Proc16 ( signal s_st_arr2 : inout st_arr2 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr2 : out chk_sig_type ) is begin case counter is when 0 => s_st_arr2 <= transport c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P16" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr2 <= transport c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 <= transport c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc16 ; -- procedure Proc17 ( signal s_st_arr3 : inout st_arr3 ; variable counter : inout integer ; variable correct : inout boolean ; variable savtime : inout time ; signal chk_st_arr3 : out chk_sig_type ) is begin case counter is when 0 => s_st_arr3 <= transport c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00076.P17" , "Multi transport transactions occurred on signal " & "asg with simple name on LHS", correct ) ; s_st_arr3 <= transport c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 <= transport c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00076" , "One transport transaction occurred on signal " & "asg with simple name on LHS", correct ) ; test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00076" , "Old transactions were removed on signal " & "asg with simple name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc17 ; -- -- end ENT00076 ; -- architecture ARCH00076 of ENT00076 is begin PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Transport transactions entirely completed", chk_boolean = 4 ) ; end if ; end process PGEN_CHKP_1 ; -- P1 : process ( s_boolean ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc1 ( s_boolean, counter, correct, savtime, chk_boolean ) ; end process P1 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Transport transactions entirely completed", chk_bit = 4 ) ; end if ; end process PGEN_CHKP_2 ; -- P2 : process ( s_bit ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc2 ( s_bit, counter, correct, savtime, chk_bit ) ; end process P2 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Transport transactions entirely completed", chk_severity_level = 4 ) ; end if ; end process PGEN_CHKP_3 ; -- P3 : process ( s_severity_level ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc3 ( s_severity_level, counter, correct, savtime, chk_severity_level ) ; end process P3 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Transport transactions entirely completed", chk_character = 4 ) ; end if ; end process PGEN_CHKP_4 ; -- P4 : process ( s_character ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc4 ( s_character, counter, correct, savtime, chk_character ) ; end process P4 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Transport transactions entirely completed", chk_st_enum1 = 4 ) ; end if ; end process PGEN_CHKP_5 ; -- P5 : process ( s_st_enum1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc5 ( s_st_enum1, counter, correct, savtime, chk_st_enum1 ) ; end process P5 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Transport transactions entirely completed", chk_integer = 4 ) ; end if ; end process PGEN_CHKP_6 ; -- P6 : process ( s_integer ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc6 ( s_integer, counter, correct, savtime, chk_integer ) ; end process P6 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Transport transactions entirely completed", chk_st_int1 = 4 ) ; end if ; end process PGEN_CHKP_7 ; -- P7 : process ( s_st_int1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc7 ( s_st_int1, counter, correct, savtime, chk_st_int1 ) ; end process P7 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Transport transactions entirely completed", chk_time = 4 ) ; end if ; end process PGEN_CHKP_8 ; -- P8 : process ( s_time ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc8 ( s_time, counter, correct, savtime, chk_time ) ; end process P8 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Transport transactions entirely completed", chk_st_phys1 = 4 ) ; end if ; end process PGEN_CHKP_9 ; -- P9 : process ( s_st_phys1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc9 ( s_st_phys1, counter, correct, savtime, chk_st_phys1 ) ; end process P9 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Transport transactions entirely completed", chk_real = 4 ) ; end if ; end process PGEN_CHKP_10 ; -- P10 : process ( s_real ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc10 ( s_real, counter, correct, savtime, chk_real ) ; end process P10 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Transport transactions entirely completed", chk_st_real1 = 4 ) ; end if ; end process PGEN_CHKP_11 ; -- P11 : process ( s_st_real1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc11 ( s_st_real1, counter, correct, savtime, chk_st_real1 ) ; end process P11 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Transport transactions entirely completed", chk_st_rec1 = 4 ) ; end if ; end process PGEN_CHKP_12 ; -- P12 : process ( s_st_rec1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc12 ( s_st_rec1, counter, correct, savtime, chk_st_rec1 ) ; end process P12 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Transport transactions entirely completed", chk_st_rec2 = 4 ) ; end if ; end process PGEN_CHKP_13 ; -- P13 : process ( s_st_rec2 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc13 ( s_st_rec2, counter, correct, savtime, chk_st_rec2 ) ; end process P13 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Transport transactions entirely completed", chk_st_rec3 = 4 ) ; end if ; end process PGEN_CHKP_14 ; -- P14 : process ( s_st_rec3 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc14 ( s_st_rec3, counter, correct, savtime, chk_st_rec3 ) ; end process P14 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Transport transactions entirely completed", chk_st_arr1 = 4 ) ; end if ; end process PGEN_CHKP_15 ; -- P15 : process ( s_st_arr1 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc15 ( s_st_arr1, counter, correct, savtime, chk_st_arr1 ) ; end process P15 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Transport transactions entirely completed", chk_st_arr2 = 4 ) ; end if ; end process PGEN_CHKP_16 ; -- P16 : process ( s_st_arr2 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc16 ( s_st_arr2, counter, correct, savtime, chk_st_arr2 ) ; end process P16 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Transport transactions entirely completed", chk_st_arr3 = 4 ) ; end if ; end process PGEN_CHKP_17 ; -- P17 : process ( s_st_arr3 ) variable counter : integer := 0 ; variable correct : boolean ; variable savtime : time ; begin Proc17 ( s_st_arr3, counter, correct, savtime, chk_st_arr3 ) ; end process P17 ; -- -- end ARCH00076 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00076_Test_Bench is signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- end ENT00076_Test_Bench ; -- architecture ARCH00076_Test_Bench of ENT00076_Test_Bench is begin L1: block component UUT port ( s_boolean : inout boolean ; s_bit : inout bit ; s_severity_level : inout severity_level ; s_character : inout character ; s_st_enum1 : inout st_enum1 ; s_integer : inout integer ; s_st_int1 : inout st_int1 ; s_time : inout time ; s_st_phys1 : inout st_phys1 ; s_real : inout real ; s_st_real1 : inout st_real1 ; s_st_rec1 : inout st_rec1 ; s_st_rec2 : inout st_rec2 ; s_st_rec3 : inout st_rec3 ; s_st_arr1 : inout st_arr1 ; s_st_arr2 : inout st_arr2 ; s_st_arr3 : inout st_arr3 ) ; end component ; -- for CIS1 : UUT use entity WORK.ENT00076 ( ARCH00076 ) ; begin CIS1 : UUT port map ( s_boolean , s_bit , s_severity_level , s_character , s_st_enum1 , s_integer , s_st_int1 , s_time , s_st_phys1 , s_real , s_st_real1 , s_st_rec1 , s_st_rec2 , s_st_rec3 , s_st_arr1 , s_st_arr2 , s_st_arr3 ) ; end block L1 ; end ARCH00076_Test_Bench ;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := altera; constant CFG_MEMTECH : integer := altera; constant CFG_PADTECH : integer := altera; constant CFG_TRANSTECH : integer := GTP0; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := inferred; constant CFG_CLKMUL : integer := 2; constant CFG_CLKDIV : integer := 2; constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 2 + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 0; constant CFG_SVT : integer := 0; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (2); constant CFG_PWD : integer := 0*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 2; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 0; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 2; constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 0; constant CFG_ITLBNUM : integer := 2; constant CFG_DTLBNUM : integer := 2; constant CFG_TLB_TYPE : integer := 1 + 0*2; constant CFG_TLB_REP : integer := 1; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 0 + 64*0; constant CFG_ATBSZ : integer := 0; constant CFG_AHBPF : integer := 0; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; constant CFG_NP_ASI : integer := 0; constant CFG_WRPSR : integer := 0; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 0; -- Ethernet DSU constant CFG_DSU_ETH : integer := 0 + 0 + 0; constant CFG_ETH_BUF : integer := 1; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000009#; -- PROM/SRAM controller constant CFG_SRCTRL : integer := 1; constant CFG_SRCTRL_PROMWS : integer := (3); constant CFG_SRCTRL_RAMWS : integer := (2); constant CFG_SRCTRL_IOWS : integer := (0); constant CFG_SRCTRL_RMW : integer := 1; constant CFG_SRCTRL_8BIT : integer := 0; constant CFG_SRCTRL_SRBANKS : integer := 1; constant CFG_SRCTRL_BANKSZ : integer := 0; constant CFG_SRCTRL_ROMASEL : integer := (19); -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 0; constant CFG_MCTRL_RAM8BIT : integer := 0; constant CFG_MCTRL_RAM16BIT : integer := 0; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- SDRAM controller constant CFG_SDCTRL : integer := 0; constant CFG_SDCTRL_INVCLK : integer := 0; constant CFG_SDCTRL_SD64 : integer := 0; constant CFG_SDCTRL_PAGE : integer := 0 + 0; -- AHB ROM constant CFG_AHBROMEN : integer := 0; constant CFG_AHBROPIP : integer := 0; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#000#; constant CFG_ROMMASK : integer := 16#E00# + 16#000#; -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 0; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; -- CAN 2.0 interface constant CFG_CAN : integer := 0; constant CFG_CANIO : integer := 16#0#; constant CFG_CANIRQ : integer := 0; constant CFG_CANLOOP : integer := 0; constant CFG_CAN_SYNCRST : integer := 0; constant CFG_CANFT : integer := 0; -- Spacewire interface constant CFG_SPW_EN : integer := 0; constant CFG_SPW_NUM : integer := 1; constant CFG_SPW_AHBFIFO : integer := 4; constant CFG_SPW_RXFIFO : integer := 16; constant CFG_SPW_RMAP : integer := 0; constant CFG_SPW_RMAPBUF : integer := 4; constant CFG_SPW_RMAPCRC : integer := 0; constant CFG_SPW_NETLIST : integer := 0; constant CFG_SPW_FT : integer := 0; constant CFG_SPW_GRSPW : integer := 2; constant CFG_SPW_RXUNAL : integer := 0; constant CFG_SPW_DMACHAN : integer := 1; constant CFG_SPW_PORTS : integer := 1; constant CFG_SPW_INPUT : integer := 2; constant CFG_SPW_OUTPUT : integer := 0; constant CFG_SPW_RTSAME : integer := 0; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 1; -- UART 2 constant CFG_UART2_ENABLE : integer := 0; constant CFG_UART2_FIFO : integer := 1; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 0; constant CFG_GRGPIO_IMASK : integer := 16#0000#; constant CFG_GRGPIO_WIDTH : integer := 1; -- GRLIB debugging constant CFG_DUART : integer := 0; end;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; ENTITY test_datapath_averager IS END test_datapath_averager; ARCHITECTURE behavior OF test_datapath_averager IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT datapath_averager PORT( mem_addr : IN STD_LOGIC_VECTOR(5 downto 0); window_val : IN std_logic_vector(1 downto 0); overflow : OUT std_logic; clk : IN std_logic; masterReset : IN std_logic; input_val : OUT std_logic_vector(7 downto 0); average_val : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal mem_addr : std_logic_vector( 5 downto 0) := "000000"; signal window_val : std_logic_vector(1 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal masterReset : std_logic := '0'; --BiDirs signal overflow : std_logic := '0'; --Outputs signal input_val : std_logic_vector(7 downto 0) := (others => '0'); signal average_val : std_logic_vector(7 downto 0) := (others => '0'); -- Clock period definitions constant clk_period : time := 10 ns; signal counter : std_logic_vector( 5 downto 0) := (others => '0'); BEGIN -- Instantiate the Unit Under Test (UUT) uut: datapath_averager PORT MAP ( mem_addr => mem_addr, window_val => window_val, overflow => overflow, clk => clk, masterReset => masterReset, input_val => input_val, average_val => average_val ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; --mem_addr <= "000001"; mem_addr <= counter; window_val <= "01"; -- Stimulus process stim_proc: process (clk) begin if (masterReset = '1') then counter <= (others => '0'); elsif (clk'event and clk = '1') then counter <= counter + '1'; end if; end process; process begin wait for clk_period*10; masterReset <= '1'; wait until CLK'event and CLK='1'; masterReset <= '1'; wait for clk_period*3; masterReset <= '0'; wait until CLK'event and CLK='1'; masterReset <= '0'; wait for clk_period*50; end process; END;
use std.textio.all; package read_string is function read_string_time (s : string) return time; end read_string; package body read_string is function read_string_time (s : string) return time is variable l : line := new string'(s); variable t : time; variable read_ok : boolean; begin read(l, t, read_ok); if not read_ok then report "read time failed" severity failure; end if; return t; end function; end package body read_string; use work.read_string.all; entity test_time is generic (test_t : time := read_string_time("123 ps")); end test_time; architecture test of test_time is begin process variable t : time; begin t := read_string_time("321 ps"); report "t=" & time'image(t) severity warning; wait; end process; end test;
use std.textio.all; package read_string is function read_string_time (s : string) return time; end read_string; package body read_string is function read_string_time (s : string) return time is variable l : line := new string'(s); variable t : time; variable read_ok : boolean; begin read(l, t, read_ok); if not read_ok then report "read time failed" severity failure; end if; return t; end function; end package body read_string; use work.read_string.all; entity test_time is generic (test_t : time := read_string_time("123 ps")); end test_time; architecture test of test_time is begin process variable t : time; begin t := read_string_time("321 ps"); report "t=" & time'image(t) severity warning; wait; end process; end test;
use std.textio.all; package read_string is function read_string_time (s : string) return time; end read_string; package body read_string is function read_string_time (s : string) return time is variable l : line := new string'(s); variable t : time; variable read_ok : boolean; begin read(l, t, read_ok); if not read_ok then report "read time failed" severity failure; end if; return t; end function; end package body read_string; use work.read_string.all; entity test_time is generic (test_t : time := read_string_time("123 ps")); end test_time; architecture test of test_time is begin process variable t : time; begin t := read_string_time("321 ps"); report "t=" & time'image(t) severity warning; wait; end process; end test;
------------------------------------------------------------------------------- -- Processor Common Library Package ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: system_xadc_wiz_0_0_proc_common_pkg.vhd -- Version: v1.21b -- Description: This file contains the constants and functions used in the -- processor common library components. -- ------------------------------------------------------------------------------- -- Structure: -- ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 09/12/01 -- Created from opb_arb_pkg.vhd -- -- ALS 09/21/01 -- ^^^^^^ -- Added pwr function. Replaced log2 function with one that works for XST. -- ~~~~~~ -- -- ALS 12/07/01 -- ^^^^^^ -- Added Addr_bits function. -- ~~~~~~ -- ALS 01/31/02 -- ^^^^^^ -- Added max2 function. -- ~~~~~~ -- FLO 02/22/02 -- ^^^^^^ -- Extended input argument range of log2 function to 2^30. Also, added -- a check that the argument does not exceed this value; a failure -- assertion violation is generated if it does not. -- ~~~~~~ -- FLO 08/31/06 -- ^^^^^^ -- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and -- Get_RLOC_Name. These objects are not used. Further, the functions -- produced misleading warnings (CR419886, CR419898). -- ~~~~~~ -- FLO 05/25/07 -- ^^^^^^ -- -Reimplemented function pad_power2 to correct error when the input -- argument is 1. (fixes CR 303469) -- -Added function clog2(x), which returns the integer ceiling of the -- base 2 logarithm of x. This function can be used in place of log2 -- when wishing to avoid the XST warning, "VHDL Assertion Statement -- with non constant condition is ignored". -- ~~~~~~ -- -- DET 1/17/2008 v3_30_a -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- -- DET 5/8/2009 v3_30_a for EDK L.SP2 -- ~~~~~~ -- - Per CR520627 -- - Added synthesis translate_off/on constructs to the log2 function -- around the assertion statement. This removes a repetative XST Warning -- in SRP files about a non-constant assertion check. -- ^^^^^^ -- FL0 20/27/2010 -- ^^^^^^ -- Removed 42 TBD comment, again. (CR 568493) -- ~~~~~~ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- need conversion function to convert reals/integers to std logic vectors use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package system_xadc_wiz_0_0_proc_common_pkg is ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type CHAR_TO_INT_TYPE is array (character) of integer; -- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; -- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63); ------------------------------------------------------------------------------- -- Function and Procedure Declarations ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer; function min2 (num1, num2 : integer) return integer; function Addr_Bits(x,y : std_logic_vector) return integer; function clog2(x : positive) return natural; function pad_power2 ( in_num : integer ) return integer; function pad_4 ( in_num : integer ) return integer; function log2(x : natural) return integer; function pwr(x: integer; y: integer) return integer; function String_To_Int(S : string) return integer; function itoa (int : integer) return string; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- the RESET_ACTIVE constant should denote the logic level of an active reset constant RESET_ACTIVE : std_logic := '1'; -- table containing strings representing hex characters for conversion to -- integers constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE := ('0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 'A'|'a' => 10, 'B'|'b' => 11, 'C'|'c' => 12, 'D'|'d' => 13, 'E'|'e' => 14, 'F'|'f' => 15, others => -1); end system_xadc_wiz_0_0_proc_common_pkg; package body system_xadc_wiz_0_0_proc_common_pkg is ------------------------------------------------------------------------------- -- Function Definitions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Function max2 -- -- This function returns the greater of two numbers. ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer is begin if num1 >= num2 then return num1; else return num2; end if; end function max2; ------------------------------------------------------------------------------- -- Function min2 -- -- This function returns the lesser of two numbers. ------------------------------------------------------------------------------- function min2 (num1, num2 : integer) return integer is begin if num1 <= num2 then return num1; else return num2; end if; end function min2; ------------------------------------------------------------------------------- -- Function Addr_bits -- -- function to convert an address range (base address and an upper address) -- into the number of upper address bits needed for decoding a device -- select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits(x,y : std_logic_vector) return integer is variable addr_xor : std_logic_vector(x'range); variable count : integer := 0; begin assert x'length = y'length and (x'ascending xnor y'ascending) report "Addr_Bits: arguments are not the same type" severity ERROR; addr_xor := x xor y; for i in x'range loop if addr_xor(i) = '1' then return count; end if; count := count + 1; end loop; return x'length; end Addr_Bits; -------------------------------------------------------------------------------- -- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, -- i.e., the least integer greater than or equal to log2(x). -------------------------------------------------------------------------------- function clog2(x : positive) return natural is variable r : natural := 0; variable rp : natural := 1; -- rp tracks the value 2**r begin while rp < x loop -- Termination condition T: x <= 2**r -- Loop invariant L: 2**(r-1) < x r := r + 1; if rp > integer'high - rp then exit; end if; -- If doubling rp overflows -- the integer range, the doubled value would exceed x, so safe to exit. rp := rp + rp; end loop; -- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r return r; -- end clog2; ------------------------------------------------------------------------------- -- Function pad_power2 -- -- This function returns the next power of 2 from the input number. If the -- input number is a power of 2, this function returns the input number. -- -- This function is used to round up the number of masters to the next power -- of 2 if the number of masters is not already a power of 2. -- -- Input argument 0, which is not a power of two, is accepted and returns 0. -- Input arguments less than 0 are not allowed. ------------------------------------------------------------------------------- -- function pad_power2 (in_num : integer ) return integer is begin if in_num = 0 then return 0; else return 2**(clog2(in_num)); end if; end pad_power2; ------------------------------------------------------------------------------- -- Function pad_4 -- -- This function returns the next multiple of 4 from the input number. If the -- input number is a multiple of 4, this function returns the input number. -- ------------------------------------------------------------------------------- -- function pad_4 (in_num : integer ) return integer is variable out_num : integer; begin out_num := (((in_num-1)/4) + 1)*4; return out_num; end pad_4; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- -- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------------------- -- Function pwr -- x**y -- negative numbers not allowed for y ------------------------------------------------------------------------------- function pwr(x: integer; y: integer) return integer is variable z : integer := 1; begin if y = 0 then return 1; else for i in 1 to y loop z := z * x; end loop; return z; end if; end function pwr; ------------------------------------------------------------------------------- -- Function itoa -- -- The itoa function converts an integer to a text string. -- This function is required since `image doesn't work in Synplicity -- Valid input range is -9999 to 9999 ------------------------------------------------------------------------------- -- function itoa (int : integer) return string is type table is array (0 to 9) of string (1 to 1); constant LUT : table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9"); variable str1 : string(1 to 1); variable str2 : string(1 to 2); variable str3 : string(1 to 3); variable str4 : string(1 to 4); variable str5 : string(1 to 5); variable abs_int : natural; variable thousands_place : natural; variable hundreds_place : natural; variable tens_place : natural; variable ones_place : natural; variable sign : integer; begin abs_int := abs(int); if abs_int > int then sign := -1; else sign := 1; end if; thousands_place := abs_int/1000; hundreds_place := (abs_int-thousands_place*1000)/100; tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10; ones_place := (abs_int-thousands_place*1000-hundreds_place*100-tens_place*10); if sign>0 then if thousands_place>0 then str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif hundreds_place>0 then str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str3; elsif tens_place>0 then str2 := LUT(tens_place) & LUT(ones_place); return str2; else str1 := LUT(ones_place); return str1; end if; else if thousands_place>0 then str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str5; elsif hundreds_place>0 then str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif tens_place>0 then str3 := "-" & LUT(tens_place) & LUT(ones_place); return str3; else str2 := "-" & LUT(ones_place); return str2; end if; end if; end itoa; ----------------------------------------------------------------------------- -- Function String_To_Int -- -- Converts a string of hex character to an integer -- accept negative numbers ----------------------------------------------------------------------------- function String_To_Int(S : String) return Integer is variable Result : integer := 0; variable Temp : integer := S'Left; variable Negative : integer := 1; begin for I in S'Left to S'Right loop if (S(I) = '-') then Temp := 0; Negative := -1; else Temp := STRHEX_TO_INT_TABLE(S(I)); if (Temp = -1) then assert false report "Wrong value in String_To_Int conversion " & S(I) severity error; end if; end if; Result := Result * 16 + Temp; end loop; return (Negative * Result); end String_To_Int; end package body system_xadc_wiz_0_0_proc_common_pkg;
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 --Date : Thu Mar 10 14:13:03 2016 --Host : minmi running 64-bit elementary OS Freya --Command : generate_target system.bd --Design : system --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=1,synth_mode=Global}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of system : entity is "system.hwdef"; end system; architecture STRUCTURE of system is component system_processing_system7_0_0 is port ( SDIO0_WP : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component system_processing_system7_0_0; component system_zybo_hdmi_0_0 is port ( clk_125 : in STD_LOGIC; clk_25 : in STD_LOGIC; hsync : in STD_LOGIC; vsync : in STD_LOGIC; active : in STD_LOGIC; rgb : in STD_LOGIC_VECTOR ( 23 downto 0 ); tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ); hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC ); end component system_zybo_hdmi_0_0; component system_clk_wiz_0_0 is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); end component system_clk_wiz_0_0; component system_vga_sync_0_0 is port ( clk_25 : in STD_LOGIC; rst : in STD_LOGIC; active : out STD_LOGIC; hsync : out STD_LOGIC; vsync : out STD_LOGIC; xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); end component system_vga_sync_0_0; component system_vga_color_test_0_0 is port ( clk_25 : in STD_LOGIC; xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); rgb : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); end component system_vga_color_test_0_0; component system_inverter_0_0 is port ( x : in STD_LOGIC; x_not : out STD_LOGIC ); end component system_inverter_0_0; signal Net : STD_LOGIC; signal hdmi_cec_1 : STD_LOGIC; signal hdmi_hpd_1 : STD_LOGIC; signal inverter_0_x_not : STD_LOGIC; signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; signal processing_system7_0_DDR_CKE : STD_LOGIC; signal processing_system7_0_DDR_CK_N : STD_LOGIC; signal processing_system7_0_DDR_CK_P : STD_LOGIC; signal processing_system7_0_DDR_CS_N : STD_LOGIC; signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ODT : STD_LOGIC; signal processing_system7_0_DDR_RAS_N : STD_LOGIC; signal processing_system7_0_DDR_RESET_N : STD_LOGIC; signal processing_system7_0_DDR_WE_N : STD_LOGIC; signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 ); signal vga_sync_0_active : STD_LOGIC; signal vga_sync_0_hsync : STD_LOGIC; signal vga_sync_0_vsync : STD_LOGIC; signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 ); signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC; signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 ); signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); begin hdmi_cec_1 <= hdmi_cec; hdmi_hpd_1 <= hdmi_hpd; hdmi_out_en <= zybo_hdmi_0_hdmi_out_en; tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0); tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0); clk_wiz_0: component system_clk_wiz_0_0 port map ( clk_in1 => processing_system7_0_FCLK_CLK0, clk_out1 => Net, locked => NLW_clk_wiz_0_locked_UNCONNECTED, resetn => processing_system7_0_FCLK_RESET0_N ); inverter_0: component system_inverter_0_0 port map ( x => processing_system7_0_FCLK_RESET0_N, x_not => inverter_0_x_not ); processing_system7_0: component system_processing_system7_0_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, FCLK_CLK0 => processing_system7_0_FCLK_CLK0, FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_ARREADY => '0', M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED, M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_AWREADY => '0', M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED, M_AXI_GP0_BID(11 downto 0) => B"000000000000", M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED, M_AXI_GP0_BRESP(1 downto 0) => B"00", M_AXI_GP0_BVALID => '0', M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP0_RID(11 downto 0) => B"000000000000", M_AXI_GP0_RLAST => '0', M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED, M_AXI_GP0_RRESP(1 downto 0) => B"00", M_AXI_GP0_RVALID => '0', M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0), M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED, M_AXI_GP0_WREADY => '0', M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, SDIO0_WP => '0', TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED ); vga_color_test_0: component system_vga_color_test_0_0 port map ( clk_25 => Net, rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0), xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0), yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0) ); vga_sync_0: component system_vga_sync_0_0 port map ( active => vga_sync_0_active, clk_25 => Net, hsync => vga_sync_0_hsync, rst => inverter_0_x_not, vsync => vga_sync_0_vsync, xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0), yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0) ); zybo_hdmi_0: component system_zybo_hdmi_0_0 port map ( active => vga_sync_0_active, clk_125 => processing_system7_0_FCLK_CLK0, clk_25 => Net, hdmi_cec => hdmi_cec_1, hdmi_hpd => hdmi_hpd_1, hdmi_out_en => zybo_hdmi_0_hdmi_out_en, hsync => vga_sync_0_hsync, rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0), tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0), tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0), vsync => vga_sync_0_vsync ); end STRUCTURE;
-------------------------------------------------------------------------------- -- FILE: AdderSumGenerator -- DESC: The sum generator part of a Adder, typically used in P4 Adder -- -- Author: -- Create: 2015-05-27 -- Update: 2015-05-27 -- Status: TESTED -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.Consts.all; -------------------------------------------------------------------------------- -- ENTITY -------------------------------------------------------------------------------- entity AdderSumGenerator is generic ( DATA_SIZE : integer := C_SYS_DATA_SIZE; SPARSITY : integer := C_ADD_SPARSITY ); port ( a, b: in std_logic_vector(DATA_SIZE-1 downto 0); cin: in std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0); sum: out std_logic_vector(DATA_SIZE-1 downto 0) ); end AdderSumGenerator; -------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------- architecture adder_sum_generator_arch of AdderSumGenerator is component AdderCarrySelect is generic( DATA_SIZE : integer := C_SYS_DATA_SIZE ); port( a, b: in std_logic_vector(DATA_SIZE-1 downto 0); sel: in std_logic; sum: out std_logic_vector(DATA_SIZE-1 downto 0) ); end component; begin GE0: for i in 0 to DATA_SIZE/SPARSITY-1 generate begin ACSi: AdderCarrySelect generic map(SPARSITY) port map(a((i+1)*SPARSITY-1 downto i*SPARSITY), b((i+1)*SPARSITY-1 downto i*SPARSITY), cin(i), sum((i+1)*SPARSITY-1 downto i*SPARSITY)); end generate; end adder_sum_generator_arch;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jvwqzKBKhrxQWN8hsOjOuhm8qkei5fK+KBFDI6UMQ6LTpmEm6svKSD063x1ZEoldq0EPd/8Fzm27 HyWMasS+AnODAcA+LSU8UJUegB0MUFBnmupwwVd2d0q90AtoPdgKjqQOfz2Yi2tPkdwEy2Kj1O0O mZu+VaX5r1zYYPscnodrP06dvyymGeL2alzplCMWc3Opy24bBeYqwB/f6wTWIGBw2ZgUxQfISBlG kQwLbZjy47lLp53zoxMKWmiQTv8v+ReeLQVEZwdTjKGMpUDoWVNPShmJ1luJ3y7FFCN4dF3KFbos DyO9kgbvdt+2ODqiDQpisUfHRUS1p7a69NANUw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UWt4kN0n3VZaA0HuQJAVduTv5X2Vh2Gb+AMwzaHB0yu2DXN/3Roy/psxwQdGq0zMlk0Ug073bgEn +LdAGpvs9bqccgaVY6CUwl7xLbLwtIeP4PZYKNzOovwIbYjYtj8zx4f63Yc5H9WpZBzBgN4pVq02 /XSCqRxlIgO1OSis1R0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block aEwtqlfh0lP+4CzXQC5dDfGrPxW1RicwHMzG9ss7VdTa5XjjR8ErOJBMKW9N9kCRklx3/ihFp2+H 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jvwqzKBKhrxQWN8hsOjOuhm8qkei5fK+KBFDI6UMQ6LTpmEm6svKSD063x1ZEoldq0EPd/8Fzm27 HyWMasS+AnODAcA+LSU8UJUegB0MUFBnmupwwVd2d0q90AtoPdgKjqQOfz2Yi2tPkdwEy2Kj1O0O mZu+VaX5r1zYYPscnodrP06dvyymGeL2alzplCMWc3Opy24bBeYqwB/f6wTWIGBw2ZgUxQfISBlG kQwLbZjy47lLp53zoxMKWmiQTv8v+ReeLQVEZwdTjKGMpUDoWVNPShmJ1luJ3y7FFCN4dF3KFbos DyO9kgbvdt+2ODqiDQpisUfHRUS1p7a69NANUw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UWt4kN0n3VZaA0HuQJAVduTv5X2Vh2Gb+AMwzaHB0yu2DXN/3Roy/psxwQdGq0zMlk0Ug073bgEn +LdAGpvs9bqccgaVY6CUwl7xLbLwtIeP4PZYKNzOovwIbYjYtj8zx4f63Yc5H9WpZBzBgN4pVq02 /XSCqRxlIgO1OSis1R0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block aEwtqlfh0lP+4CzXQC5dDfGrPxW1RicwHMzG9ss7VdTa5XjjR8ErOJBMKW9N9kCRklx3/ihFp2+H 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jvwqzKBKhrxQWN8hsOjOuhm8qkei5fK+KBFDI6UMQ6LTpmEm6svKSD063x1ZEoldq0EPd/8Fzm27 HyWMasS+AnODAcA+LSU8UJUegB0MUFBnmupwwVd2d0q90AtoPdgKjqQOfz2Yi2tPkdwEy2Kj1O0O mZu+VaX5r1zYYPscnodrP06dvyymGeL2alzplCMWc3Opy24bBeYqwB/f6wTWIGBw2ZgUxQfISBlG kQwLbZjy47lLp53zoxMKWmiQTv8v+ReeLQVEZwdTjKGMpUDoWVNPShmJ1luJ3y7FFCN4dF3KFbos DyO9kgbvdt+2ODqiDQpisUfHRUS1p7a69NANUw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UWt4kN0n3VZaA0HuQJAVduTv5X2Vh2Gb+AMwzaHB0yu2DXN/3Roy/psxwQdGq0zMlk0Ug073bgEn +LdAGpvs9bqccgaVY6CUwl7xLbLwtIeP4PZYKNzOovwIbYjYtj8zx4f63Yc5H9WpZBzBgN4pVq02 /XSCqRxlIgO1OSis1R0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block aEwtqlfh0lP+4CzXQC5dDfGrPxW1RicwHMzG9ss7VdTa5XjjR8ErOJBMKW9N9kCRklx3/ihFp2+H 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jvwqzKBKhrxQWN8hsOjOuhm8qkei5fK+KBFDI6UMQ6LTpmEm6svKSD063x1ZEoldq0EPd/8Fzm27 HyWMasS+AnODAcA+LSU8UJUegB0MUFBnmupwwVd2d0q90AtoPdgKjqQOfz2Yi2tPkdwEy2Kj1O0O mZu+VaX5r1zYYPscnodrP06dvyymGeL2alzplCMWc3Opy24bBeYqwB/f6wTWIGBw2ZgUxQfISBlG kQwLbZjy47lLp53zoxMKWmiQTv8v+ReeLQVEZwdTjKGMpUDoWVNPShmJ1luJ3y7FFCN4dF3KFbos DyO9kgbvdt+2ODqiDQpisUfHRUS1p7a69NANUw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UWt4kN0n3VZaA0HuQJAVduTv5X2Vh2Gb+AMwzaHB0yu2DXN/3Roy/psxwQdGq0zMlk0Ug073bgEn +LdAGpvs9bqccgaVY6CUwl7xLbLwtIeP4PZYKNzOovwIbYjYtj8zx4f63Yc5H9WpZBzBgN4pVq02 /XSCqRxlIgO1OSis1R0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block aEwtqlfh0lP+4CzXQC5dDfGrPxW1RicwHMzG9ss7VdTa5XjjR8ErOJBMKW9N9kCRklx3/ihFp2+H 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AolBytnjEB9vpNrjcwnWPQ8nzJNLl5zUs1zi1ZBzW3yv04oyVuZFFFC6sIXpAimh13IxH6laB+kK b0fu2zHWbg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block S1URi6qiBAwYtGqhuIWcLaBn/++1FNb+yj2QZVxchxmr+DeQ1s17oT1CDAgcbPMuXpUY2YsioKKJ D0vrkzwVR86uTVGGlCD4o1PwFJ9WRGPIo/mTOgh7PnaPHh8Qn7+sl/0aVgcTGp+urmuV7syRLcKU ktLKKwESCE2jztZoi7Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO80x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO80x64WC; ARCHITECTURE DPBSCFIFO80x64WC_arch OF DPBSCFIFO80x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 80, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 80, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO80x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO80x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO80x64WC; ARCHITECTURE DPBSCFIFO80x64WC_arch OF DPBSCFIFO80x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 80, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 80, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO80x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO80x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO80x64WC; ARCHITECTURE DPBSCFIFO80x64WC_arch OF DPBSCFIFO80x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 80, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 80, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO80x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO80x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO80x64WC; ARCHITECTURE DPBSCFIFO80x64WC_arch OF DPBSCFIFO80x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO80x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(79 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(79 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 80, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 80, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO80x64WC_arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1814.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01814ent IS END c07s01b00x00p08n01i01814ent; ARCHITECTURE c07s01b00x00p08n01i01814arch OF c07s01b00x00p08n01i01814ent IS type small_int is range 0 to 7; type byte is range small_int to 3; BEGIN TESTING: PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01814 - Type name are not permitted as primaries in a range expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01814arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1814.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01814ent IS END c07s01b00x00p08n01i01814ent; ARCHITECTURE c07s01b00x00p08n01i01814arch OF c07s01b00x00p08n01i01814ent IS type small_int is range 0 to 7; type byte is range small_int to 3; BEGIN TESTING: PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01814 - Type name are not permitted as primaries in a range expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01814arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1814.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01814ent IS END c07s01b00x00p08n01i01814ent; ARCHITECTURE c07s01b00x00p08n01i01814arch OF c07s01b00x00p08n01i01814ent IS type small_int is range 0 to 7; type byte is range small_int to 3; BEGIN TESTING: PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01814 - Type name are not permitted as primaries in a range expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01814arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc980.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p05n01i00980ent IS END c06s03b00x00p05n01i00980ent; ARCHITECTURE c06s03b00x00p05n01i00980arch OF c06s03b00x00p05n01i00980ent IS BEGIN TESTING: PROCESS type R1 is record RE1: BOOLEAN; end record; type R2 is record RE2: BOOLEAN; end record; function F2 return R2 is begin return (RE2=>TRUE); end F2; variable V1: R1 ; variable V10: BOOLEAN; BEGIN V10 := F2.RE1; -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT; assert FALSE report "***FAILED TEST: c06s03b00x00p05n01i00980 - Illegal record element name." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p05n01i00980arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc980.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p05n01i00980ent IS END c06s03b00x00p05n01i00980ent; ARCHITECTURE c06s03b00x00p05n01i00980arch OF c06s03b00x00p05n01i00980ent IS BEGIN TESTING: PROCESS type R1 is record RE1: BOOLEAN; end record; type R2 is record RE2: BOOLEAN; end record; function F2 return R2 is begin return (RE2=>TRUE); end F2; variable V1: R1 ; variable V10: BOOLEAN; BEGIN V10 := F2.RE1; -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT; assert FALSE report "***FAILED TEST: c06s03b00x00p05n01i00980 - Illegal record element name." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p05n01i00980arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc980.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p05n01i00980ent IS END c06s03b00x00p05n01i00980ent; ARCHITECTURE c06s03b00x00p05n01i00980arch OF c06s03b00x00p05n01i00980ent IS BEGIN TESTING: PROCESS type R1 is record RE1: BOOLEAN; end record; type R2 is record RE2: BOOLEAN; end record; function F2 return R2 is begin return (RE2=>TRUE); end F2; variable V1: R1 ; variable V10: BOOLEAN; BEGIN V10 := F2.RE1; -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT; assert FALSE report "***FAILED TEST: c06s03b00x00p05n01i00980 - Illegal record element name." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p05n01i00980arch;
------------------------------------------------------------------------------- -- Title : DS18b20 Reader ------------------------------------------------------------------------------- -- Author : [email protected] ------------------------------------------------------------------------------- -- Description: Trigger by the "refresh" signal this ip-core requests a -- temperature reading from the connected DS18b20 sensor. -- -- Uses the skip rom command to avoid handling ROM-IDs of sensors. -- Only a single sensor can be used. -- -- DS18b20 Sequence is: -- reset bus -- skip rom (0xcc) -- convert emperature (0x44) -- read bytes - sensor active while 0 are read -- reset bus -- skip rom (0xcc) -- "read scratchpad" (0xbe) -- Rx Temperature LSB -- Rx Temperature MSB -- (drop the rest and idle) -- ------------------------------------------------------------------------------- -- Created : 2014-12-14 ------------------------------------------------------------------------------- -- Copyright (c) 2014, Carl Treudler -- All Rights Reserved. -- -- The file is part for the Loa project and is released under the -- 3-clause BSD license. See the file `LICENSE` for the full license -- governing this code. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.onewire_pkg.all; use work.ds18b20_pkg.all; entity ds18b20 is port ( ow_out : in onewire_out_type; ow_in : out onewire_in_type; ds18b20_in : in ds18b20_in_type; ds18b20_out : out ds18b20_out_type; clk : in std_logic); end ds18b20; architecture behavioural of ds18b20 is type ds18b20_state_type is (idle, reset1, reset2, skip_rom1, skip_rom2, conv_temp1, conv_temp2, wait_for_conversion1, wait_for_conversion2, wait_for_conversion3, reset3, reset4, skip_rom3, skip_rom4, read_sp1, read_sp2, read_sp3, read_sp4, read_sp5, read_sp6); type ds18b20_type is record state : ds18b20_state_type; ow_in : onewire_in_type; ds18b20_out : ds18b20_out_type; byte_cnt : integer range 0 to 3; end record; ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal r, rin : ds18b20_type := (state => IDLE, ow_in => (d => (others => '0'), re => '0', we => '0', reset_bus => '0'), ds18b20_out => (value => (others => '0'), update => '0', err => '0'), byte_cnt => 0); begin -- architecture behavourial ---------------------------------------------------------------------------- -- Connections between ports and signals ---------------------------------------------------------------------------- ds18b20_out <= r.ds18b20_out; ow_in <= r.ow_in; ---------------------------------------------------------------------------- -- Combinatorial part of FSM ---------------------------------------------------------------------------- comb_proc : process(ds18b20_in, ow_out, r) variable v : ds18b20_type; begin v := r; case r.state is when idle => if ds18b20_in.refresh = '1' then v.state := reset1; v.ow_in.reset_bus := '1'; end if; when reset1 => v.ow_in.reset_bus := '0'; v.state := reset2; when reset2 => if ow_out.busy = '0' then v.state := skip_rom1; v.ow_in.d := x"CC"; v.ow_in.we := '1'; end if; when skip_rom1 => v.ow_in.we := '0'; v.state := skip_rom2; when skip_rom2 => if ow_out.busy = '0' then v.state := conv_temp1; v.ow_in.d := x"44"; v.ow_in.we := '1'; end if; when conv_temp1 => v.ow_in.we := '0'; v.state := conv_temp2; when conv_temp2 => if ow_out.busy = '0' then v.state := wait_for_conversion1; end if; when wait_for_conversion1 => v.ow_in.re := '1'; v.state := wait_for_conversion2; when wait_for_conversion2 => v.ow_in.re := '0'; v.state := wait_for_conversion3; when wait_for_conversion3 => if ow_out.busy = '0' then if ow_out.d = x"ff" then v.state := reset3; v.ow_in.reset_bus := '1'; else v.state := wait_for_conversion1; end if; end if; when reset3 => v.ow_in.reset_bus := '0'; v.state := reset4; when reset4 => if ow_out.busy = '0' then v.state := skip_rom3; v.ow_in.d := x"CC"; v.ow_in.we := '1'; end if; when skip_rom3 => v.ow_in.we := '0'; v.state := skip_rom4; when skip_rom4 => if ow_out.busy = '0' then v.state := read_sp1; end if; when read_sp1 => v.ow_in.d := x"be"; v.ow_in.we := '1'; v.byte_cnt := 0; v.state := read_sp2; when read_sp2 => v.ow_in.we := '0'; v.state := read_sp3; when read_sp3 => if ow_out.busy = '0' then v.state := read_sp4; end if; when read_sp4 => v.ow_in.re := '1'; v.state := read_sp5; when read_sp5 => v.ow_in.re := '0'; v.state := read_sp6; when read_sp6 => if ow_out.busy = '0' then if v.byte_cnt = 0 then v.ds18b20_out.value(7 downto 0) := ow_out.d; v.byte_cnt := v.byte_cnt + 1; v.state := read_sp4; elsif v.byte_cnt = 1 then v.ds18b20_out.value(15 downto 8) := ow_out.d; v.state := idle; end if; end if; when others => v.state := IDLE; end case; rin <= v; end process comb_proc; ---------------------------------------------------------------------------- -- Sequential part of finite state machine (FSM) ---------------------------------------------------------------------------- seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- -- None. end behavioural;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --============================================================================-- -- Design unit : DMA2AHB (Entity & architecture declarations) -- -- File name : dma2ahb.vhd -- -- Purpose : AMBA AHB master interface with DMA input -- -- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A, -- 13th May 1999, issue A, first release, ARM Limited -- The document can be retrieved from http://www.arm.com -- AMBA is a trademark of ARM Limited. -- ARM is a registered trademark of ARM Limited. -- -- Note : Naming convention according to AMBA(TM) Specification: -- Signal names are in upper case, except for the following: -- A lower case 'n' in the name indicates that the signal -- is active low. -- Constant names are in upper case. -- The least significant bit of an array is located to the right, -- carrying the index number zero. -- -- Limitations : The AMBA AHB interface has been reduced in function to support -- only what is required. The following features are constrained: -- Optionally generates HSIZE=BYTE, HWORD and WORD -- Only generates HPROT="0011" -- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR -- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16 -- -- Generates the following on reponses on DMA interface: -- HRESP=HRESP_OKAY => DMAOut.Ready -- HRESP=HRESP_ERROR => DMAOut.Fault -- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used) -- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used) -- -- Assumes pipelined data input (after OKAY asserted). -- -- Only big-endianness is supported. -- -- Supports Early Bus Termination with automatic restart. -- Supports Retry/Split with automatic restart. -- -- Library : gaisler -- -- Authors : Aeroflex Gaisler AB -- -- Contact : mailto:[email protected] -- http://www.gaisler.com -- -- Disclaimer : All information is provided "as is", there is no warranty that -- the information is correct or suitable for any purpose, -- neither implicit nor explicit. -- -------------------------------------------------------------------------------- -- Version Author Date Changes -- -- 0.1 SH 1 Jul 2003 New version -- 0.2 SH 21 Jul 2003 Combinatorial response introduced -- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced -- (early burst termination) -- Optimised coding -- Idle transfer initiated in 1st error phase -- 1.3 SH 1 Oct 2004 Ported to GRLIB -- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts -- Support for record types -- 1.5 SH 1 Sep 2005 New library gaisler -- 1.6 SH 20 Sep 2005 Added transparent HSIZE support -- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high -- 1.8 SH 10 Nov 2005 Re-ported to GRLIB -- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle -- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination -- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal -- 1.9.3 SH 24 Feb 2006 Added syncrst generic -- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address -- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged) -- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts -- 1.9.7 MI 4 Aug 2008 Support for Lock -- 1.9.8 SH 16 Apr 2009 Address recovery after SPLIT/RETRY moved -- 1.9.9 SH 9 Oct 2009 HPROT defult to 0x3 -- 2.0 SH 4 Mar 2011 DMAOut.Grant masked while ReAddrPhase set -------------------------------------------------------------------------------- library IEEE; use IEEE.Std_Logic_1164.all; library GRLIB; use GRLIB.AMBA.all; use GRLIB.STDLIB.all; use GRLIB.DMA2AHB_Package.all; entity DMA2AHB is generic( hindex: in Integer := 0; vendorid: in Integer := 0; deviceid: in Integer := 0; version: in Integer := 0; syncrst: in Integer := 1; boundary: in Integer := 1); port( -- AMBA AHB system signals HCLK: in Std_ULogic; -- system clock HRESETn: in Std_ULogic; -- asynchronous reset -- Direct Memory Access Interface DMAIn: in DMA_In_Type; DMAOut: out DMA_OUt_Type; -- AMBA AHB Master Interface AHBIn: in AHB_Mst_In_Type; AHBOut: out AHB_Mst_Out_Type); end entity DMA2AHB; --============================== Architecture ================================-- architecture RTL of DMA2AHB is --=========================================================================-- -- Configuration GRLIB ----------------------------------------------------------------------------- constant HConfig: AHB_Config_Type := ( 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), others => (others => '0')); --=========================================================================-- ----------------------------------------------------------------------------- -- Local signals ----------------------------------------------------------------------------- signal Address: Std_Logic_Vector(31 downto 0); signal AddressSave: Std_Logic_Vector(31 downto 0); signal ActivePhase: Std_ULogic; -- ongoing access signal AddressPhase: Std_ULogic; -- address phase signal DataPhase: Std_ULogic; -- data phase signal ReDataPhase: Std_ULogic; -- restart first signal ReAddrPhase: Std_ULogic; -- restart second signal IdlePhase: Std_ULogic; -- idle phase signal EarlyPhase: Std_ULogic; -- early termination signal BoundaryPhase: Std_ULogic; -- boundary crossing signal SingleAcc: Std_ULogic; -- single access signal WriteAcc: Std_ULogic; -- write access signal DelDataPhase: Std_ULogic; -- restart first signal DelAddrPhase: Std_ULogic; -- restart second signal AHBInHGRANTx: Std_ULogic; -- decoded grant begin --=========================================================================-- -- AMBA AHB master interface ----------------------------------------------------------------------------- AHBOut.HIRQ <= (others => '0'); AHBOut.HCONFIG <= HConfig; AHBOut.HINDEX <= hindex; AHBInHGRANTx <= AHBIn.HGRANT(hindex); --=========================================================================-- ----------------------------------------------------------------------------- -- AMBA AHB Master interface with fast issuing of accesses ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Fixed AMBA AHB signals ----------------------------------------------------------------------------- AHBOut.HPROT <= "0011"; ----------------------------------------------------------------------------- -- Combinatorial paths ----------------------------------------------------------------------------- AHBOut.HADDR <= Address; -- internal to external AHBOut.HWDATA <= ahbdrivedata(DMAIn.Data); -- combinatorial path DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and DataPhase ='1' and AHBIN.HRESP=HRESP_OKAY else '0'; DMAOut.Retry <= '1' when AHBIn.HREADY='0' and DataPhase ='1' and (AHBIN.HRESP=HRESP_RETRY or AHBIN.HRESP=HRESP_SPLIT) else '0'; DMAOut.Fault <= '1' when AHBIn.HREADY='0' and DataPhase ='1' and AHBIN.HRESP=HRESP_ERROR else '0'; DMAOut.Grant <= '0' when ReDataPhase='1' or ReAddrPhase='1' else '1' when AHBIn.HREADY='1' and AHBInHGRANTx='1' and DMAIn.Request='1' else '0'; AHBOut.HBUSREQ <= '0' when IdlePhase='1' else '1' when DMAIn.Request='1' else '1' when DMAIn.Burst='1' else '1' when ReDataPhase='1' else '1' when ReAddrPhase='1' else '0'; AHBOut.HLOCK <= '0' when IdlePhase='1' else '1' when (DMAIn.Lock and (DMAIn.Request or ReDataPhase)) = '1'else '0'; ----------------------------------------------------------------------------- -- The AMBA AHB interfacing is done in this process ----------------------------------------------------------------------------- AHBMaster: process(HCLK, HRESETn) variable BoundaryCrossing: Std_ULogic; variable AddressInc: Std_Logic_Vector(3 downto 0); -------------------------------------------------------------------------- -- This procedure is used to define all reset values for the -- asynchronous or synchronous reset statements in this process. This -- is done to avoid source code duplication. -------------------------------------------------------------------------- procedure Reset is begin ActivePhase <= '0'; EarlyPhase <= '0'; AddressPhase <= '0'; DataPhase <= '0'; ReDataPhase <= '0'; ReAddrPhase <= '0'; DelDataPhase <= '0'; DelAddrPhase <= '0'; BoundaryPhase <= '0'; IdlePhase <= '0'; EarlyPhase <= '0'; SingleAcc <= '0'; WriteAcc <= '0'; Address <= (others => '0'); AddressSave <= (others => '0'); DMAOut.Ready <= '0'; DMAOut.Data <= (others => '0'); AHBOut.HSIZE <= HSIZE_BYTE; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HTRANS <= HTRANS_IDLE; AHBOut.HWRITE <= '0'; end Reset; --------------------------------------------------------------- begin if HRESETn='0' and syncrst=0 then -- asynchronous reset Reset; elsif Rising_Edge(HCLK) then if DMAIn.Reset='1' or -- functional reset (syncrst/=0 and HRESETn='0') then -- synchronous reset Reset; else -- no reset -------------------------------------------------------------------- -- Temporary variables -------------------------------------------------------------------- BoundaryCrossing := '0'; AddressInc := (others => '0'); -------------------------------------------------------------------- -- AMBA AHB interface - data phase handling -------------------------------------------------------------------- -- indicate when no more activies are pending if AddressPhase='0' and DataPhase='0' and ReDataPhase='0' and ReAddrPhase='0' and DMAIn.Burst='0' then ActivePhase <= '0'; end if; if AHBIn.HREADY='0' and DataPhase='1' then -- error check if AHBIN.HRESP=HRESP_ERROR then DataPhase <= '0'; -- data phase aborted end if; -- split or retry check if AHBIN.HRESP=HRESP_SPLIT or AHBIN.HRESP=HRESP_RETRY then ReDataPhase <= DataPhase; -- restart phases ReAddrPhase <= AddressPhase or ReAddrPhase; AddressPhase <= '0'; -- addr phase aborted DataPhase <= '0'; -- data phase aborted end if; end if; if AHBIn.HREADY='1' and DataPhase='1' then -- sample AHB input data at end of data phase DMAOut.Data <= ahbreadword(AHBIn.HRDATA); DataPhase <= '0'; -- data phase ends DMAOut.Ready <= '1'; else -- remove acknowledgement after one cycle DMAOut.Ready <= '0'; end if; -------------------------------------------------------------------- -- AMBA AHB interface - address phase handling -------------------------------------------------------------------- -- initialize data phase on AHB after previous address phase if AddressPhase='1' and AHBIn.HREADY='1' then DataPhase <= '1'; -- data phase start end if; -- address generation on AHB if AHBIn.HREADY='1' then if AddressPhase='1' then -- burst continuation, sequential transfer AddressInc(conv_integer(DMAIn.Size)) := '1'; if boundary=1 then -- automatic boundary Address <= Address + AddressInc; AddressSave <= Address; if Address(9 downto 2)="11111111" then BoundaryCrossing := '1'; BoundaryPhase <= '1'; end if; else Address(31 downto 10) <= DMAIn.Address(31 downto 10); Address( 9 downto 0) <= Address(9 downto 0) + AddressInc; AddressSave(9 downto 0) <= Address(9 downto 0); end if; if DMAIn.Size=HSIZE8 then AHBOut.HSIZE <= HSIZE_BYTE; elsif DMAIn.Size=HSIZE16 then AHBOut.HSIZE <= HSIZE_HWORD; else AHBOut.HSIZE <= HSIZE_WORD; end if; elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then -- start of burst, non-sequential transfer -- start of single, non-sequential transfer if boundary=1 then -- automatic boundary Address <= DMAIn.Address; AddressSave <= DMAIn.Address; BoundaryCrossing := '0'; BoundaryPhase <= '0'; else Address <= DMAIn.Address; AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0); end if; if DMAIn.Size=HSIZE8 then AHBOut.HSIZE <= HSIZE_BYTE; elsif DMAIn.Size=HSIZE16 then AHBOut.HSIZE <= HSIZE_HWORD; else AHBOut.HSIZE <= HSIZE_WORD; end if; end if; end if; -- address generation on AHB if AHBIn.HREADY='1' then IdlePhase <= '0'; -- one clock cycle only end if; -- initialize address phase on AHB if AHBIn.HREADY='1' then -- granted the AHB bus if AHBInHGRANTx='1' then if ReDataPhase='1' then ReDataPhase <= '0'; AddressPhase <= '1'; -- address phase start EarlyPhase <= '0'; AHBOut.HTRANS <= HTRANS_NONSEQ; if SingleAcc='1' then AHBOut.HBURST <= HBURST_SINGLE; else AHBOut.HBURST <= HBURST_INCR; end if; AHBOut.HWRITE <= WriteAcc; -- go back with address if boundary=1 then Address <= AddressSave; else Address(9 downto 0) <= AddressSave(9 downto 0); end if; elsif ReAddrPhase='1' then AddressPhase <= '1'; -- address phase start ReAddrPhase <= '0'; if AddressPhase='1' then if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then -- new bursts, non-sequential transfer AHBOut.HTRANS <= HTRANS_NONSEQ; BoundaryPhase <= '0'; else -- burst continuation, sequential transfer AHBOut.HTRANS <= HTRANS_SEQ; end if; else AHBOut.HTRANS <= HTRANS_NONSEQ; end if; EarlyPhase <= '0'; if SingleAcc='1' then AHBOut.HBURST <= HBURST_SINGLE; else AHBOut.HBURST <= HBURST_INCR; end if; AHBOut.HWRITE <= WriteAcc; elsif EarlyPhase='1' then -- early terminated burst resumed AddressPhase <= '1'; -- address phase start EarlyPhase <= '0'; AHBOut.HTRANS <= HTRANS_NONSEQ; AHBOut.HBURST <= HBURST_INCR; AHBOut.HWRITE <= WriteAcc; elsif DMAIn.Request='1' and DMAIn.Burst='1' then AddressPhase <= '1'; -- address phase start if ActivePhase='1' then -- burst continuation, sequential transfer if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then -- new bursts, non-sequential transfer AHBOut.HTRANS <= HTRANS_NONSEQ; BoundaryPhase <= '0'; else -- burst continuation, sequential transfer AHBOut.HTRANS <= HTRANS_SEQ; end if; else -- start of burst, non-sequential transfer AHBOut.HTRANS <= HTRANS_NONSEQ; if DMAIn.Beat ="00" then AHBOut.HBURST <= HBURST_INCR; elsif DMAIn.Beat ="01" then AHBOut.HBURST <= HBURST_INCR4; elsif DMAIn.Beat ="10" then AHBOut.HBURST <= HBURST_INCR8; else AHBOut.HBURST <= HBURST_INCR16; end if; AHBOut.HWRITE <= DMAIn.Store; ActivePhase <= '1'; SingleAcc <= '0'; WriteAcc <= DMAIn.Store; end if; elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then -- burst in wait state AddressPhase <= '0'; -- no address phase AHBOut.HTRANS <= HTRANS_BUSY; elsif DMAIn.Request='1' and DMAIn.Burst='0' then -- start of single, non-sequential transfer AddressPhase <= '1'; -- address phase start ActivePhase <= '1'; SingleAcc <= '1'; WriteAcc <= DMAIn.Store; AHBOut.HTRANS <= HTRANS_NONSEQ; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HWRITE <= DMAIn.Store; else -- drive idle transfer as default master -- the next cycle will start the address phase AddressPhase <= '0'; -- no useful address AHBOut.HTRANS <= HTRANS_IDLE; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HWRITE <= '0'; end if; -- not granted the AHB bus, but early burst termination elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then -- must restart a burst transfer since grant removed AddressPhase <= '0'; -- no address phase EarlyPhase <= '1'; AHBOut.HTRANS <= HTRANS_IDLE; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HWRITE <= '0'; -- not granted the AHB bus else -- drive idle transfer as default master -- the next cycle will start the address phase AddressPhase <= '0'; -- no useful address AHBOut.HTRANS <= HTRANS_IDLE; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HWRITE <= '0'; end if; elsif AHBIn.HREADY='0' and DataPhase='1' then if AHBIN.HRESP=HRESP_ERROR or AHBIN.HRESP=HRESP_SPLIT or AHBIN.HRESP=HRESP_RETRY then -- drive idle transfer due to error, retry or split -- the next cycle will start the address phase AddressPhase <= '0'; -- no useful address IdlePhase <= '1'; AHBOut.HTRANS <= HTRANS_IDLE; AHBOut.HBURST <= HBURST_SINGLE; AHBOut.HWRITE <= '0'; end if; end if; end if; if AHBIn.HREADY='1' then -- delay one phase DelDataPhase <= ReDataPhase; DelAddrPhase <= ReAddrPhase; end if; -- temporary variables cleared BoundaryCrossing := '0'; AddressInc := (others => '0'); else null; end if; end process AHBMaster; end architecture RTL; --======================================================--
-- $Id: pdp11.vhd 1321 2022-11-24 15:06:47Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Package Name: pdp11 -- Description: Definitions for pdp11 components -- -- Dependencies: - -- Tool versions: ise 8.2-14.7; viv 2016.2-2022.1; ghdl 0.18-2.0.0 -- -- Revision History: -- Date Rev Version Comment -- 2022-11-24 1321 1.5.17 add cpustat_type intpend -- 2022-11-21 1320 1.6.16 rename some rsv->ser and cpustat_type trap_->treq_; -- remove vm_cntl_type.trap_done; add in_vecysv; -- 2022-10-25 1309 1.6.15 rename _gpr -> _gr -- 2022-10-03 1301 1.6.14 add decode_stat_type.is_dstpcmode1 -- 2022-08-13 1279 1.6.13 ssr->mmr rename -- 2019-06-02 1159 1.6.12 add rbaddr_ constants -- 2019-03-01 1116 1.6.11 define c_init_rbf_greset -- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer -- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache -- add DM_STAT_SE.pcload -- 2018-09-29 1051 1.6.8 add pdp11_dmpcnt; add DM_STAT_SE.(cpbusy,idec) -- 2017-04-22 884 1.6.7 dm_stat_se: add idle; pdp11_dmcmon: add SNUM generic -- 2016-12-26 829 1.6.6 BUGFIX: psw init with pri=0, as on real 11/70 -- 2015-11-01 712 1.6.5 define sbcntl_sbf_tmu := 12; use for pdp11_tmu_sb -- 2015-07-19 702 1.6.4 change DM_STAT_(DP|CO); add DM_STAT_SE -- 2015-07-10 700 1.6.3 define c_cpurust_hbpt; -- 2015-07-04 697 1.6.2 add pdp11_dm(hbpt|cmon); change DM_STAT_(SY|VM|CO) -- 2015-06-26 695 1.6.1 add pdp11_dmscnt (add support) -- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70 -- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70 -- 2015-02-20 649 1.5.3 add pdp11_statleds -- 2015-02-08 644 1.5.2 add pdp11_bram_memctl -- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.5 rb_mreq addr now 16 bit -- 2014-08-10: 581 1.4.10 add c_cc_f_* field defs for condition code array -- 2014-07-12 569 1.4.9 dpath_stat_type: merge div_zero+div_ovfl to div_quit -- dpath_cntl_type: add munit_s_div_sr -- 2011-11-18 427 1.4.8 now numeric_std clean -- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib -- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM; -- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names -- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit -- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's -- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type -- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri -- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type; -- reassign cp command codes and rename: c_cp_func_... -- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from -- dpath_cntl_type; add cpdout_we to dpath_cntl_type; -- reassign rbus adresses and rename: c_rb_addr_... -- -> c_rbaddr_...; rename rbus fields: c_rb_statf_... -- -> c_stat_rbf_... -- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type -- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ -- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT -- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp; -- rename c_rp_addr_* -> c_rb_addr_* -- 2010-03-21 270 1.2.6 add pdp11_du_drv -- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented) -- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb -- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0' -- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP -- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; -- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes; -- move (and rename) intbus defs to iblib package; -- move intbus devices to ibdlib package; -- rename ubf_ --> ibf_; -- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11 -- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust -- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat -- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq -- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports -- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET -- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type -- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type. -- _vmbox,_mmu interface changed -- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram -- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70 -- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses) -- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector -- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri -- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11) -- mod pdp11_intmap; -- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr -- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) -- add ibdr_kw11l. -- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type -- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01] -- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port -- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri -- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's -- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands -- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core -- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o) -- 2007-06-14 56 1.0.1 Use slvtypes.all -- 2007-05-12 26 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; use work.rblib.all; package pdp11 is -- default rbus base addresses and offsets constant rbaddr_cpu0_core : slv16 := x"0000"; -- cpu0 core base constant rbaddr_cpu0_ibus : slv16 := x"4000"; -- cpu0 ibus window base constant rbaddr_dmscnt_off : slv16 := x"0040"; -- dmscnt offset constant rbaddr_dmcmon_off : slv16 := x"0048"; -- dmcmon offset constant rbaddr_dmhbpt_off : slv16 := x"0050"; -- dmhbpt offset constant rbaddr_dmpcnt_off : slv16 := x"0060"; -- dmpcnt offset type psw_type is record -- processor status cmode : slv2; -- current mode pmode : slv2; -- previous mode rset : slbit; -- register set pri : slv3; -- processor priority tflag : slbit; -- trace flag cc : slv4; -- condition codes (NZVC). end record psw_type; constant c_cc_f_n: integer := 3; -- condition code: n constant c_cc_f_z: integer := 2; -- condition code: z constant c_cc_f_v: integer := 1; -- condition code: v constant c_cc_f_c: integer := 0; -- condition code: c constant psw_init : psw_type := ( "00","00", -- cmode, pmode (=kernel) '0',"000",'0', -- rset, pri (=0), tflag "0000" -- cc NZVC=0 ); constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor constant c_psw_umode : slv2 := "11"; -- processor mode: user subtype psw_ibf_cmode is integer range 15 downto 14; subtype psw_ibf_pmode is integer range 13 downto 12; constant psw_ibf_rset: integer := 11; subtype psw_ibf_pri is integer range 7 downto 5; constant psw_ibf_tflag: integer := 4; subtype psw_ibf_cc is integer range 3 downto 0; type parpdr_type is record -- combined PAR/PDR MMU status paf : slv16; -- page address field plf : slv7; -- page length field ed : slbit; -- expansion direction acf : slv3; -- access control field end record parpdr_type; constant parpdr_init : parpdr_type := ( (others=>'0'), -- paf "0000000",'0',"000" -- plf, ed, acf ); type dpath_cntl_type is record -- data path control gr_asrc : slv3; -- src register address gr_adst : slv3; -- dst register address gr_mode : slv2; -- psw mode for gr access gr_rset : slbit; -- register set gr_we : slbit; -- gr write enable gr_bytop : slbit; -- gr high byte enable gr_pcinc : slbit; -- pc increment enable psr_ccwe : slbit; -- enable update cc psr_we: slbit; -- write enable psw (from DIN) psr_func : slv3; -- write function psw (from DIN) dsrc_sel : slbit; -- src data register source select dsrc_we : slbit; -- src data register write enable ddst_sel : slbit; -- dst data register source select ddst_we : slbit; -- dst data register write enable dtmp_sel : slv2; -- tmp data register source select dtmp_we : slbit; -- tmp data register write enable ounit_asel : slv2; -- ounit a port selector ounit_azero : slbit; -- ounit a port force zero ounit_const : slv9; -- ounit b port const ounit_bsel : slv2; -- ounit b port selector ounit_opsub : slbit; -- ounit operation aunit_srcmod : slv2; -- aunit src port modifier aunit_dstmod : slv2; -- aunit dst port modifier aunit_cimod : slv2; -- aunit ci port modifier aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction) aunit_ccmode : slv3; -- aunit cc port mode aunit_bytop : slbit; -- aunit byte operation lunit_func : slv4; -- lunit function lunit_bytop : slbit; -- lunit byte operation munit_func : slv2; -- munit function munit_s_div : slbit; -- munit s_opg_div state munit_s_div_cn : slbit; -- munit s_opg_div_cn state munit_s_div_cr : slbit; -- munit s_opg_div_cr state munit_s_div_sr : slbit; -- munit s_opg_div_sr state munit_s_ash : slbit; -- munit s_opg_ash state munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state munit_s_ashc : slbit; -- munit s_opg_ashc state munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state ireg_we : slbit; -- ireg register write enable cres_sel : slv3; -- result bus (cres) select dres_sel : slv3; -- result bus (dres) select vmaddr_sel : slv2; -- virtual address select cpdout_we : slbit; -- capture dres for cpdout end record dpath_cntl_type; constant dpath_cntl_init : dpath_cntl_type := ( "000","000","00",'0','0','0','0', -- gr '0','0',"000", -- psr '0','0','0','0',"00",'0', -- dsrc,..,dtmp "00",'0',"000000000","00",'0', -- ounit "00","00","00",'0',"000",'0', -- aunit "0000",'0', -- lunit "00",'0','0','0','0','0','0','0','0',-- munit '0',"000","000","00",'0' -- rest ); constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC) constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST) constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP type dpath_stat_type is record -- data path status ccout_z : slbit; -- current effective Z cc flag shc_tc : slbit; -- last shc cycle (shc==0) div_cr : slbit; -- division: remainder correction needed div_cq : slbit; -- division: quotient correction needed div_quit : slbit; -- division: abort (0/ or /0 or V=1) end record dpath_stat_type; constant dpath_stat_init : dpath_stat_type := (others=>'0'); type decode_stat_type is record -- decode status is_dstmode0 : slbit; -- dest. is register mode is_srcpc : slbit; -- source is pc is_srcpcmode1 : slbit; -- source is pc and mode=1 is_dstpc : slbit; -- dest. is pc is_dstpcmode1 : slbit; -- dest. is pc and mode=1 is_dstw_reg : slbit; -- dest. register to be written is_dstw_pc : slbit; -- pc register to be written is_rmwop : slbit; -- read-modify-write operation is_bytop : slbit; -- byte operation is_res : slbit; -- reserved operation code op_rtt : slbit; -- RTT instruction op_mov : slbit; -- MOV instruction trap_vec : slv3; -- trap vector addr bits 4:2 force_srcsp : slbit; -- force src register to be sp updt_dstadsrc : slbit; -- update dsrc in dsta flow aunit_srcmod : slv2; -- aunit src port modifier aunit_dstmod : slv2; -- aunit dst port modifier aunit_cimod : slv2; -- aunit ci port modifier aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction) aunit_ccmode : slv3; -- aunit cc port mode lunit_func : slv4; -- lunit function munit_func : slv2; -- munit function res_sel : slv3; -- result bus (cres/dres) select fork_op : slv4; -- op fork after idecode state fork_srcr : slv2; -- src-read fork after idecode state fork_dstr : slv2; -- dst-read fork after src read state fork_dsta : slv2; -- dst-addr fork after idecode state fork_opg : slv4; -- opg fork fork_opa : slv3; -- opa fork do_fork_op : slbit; -- execute fork_op do_fork_srcr : slbit; -- execute fork_srcr do_fork_dstr : slbit; -- execute fork_dstr do_fork_dsta : slbit; -- execute fork_dsta do_fork_opg : slbit; -- execute fork_opg do_pref_dec : slbit; -- can do prefetch at decode phase end record decode_stat_type; constant decode_stat_init : decode_stat_type := ( '0','0','0','0','0','0','0','0','0','0', -- is_ '0','0',"000",'0','0', -- op_, trap_, force_, updt_ "00","00","00",'0',"000", -- aunit_ "0000","00","000", -- lunit_, munit_, res_ "0000","00","00","00","0000","000", -- fork_ '0','0','0','0','0', -- do_fork_ '0' -- do_pref_ ); constant c_fork_op_halt : slv4 := "0000"; constant c_fork_op_wait : slv4 := "0001"; constant c_fork_op_rtti : slv4 := "0010"; constant c_fork_op_trap : slv4 := "0011"; constant c_fork_op_reset: slv4 := "0100"; constant c_fork_op_rts : slv4 := "0101"; constant c_fork_op_spl : slv4 := "0110"; constant c_fork_op_mcc : slv4 := "0111"; constant c_fork_op_br : slv4 := "1000"; constant c_fork_op_mark : slv4 := "1001"; constant c_fork_op_sob : slv4 := "1010"; constant c_fork_op_mtp : slv4 := "1011"; constant c_fork_srcr_def : slv2:= "00"; constant c_fork_srcr_inc : slv2:= "01"; constant c_fork_srcr_dec : slv2:= "10"; constant c_fork_srcr_ind : slv2:= "11"; constant c_fork_dstr_def : slv2:= "00"; constant c_fork_dstr_inc : slv2:= "01"; constant c_fork_dstr_dec : slv2:= "10"; constant c_fork_dstr_ind : slv2:= "11"; constant c_fork_dsta_def : slv2:= "00"; constant c_fork_dsta_inc : slv2:= "01"; constant c_fork_dsta_dec : slv2:= "10"; constant c_fork_dsta_ind : slv2:= "11"; constant c_fork_opg_gen : slv4 := "0000"; constant c_fork_opg_wdef : slv4 := "0001"; constant c_fork_opg_winc : slv4 := "0010"; constant c_fork_opg_wdec : slv4 := "0011"; constant c_fork_opg_wind : slv4 := "0100"; constant c_fork_opg_mul : slv4 := "0101"; constant c_fork_opg_div : slv4 := "0110"; constant c_fork_opg_ash : slv4 := "0111"; constant c_fork_opg_ashc : slv4 := "1000"; constant c_fork_opa_jsr : slv3 := "000"; constant c_fork_opa_jmp : slv3 := "001"; constant c_fork_opa_mtp : slv3 := "010"; constant c_fork_opa_mfp_reg : slv3 := "011"; constant c_fork_opa_mfp_mem : slv3 := "100"; -- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors constant c_cpurust_init : slv4 := "0000"; -- cpu in init state constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended constant c_cpurust_hbpt : slv4 := "0110"; -- cpu had hardware bpt constant c_cpurust_runs : slv4 := "0111"; -- cpu running constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt constant c_cpurust_recser : slv4 := "1001"; -- recursive stack error halt constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure type cpustat_type is record -- CPU status cmdbusy : slbit; -- command busy cmdack : slbit; -- command acknowledge cmderr : slbit; -- command error cmdmerr : slbit; -- command memory access error cpugo : slbit; -- CPU go state cpustep : slbit; -- CPU step flag cpususp : slbit; -- CPU susp flag cpuwait : slbit; -- CPU wait flag cpurust : slv4; -- CPU run status suspint : slbit; -- internal suspend flag suspext : slbit; -- external suspend flag cpfunc : slv5; -- current control port function cprnum : slv3; -- current control port register number waitsusp : slbit; -- WAIT instruction suspended itimer : slbit; -- ITIMER pulse creset : slbit; -- CRESET pulse breset : slbit; -- BRESET pulse intack : slbit; -- INT_ACK pulse intpend : slbit; -- interrupt pending intvect : slv9_2; -- current interrupt vector treq_mmu : slbit; -- mmu trap requested treq_ysv : slbit; -- ysv trap requested prefdone : slbit; -- prefetch done do_grwe : slbit; -- pending gr_we in_vecser : slbit; -- in fatal stack error vector flow in_vecysv : slbit; -- in ysv trap flow end record cpustat_type; constant cpustat_init : cpustat_type := ( '0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr '0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait c_cpurust_init, -- cpurust '0','0', -- suspint,suspext "00000","000", -- cpfunc, cprnum '0', -- waitsusp '0','0','0','0','0', -- itimer,creset,breset,intack,intpend (others=>'0'), -- intvect '0','0','0', -- treq_(mmu|ysv), prefdone '0','0','0' -- do_grwe, in_vec(ser|ysv) ); type cpuerr_type is record -- CPU error register illhlt : slbit; -- illegal halt (in non-kernel mode) adderr : slbit; -- address error (odd, jmp/jsr reg) nxm : slbit; -- non-existent memory iobto : slbit; -- I/O bus timeout (non-exist UB) ysv : slbit; -- yellow stack violation rsv : slbit; -- red stack violation end record cpuerr_type; constant cpuerr_init : cpuerr_type := (others=>'0'); type vm_cntl_type is record -- virt memory control port req : slbit; -- request wacc : slbit; -- write access macc : slbit; -- modify access (r-m-w sequence) cacc : slbit; -- console access bytop : slbit; -- byte operation dspace : slbit; -- dspace operation kstack : slbit; -- access through kernel stack vecser : slbit; -- in fatal stack error vector flow mode : slv2; -- mode end record vm_cntl_type; constant vm_cntl_init : vm_cntl_type := ( '0','0','0','0', -- req, wacc, macc,cacc '0','0','0', -- bytop, dspace, kstack '0',"00" -- vecser, mode ); type vm_stat_type is record -- virt memory status port ack : slbit; -- acknowledge err : slbit; -- error (see err_xxx for reason) fail : slbit; -- failure (machine check) err_odd : slbit; -- abort: odd address error err_mmu : slbit; -- abort: mmu reject err_nxm : slbit; -- abort: non-existing memory err_iobto : slbit; -- abort: non-existing I/O resource err_rsv : slbit; -- abort: red stack violation trap_ysv : slbit; -- trap: yellow stack violation trap_mmu : slbit; -- trap: mmu trap end record vm_stat_type; constant vm_stat_init : vm_stat_type := (others=>'0'); type em_mreq_type is record -- external memory - master request req : slbit; -- request we : slbit; -- write enable be : slv2; -- byte enables cancel : slbit; -- cancel request addr : slv22_1; -- address din : slv16; -- data in (input to memory) end record em_mreq_type; constant em_mreq_init : em_mreq_type := ( '0','0',"00",'0', -- req, we, be, cancel (others=>'0'),(others=>'0') -- addr, din ); type em_sres_type is record -- external memory - slave response ack_r : slbit; -- acknowledge read ack_w : slbit; -- acknowledge write dout : slv16; -- data out (output from memory) end record em_sres_type; constant em_sres_init : em_sres_type := ( '0','0', -- ack_r, ack_w (others=>'0') -- dout ); type mmu_cntl_type is record -- mmu control port req : slbit; -- translate request wacc : slbit; -- write access macc : slbit; -- modify access (r-m-w sequence) cacc : slbit; -- console access (bypass mmu) dspace : slbit; -- dspace access mode : slv2; -- processor mode trap_done : slbit; -- mmu trap taken (set mmr0 bit) end record mmu_cntl_type; constant mmu_cntl_init : mmu_cntl_type := ( '0','0','0','0', -- req, wacc, macc, cacc '0',"00",'0' -- dspace, mode, trap_done ); type mmu_stat_type is record -- mmu status port vaok : slbit; -- virtual address valid trap : slbit; -- mmu trap request ena_mmu : slbit; -- mmu enable (mmr0 bit 0) ena_22bit : slbit; -- mmu in 22 bit mode (mmr3 bit 4) ena_ubmap : slbit; -- ubmap enable (mmr3 bit 5) end record mmu_stat_type; constant mmu_stat_init : mmu_stat_type := (others=>'0'); type mmu_moni_type is record -- mmu monitor port istart : slbit; -- instruction start idone : slbit; -- instruction done pc : slv16; -- PC of new instruction regmod : slbit; -- register modified regnum : slv3; -- register number delta : slv4; -- register offset isdec : slbit; -- offset to be subtracted trace_prev : slbit; -- use mmr12 trace state of prev. state end record mmu_moni_type; constant mmu_moni_init : mmu_moni_type := ( '0','0',(others=>'0'), -- istart, idone, pc '0',"000","0000", -- regmod, regnum, delta '0','0' -- isdec, trace_prev ); type mmu_mmr0_type is record -- MMU mmr0 abo_nonres : slbit; -- abort non resident abo_length : slbit; -- abort page length abo_rdonly : slbit; -- abort read-only trap_mmu : slbit; -- trap management ena_trap : slbit; -- enable traps inst_compl : slbit; -- instruction complete page_mode : slv2; -- page mode dspace : slbit; -- address space (D=1, I=0) page_num : slv3; -- page number ena_mmu : slbit; -- enable memory management trace_prev : slbit; -- mmr12 trace status in prev. state end record mmu_mmr0_type; constant mmu_mmr0_init : mmu_mmr0_type := ( inst_compl=>'0', page_mode=>"00", page_num=>"000", others=>'0' ); type mmu_mmr1_type is record -- MMU mmr1 rb_delta : slv5; -- RB: amount change rb_num : slv3; -- RB: register number ra_delta : slv5; -- RA: amount change ra_num : slv3; -- RA: register number end record mmu_mmr1_type; constant mmu_mmr1_init : mmu_mmr1_type := ( "00000","000", -- rb_... "00000","000" -- ra_... ); type mmu_mmr3_type is record -- MMU mmr3 ena_ubmap : slbit; -- enable unibus mapping ena_22bit : slbit; -- enable 22 bit mapping dspace_km : slbit; -- enable dspace kernel dspace_sm : slbit; -- enable dspace supervisor dspace_um : slbit; -- enable dspace user end record mmu_mmr3_type; constant mmu_mmr3_init : mmu_mmr3_type := (others=>'0'); -- control port definitions -------------------------------------------------- type cp_cntl_type is record -- control port control req : slbit; -- request func : slv5; -- function rnum : slv3; -- register number end record cp_cntl_type; constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000"); type cp_stat_type is record -- control port status cmdbusy : slbit; -- command busy cmdack : slbit; -- command acknowledge cmderr : slbit; -- command error cmdmerr : slbit; -- command memory access error cpugo : slbit; -- CPU go state cpustep : slbit; -- CPU step flag cpuwait : slbit; -- CPU wait flag cpususp : slbit; -- CPU susp flag cpurust : slv4; -- CPU run status suspint : slbit; -- internal suspend suspext : slbit; -- external suspend end record cp_stat_type; constant cp_stat_init : cp_stat_type := ( '0','0','0','0', -- cmd... '0','0','0','0', -- cpu... (others=>'0'), -- cpurust '0','0' -- susp... ); type cp_addr_type is record -- control port address addr : slv22_1; -- address racc : slbit; -- ibus remote access be : slv2; -- byte enables ena_22bit : slbit; -- enable 22 bit mode ena_ubmap : slbit; -- enable unibus mapper end record cp_addr_type; constant cp_addr_init : cp_addr_type := ( (others=>'0'), -- addr '0',"00", -- racc, be '0','0' -- ena_... ); -- debug and monitoring port definitions ------------------------------------- type dm_stat_se_type is record -- debug and monitor status - sequencer idle : slbit; -- sequencer ideling (for pdp11_dcmon) cpbusy : slbit; -- in cp states istart : slbit; -- instruction start idec : slbit; -- instruction decode (for ibd_kw11p) idone : slbit; -- instruction done itimer : slbit; -- instruction timer (for ibdr_rhrp) pcload : slbit; -- PC loaded (flow change) vfetch : slbit; -- vector fetch snum : slv8; -- current state number end record dm_stat_se_type; constant dm_stat_se_init : dm_stat_se_type := ( '0','0', -- idle,cpbusy '0','0','0','0', -- istart,idec,idone,itimer '0','0', -- pcload,vfetch (others=>'0') -- snum ); constant c_snum_f_con: integer := 0; -- control state flag constant c_snum_f_ins: integer := 1; -- instruction state flag constant c_snum_f_vec: integer := 2; -- vector state flag constant c_snum_f_err: integer := 3; -- error state flag constant c_snum_f_vmw: integer := 7; -- vm wait flag type dm_stat_dp_type is record -- debug and monitor status - dpath pc : slv16; -- pc psw : psw_type; -- psw psr_we: slbit; -- psr_we ireg : slv16; -- ireg ireg_we : slbit; -- ireg we dsrc : slv16; -- dsrc register dsrc_we: slbit; -- dsrc we ddst : slv16; -- ddst register ddst_we : slbit; -- ddst we dtmp : slv16; -- dtmp register dtmp_we : slbit; -- dtmp we dres : slv16; -- dres bus cpdout_we : slbit; -- cpdout we gr_adst : slv3; -- gr dst regsiter gr_mode : slv2; -- gr mode gr_bytop : slbit; -- gr bytop gr_we : slbit; -- gr we end record dm_stat_dp_type; constant dm_stat_dp_init : dm_stat_dp_type := ( (others=>'0'), -- pc psw_init,'0', -- psw,psr_we (others=>'0'),'0', -- ireg,ireg_we (others=>'0'),'0', -- dsrc,dsrc_we (others=>'0'),'0', -- ddst,ddst_we (others=>'0'),'0', -- dtmp,dtmp_we (others=>'0'), -- dres '0', -- cpdout_we (others=>'0'),(others=>'0'), -- gr_adst, gr_mode '0','0' -- gr_bytop, gr_we ); type dm_stat_vm_type is record -- debug and monitor status - vmbox vmcntl : vm_cntl_type; -- vmbox: control vmaddr : slv16; -- vmbox: address vmdin : slv16; -- vmbox: data in vmstat : vm_stat_type; -- vmbox: status vmdout : slv16; -- vmbox: data out ibmreq : ib_mreq_type; -- ibus: request ibsres : ib_sres_type; -- ibus: response emmreq : em_mreq_type; -- external memory: request emsres : em_sres_type; -- external memory: response end record dm_stat_vm_type; constant dm_stat_vm_init : dm_stat_vm_type := ( vm_cntl_init, -- vmcntl (others=>'0'), -- vmaddr (others=>'0'), -- vmdin vm_stat_init, -- vmstat (others=>'0'), -- vmdout ib_mreq_init, -- ibmreq ib_sres_init, -- ibsres em_mreq_init, -- emmreq em_sres_init -- emsres ); type dm_stat_co_type is record -- debug and monitor status - core cpugo : slbit; -- cpugo state flag cpustep : slbit; -- cpustep state flag cpususp : slbit; -- cpususp state flag suspint : slbit; -- suspint state flag suspext : slbit; -- suspext state flag end record dm_stat_co_type; constant dm_stat_co_init : dm_stat_co_type := ( '0','0','0', -- cpu... '0','0' -- susp... ); type dm_stat_ca_type is record -- debug and monitor status - cache rd : slbit; -- read request wr : slbit; -- write request rdhit : slbit; -- read hit wrhit : slbit; -- write hit rdmem : slbit; -- read memory wrmem : slbit; -- write memory rdwait : slbit; -- read wait wrwait : slbit; -- write wait end record dm_stat_ca_type; constant dm_stat_ca_init : dm_stat_ca_type := ( '0','0','0','0', -- rd,wr,rdhit,wrhit '0','0','0','0' -- rdmem,wrmem,rdwait,wrwait ); type dm_stat_exp_type is record -- debug and monitor - sys70 export dp_pc : slv16; -- DM_STAT_DP: pc dp_psw : psw_type; -- DM_STAT_DP: psw dp_dsrc : slv16; -- DM_STAT_DP: dsrc register se_idec : slbit; -- DM_STAT_SE: instruction decode se_itimer : slbit; -- DM_STAT_SE: instruction timer end record dm_stat_exp_type; constant dm_stat_exp_init : dm_stat_exp_type := ( (others=>'0'), -- dp_pc psw_init, -- dp_psw (others=>'0'), -- dp_dsrc '0','0' -- se_idec,se_itimer ); -- rbus interface definitions ------------------------------------------------ constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gr 0 constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gr 1 constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gr 2 constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gr 3 constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gr 4 constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gr 5 constant c_rbaddr_sp : slv5 := "01110"; -- R/W gr 6 (sp) constant c_rbaddr_pc : slv5 := "01111"; -- R/W gr 7 (pc) constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables constant c_init_rbf_greset: integer := 0; subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag -- ------------------------------------- component pdp11_gr is -- general registers port ( CLK : in slbit; -- clock DIN : in slv16; -- input data ASRC : in slv3; -- source register number ADST : in slv3; -- destination register number MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11) RSET : in slbit; -- register set WE : in slbit; -- write enable BYTOP : in slbit; -- byte operation (write low byte only) PCINC : in slbit; -- increment PC DSRC : out slv16; -- source register data DDST : out slv16; -- destination register data PC : out slv16 -- current PC value ); end component; constant c_gr_r5 : slv3 := "101"; -- register number of r5 constant c_gr_sp : slv3 := "110"; -- register number of SP constant c_gr_pc : slv3 := "111"; -- register number of PC component pdp11_psr is -- processor status word register port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset DIN : in slv16; -- input data CCIN : in slv4; -- cc input CCWE : in slbit; -- enable update cc WE : in slbit; -- write enable (from DIN) FUNC : in slv3; -- write function (from DIN) PSW : out psw_type; -- current psw IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes constant c_psr_func_wall : slv3 := "100"; -- write all fields component pdp11_ounit is -- offset adder for addresses (ounit) port ( DSRC : in slv16; -- 'src' data for port A DDST : in slv16; -- 'dst' data for port A DTMP : in slv16; -- 'tmp' data for port A PC : in slv16; -- PC data for port A ASEL : in slv2; -- selector for port A AZERO : in slbit; -- force zero for port A IREG8 : in slv8; -- 'ireg' data for port B VMDOUT : in slv16; -- virt. memory data for port B CONST : in slv9; -- sequencer const data for port B BSEL : in slv2; -- selector for port B OPSUB : in slbit; -- operation: 0 add, 1 sub DOUT : out slv16; -- data output NZOUT : out slv2 -- NZ condition codes out ); end component; constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC constant c_ounit_asel_pc : slv2 := "10"; -- A = PC constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit) constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend) component pdp11_aunit is -- arithmetic unit for data (aunit) port ( DSRC : in slv16; -- 'src' data in DDST : in slv16; -- 'dst' data in CI : in slbit; -- carry flag in SRCMOD : in slv2; -- src modifier mode DSTMOD : in slv2; -- dst modifier mode CIMOD : in slv2; -- ci modifier mode CC1OP : in slbit; -- use cc modes (1 op instruction) CCMODE : in slv3; -- cc mode BYTOP : in slbit; -- byte operation DOUT : out slv16; -- data output CCOUT : out slv4 -- condition codes out ); end component; constant c_aunit_mod_pass : slv2 := "00"; -- pass data constant c_aunit_mod_inv : slv2 := "01"; -- invert data constant c_aunit_mod_zero : slv2 := "10"; -- set to 0 constant c_aunit_mod_one : slv2 := "11"; -- set to 1 -- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6) constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction component pdp11_lunit is -- logic unit for data (lunit) port ( DSRC : in slv16; -- 'src' data in DDST : in slv16; -- 'dst' data in CCIN : in slv4; -- condition codes in FUNC : in slv4; -- function BYTOP : in slbit; -- byte operation DOUT : out slv16; -- data output CCOUT : out slv4 -- condition codes out ); end component; constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !! constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB constant c_lunit_func_sxt : slv4 := "1000"; -- SXT constant c_lunit_func_swap : slv4 := "1001"; -- SWAB constant c_lunit_func_xor : slv4 := "1010"; -- XOR component pdp11_munit is -- mul/div unit for data (munit) port ( CLK : in slbit; -- clock DSRC : in slv16; -- 'src' data in DDST : in slv16; -- 'dst' data in DTMP : in slv16; -- 'tmp' data in GR_DSRC : in slv16; -- 'src' data from GR FUNC : in slv2; -- function S_DIV : in slbit; -- s_opg_div state (load dd_low) S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle) S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.) S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder) S_ASH : in slbit; -- s_opg_ash state S_ASH_CN : in slbit; -- s_opg_ash_cn state S_ASHC : in slbit; -- s_opg_ashc state S_ASHC_CN : in slbit; -- s_opg_ashc_cn state SHC_TC : out slbit; -- last shc cycle (shc==0) DIV_CR : out slbit; -- division: remainder correction needed DIV_CQ : out slbit; -- division: quotient correction needed DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1) DOUT : out slv16; -- data output DOUTE : out slv16; -- data output extra CCOUT : out slv4 -- condition codes out ); end component; constant c_munit_func_mul : slv2 := "00"; -- MUL constant c_munit_func_div : slv2 := "01"; -- DIV constant c_munit_func_ash : slv2 := "10"; -- ASH constant c_munit_func_ashc : slv2 := "11"; -- ASHC component pdp11_mmu_padr is -- mmu PAR/PDR register set port ( CLK : in slbit; -- clock MODE : in slv2; -- mode APN : in slv4; -- augmented page number (1+3 bit) AIB_WE : in slbit; -- update AIB AIB_SETA : in slbit; -- set access AIB AIB_SETW : in slbit; -- set write AIB PARPDR : out parpdr_type; -- combined PAR/PDR IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2 port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset TRACE : in slbit; -- trace enable MONI : in mmu_moni_type; -- MMU monitor port data IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_mmu is -- mmu - memory management unit port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset BRESET : in slbit; -- bus reset CNTL : in mmu_cntl_type; -- control port VADDR : in slv16; -- virtual address MONI : in mmu_moni_type; -- monitor port STAT : out mmu_stat_type; -- status port PADDRH : out slv16; -- physical address (upper 16 bit) IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_vmbox is -- virtual memory port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset CRESET : in slbit; -- cpu reset BRESET : in slbit; -- bus reset CP_ADDR : in cp_addr_type; -- console port address VM_CNTL : in vm_cntl_type; -- vm control port VM_ADDR : in slv16; -- vm address VM_DIN : in slv16; -- vm data in VM_STAT : out vm_stat_type; -- vm status port VM_DOUT : out slv16; -- vm data out EM_MREQ : out em_mreq_type; -- external memory: request EM_SRES : in em_sres_type; -- external memory: response MMU_MONI : in mmu_moni_type; -- mmu monitor port IB_MREQ_M : out ib_mreq_type; -- ibus request (master) IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers) IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices) DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status ); end component; component pdp11_dpath is -- CPU datapath port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset CNTL : in dpath_cntl_type; -- control interface STAT : out dpath_stat_type; -- status interface CP_DIN : in slv16; -- console port data in CP_DOUT : out slv16; -- console port data out PSWOUT : out psw_type; -- current psw PCOUT : out slv16; -- current pc IREG : out slv16; -- ireg out VM_ADDR : out slv16; -- virt. memory address VM_DOUT : in slv16; -- virt. memory data out VM_DIN : out slv16; -- virt. memory data in IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath ); end component; component pdp11_decode is -- instruction decoder port ( IREG : in slv16; -- input instruction word STAT : out decode_stat_type -- status output ); end component; component pdp11_sequencer is -- cpu sequencer port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset PSW : in psw_type; -- processor status PC : in slv16; -- program counter IREG : in slv16; -- IREG ID_STAT : in decode_stat_type; -- instr. decoder status DP_STAT : in dpath_stat_type; -- data path status CP_CNTL : in cp_cntl_type; -- console port control VM_STAT : in vm_stat_type; -- virtual memory status port INT_PRI : in slv3; -- interrupt priority INT_VECT : in slv9_2; -- interrupt vector INT_ACK : out slbit; -- interrupt acknowledge CRESET : out slbit; -- cpu reset BRESET : out slbit; -- bus reset MMU_MONI : out mmu_moni_type; -- mmu monitor port DP_CNTL : out dpath_cntl_type; -- data path control VM_CNTL : out vm_cntl_type; -- virtual memory control port CP_STAT : out cp_stat_type; -- console port status ESUSP_O : out slbit; -- external suspend output ESUSP_I : in slbit; -- external suspend input HBPT : in slbit; -- hardware bpt IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer ); end component; component pdp11_irq is -- interrupt requester port ( CLK : in slbit; -- clock BRESET : in slbit; -- bus reset INT_ACK : in slbit; -- interrupt acknowledge from CPU EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector EI_ACKM : out slbit; -- external interrupt acknowledge PRI : out slv3; -- interrupt priority VECT : out slv9_2; -- interrupt vector IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_ubmap is -- 11/70 unibus mapper port ( CLK : in slbit; -- clock MREQ : in slbit; -- request mapping ADDR_UB : in slv18_1; -- UNIBUS address (in) ADDR_PM : out slv22_1; -- physical memory address (out) IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_reg70 is -- 11/70 memory system registers port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_mem70 is -- 11/70 memory system registers port ( CLK : in slbit; -- clock CRESET : in slbit; -- cpu reset HM_ENA : in slbit; -- hit/miss enable HM_VAL : in slbit; -- hit/miss value CACHE_FMISS : out slbit; -- cache force miss IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); end component; component pdp11_cache is -- cache generic ( TWIDTH : positive := 9); -- tag width (5 to 9) port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type; -- em response FMISS : in slbit; -- force miss MEM_REQ : out slbit; -- memory: request MEM_WE : out slbit; -- memory: write enable MEM_BUSY : in slbit; -- memory: controller busy MEM_ACK_R : in slbit; -- memory: acknowledge read MEM_ADDR : out slv20; -- memory: address MEM_BE : out slv4; -- memory: byte enable MEM_DI : out slv32; -- memory: data in (memory view) MEM_DO : in slv32; -- memory: data out (memory view) DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache ); end component; component pdp11_core is -- full processor core port ( CLK : in slbit; -- clock RESET : in slbit; -- reset CP_CNTL : in cp_cntl_type; -- console control port CP_ADDR : in cp_addr_type; -- console address port CP_DIN : in slv16; -- console data in CP_STAT : out cp_stat_type; -- console status port CP_DOUT : out slv16; -- console data out ESUSP_O : out slbit; -- external suspend output ESUSP_I : in slbit; -- external suspend input HBPT : in slbit; -- hardware bpt EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector EI_ACKM : out slbit; -- external interrupt acknowledge EM_MREQ : out em_mreq_type; -- external memory: request EM_SRES : in em_sres_type; -- external memory: response CRESET : out slbit; -- cpu reset BRESET : out slbit; -- bus reset IB_MREQ_M : out ib_mreq_type; -- ibus master request (master) IB_SRES_M : in ib_sres_type; -- ibus slave response (master) DM_STAT_SE : out dm_stat_se_type; -- debug and monitor status - sequencer DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core ); end component; component pdp11_tmu is -- trace and monitor unit port ( CLK : in slbit; -- clock ENA : in slbit := '0'; -- enable trace output DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end component; -- this definition logically belongs into a 'for test benches' section' -- it is here for convenience to simplify instantiations. constant sbcntl_sbf_tmu : integer := 12; component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper generic ( ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu port ( CLK : in slbit; -- clock DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache ); end component; component pdp11_du_drv is -- display unit low level driver generic ( CDWIDTH : positive := 3); -- clock divider width port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset ROW0 : in slv22; -- led row 0 (22 leds, top) ROW1 : in slv16; -- led row 1 (16 leds) ROW2 : in slv16; -- led row 2 (16 leds) ROW3 : in slv10; -- led row 3 (10 leds, bottom) SWOPT : out slv8; -- option pattern from du SWOPT_RDY : out slbit; -- marks update of swopt DU_SCLK : out slbit; -- DU: sclk DU_SS_N : out slbit; -- DU: ss_n DU_MOSI : out slbit; -- DU: mosi (master out, slave in) DU_MISO : in slbit -- DU: miso (master in, slave out) ); end component; component pdp11_bram is -- BRAM based ext. memory dummy generic ( AWIDTH : positive := 14); -- address width port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type -- em response ); end component; component pdp11_bram_memctl is -- BRAM based memctl generic ( MAWIDTH : positive := 4; -- mux address width NBLOCK : positive := 11); -- number of 16 kByte blocks port ( CLK : in slbit; -- clock RESET : in slbit; -- reset REQ : in slbit; -- request WE : in slbit; -- write enable BUSY : out slbit; -- controller busy ACK_R : out slbit; -- acknowledge read ACK_W : out slbit; -- acknowledge write ACT_R : out slbit; -- signal active read ACT_W : out slbit; -- signal active write ADDR : in slv20; -- address BE : in slv4; -- byte enable DI : in slv32; -- data in (memory view) DO : out slv32 -- data out (memory view) ); end component; component pdp11_statleds is -- status leds port ( MEM_ACT_R : in slbit; -- memory active read MEM_ACT_W : in slbit; -- memory active write CP_STAT : in cp_stat_type; -- console port status DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports STATLEDS : out slv8 -- 8 bit CPU status ); end component; component pdp11_ledmux is -- hio led mux generic ( LWIDTH : positive := 8); -- led width port ( SEL : in slbit; -- select (0=stat;1=dr) STATLEDS : in slv8; -- 8 bit CPU status DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports LED : out slv(LWIDTH-1 downto 0) -- hio leds ); end component; component pdp11_dspmux is -- hio dsp mux generic ( DCWIDTH : positive := 2); -- digit counter width (2 or 3) port ( SEL : in slv2; -- select ABCLKDIV : in slv16; -- serport clock divider DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports DISPREG : in slv16; -- display register DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data ); end component; component pdp11_core_rbus is -- core to rbus interface generic ( RB_ADDR_CORE : slv16 := rbaddr_cpu0_core; RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response RB_STAT : out slv4; -- rbus: status flags RB_LAM : out slbit; -- remote attention GRESET : out slbit; -- general reset CP_CNTL : out cp_cntl_type; -- console control port CP_ADDR : out cp_addr_type; -- console address port CP_DIN : out slv16; -- console data in CP_STAT : in cp_stat_type; -- console status port CP_DOUT : in slv16 -- console data out ); end component; component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus request (slave) RB_SRES : out rb_sres_type; -- rbus response RB_STAT : out slv4; -- rbus status flags RB_LAM_CPU : out slbit; -- rbus lam (cpu) GRESET : out slbit; -- general reset (from rbus) CRESET : out slbit; -- cpu reset (from cp) BRESET : out slbit; -- bus reset (from cp or cpu) CP_STAT : out cp_stat_type; -- console port status EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector EI_ACKM : out slbit; -- external interrupt acknowledge PERFEXT : in slv8; -- cpu external perf counter signals IB_MREQ : out ib_mreq_type; -- ibus request (master) IB_SRES : in ib_sres_type; -- ibus response (from IO system) MEM_REQ : out slbit; -- memory: request MEM_WE : out slbit; -- memory: write enable MEM_BUSY : in slbit; -- memory: controller busy MEM_ACK_R : in slbit; -- memory: acknowledge read MEM_ADDR : out slv20; -- memory: address MEM_BE : out slv4; -- memory: byte enable MEM_DI : out slv32; -- memory: data in (memory view) MEM_DO : in slv32; -- memory: data out (memory view) DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports ); end component; component pdp11_hio70 is -- hio led and dsp for sys70 generic ( LWIDTH : positive := 8; -- led width DCWIDTH : positive := 2); -- digit counter width (2 or 3) port ( SEL_LED : in slbit; -- led select (0=stat;1=dr) SEL_DSP : in slv2; -- dsp select MEM_ACT_R : in slbit; -- memory active read MEM_ACT_W : in slbit; -- memory active write CP_STAT : in cp_stat_type; -- console port status DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports ABCLKDIV : in slv16; -- serport clock divider DISPREG : in slv16; -- display register LED : out slv(LWIDTH-1 downto 0); -- hio leds DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data ); end component; component pdp11_dmscnt is -- debug&moni: state counter generic ( RB_ADDR : slv16 := rbaddr_dmscnt_off); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core ); end component; component pdp11_dmcmon is -- debug&moni: cpu monitor generic ( RB_ADDR : slv16 := rbaddr_dmcmon_off; AWIDTH : natural := 8; SNUM : boolean := false); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core ); end component; component pdp11_dmhbpt is -- debug&moni: hardware breakpoint generic ( RB_ADDR : slv16 := rbaddr_dmhbpt_off; NUNIT : natural := 2); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core HBPT : out slbit -- hw break flag ); end component; component pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit generic ( RB_ADDR : slv16 := rbaddr_dmhbpt_off; INDEX : natural := 0); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core HBPT : out slbit -- hw break flag ); end component; component pdp11_dmpcnt is -- debug&moni: performance counters generic ( RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address VERS : slv8 := slv(to_unsigned(0, 8)); -- counter layout version CENA : slv32 := (others=>'1')); -- counter enables port ( CLK : in slbit; -- clock RESET : in slbit; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response PERFSIG : in slv32 -- signals to count ); end component; -- ----- move later to pdp11_conf -------------------------------------------- constant conf_vect_pirq : integer := 8#240#; constant conf_pri_pirq_1 : integer := 1; constant conf_pri_pirq_2 : integer := 2; constant conf_pri_pirq_3 : integer := 3; constant conf_pri_pirq_4 : integer := 4; constant conf_pri_pirq_5 : integer := 5; constant conf_pri_pirq_6 : integer := 6; constant conf_pri_pirq_7 : integer := 7; end package pdp11;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GoRWLEBLr9TiqcUWnetwihh+GHwEuIFkzCRFaq6hTQlc76QQpjgME6tkw2VI5EkH+SmIYW4AqvHH pd+Y8uwH2Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ptT+vqjUBg7mV2MJNdoLhkMQwhwuWPmaA1aMcTS31MbEP67gPPL4ZUPC9AWc2zCK8MpwIExu0pi4 MQiOtxd8KiPXFrLqLz85vMy+nQBpwXhV3i/WZj8N6md8gdjPfdSSonfcrLKhl/xu5c1PRAXOwbMq giTx21VIBCu/jELIbiQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GoRWLEBLr9TiqcUWnetwihh+GHwEuIFkzCRFaq6hTQlc76QQpjgME6tkw2VI5EkH+SmIYW4AqvHH pd+Y8uwH2Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ptT+vqjUBg7mV2MJNdoLhkMQwhwuWPmaA1aMcTS31MbEP67gPPL4ZUPC9AWc2zCK8MpwIExu0pi4 MQiOtxd8KiPXFrLqLz85vMy+nQBpwXhV3i/WZj8N6md8gdjPfdSSonfcrLKhl/xu5c1PRAXOwbMq giTx21VIBCu/jELIbiQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity hex2bcd is port ( CLK : in std_logic; --PUSH BUTTONS PIN ASSIGNMENT --SWITCH PIN ASSIGNMENT sw0 :in std_logic_vector(3 downto 0); sw1 :in std_logic_vector(3 downto 0); sw2 :in std_logic_vector(3 downto 0); sw3 :in std_logic_vector(3 downto 0); --YOU COULD HAVE ALSO WRITTEN -- sw: in std_logic_vector(17 downto 0); -- that would have worked too. But I did another project, SO I just kept it like that. Quartus is a pain in the butt when assigning pin. Its so time consuming and stupid :P bcd0:out std_logic_vector(3 downto 0); bcd1:out std_logic_vector(3 downto 0); bcd2:out std_logic_vector(3 downto 0); bcd3:out std_logic_vector(3 downto 0)); end hex2bcd; architecture behavior of hex2bcd is begin --You cannot have variables here my_proc: process (CLK) --Variable assignment variable random: std_logic_vector(15 downto 0) := "0000000000000000"; --16 BITS variable one: std_logic_vector(3 downto 0) := "0000"; variable ten: std_logic_vector(3 downto 0) := "0000"; variable hund: std_logic_vector(3 downto 0) := "0000"; variable thou: std_logic_vector(3 downto 0) := "0000"; variable tthou: std_logic_vector(3 downto 0) := "0000"; variable hthou: std_logic_vector(3 downto 0) := "0000"; begin --ON RISING EDGE OF CLOCK, DO THIS FUNCTION if (rising_edge(CLK)) then random := sw3 & sw2 & sw1 & sw0; for i in 0 to 15 loop --CHECKING IF THE NUMBER IS GREATER OR EQUAL TO 5 -- IF YES, THEN ADD 3 -- NOTE: THIS IS NOT THE MOST EFFICIENT WAY TO DO IT. But who cares :P! if (hthou >= "0101") then hthou := std_logic_vector (unsigned(hthou) +3); end if; if (tthou >= "0101") then tthou := std_logic_vector (unsigned(tthou) +3); end if; if (thou >= "0101") then thou := std_logic_vector (unsigned(thou) +3); end if; if (hund >= "0101") then hund := std_logic_vector (unsigned(hund) +3); end if; if (ten >= "0101") then ten := std_logic_vector (unsigned(ten) +3); end if; if (one >= "0101") then one := std_logic_vector (unsigned(one) +3); end if; -- HERE I AM DOING THE SHIFTING WORK hthou := hthou(2 downto 0) & tthou(3); tthou := tthou(2 downto 0) & thou(3); thou := thou(2 downto 0)& hund(3); hund := hund(2 downto 0)& ten(3); ten := ten(2 downto 0)& one(3); one := one(2 downto 0)& random(15); random := std_logic_vector(unsigned(random) sll 1); end loop; bcd0 <= one; bcd1 <= ten; bcd2 <= hund; bcd3 <= thou; one := "0000"; ten:= "0000"; hund := "0000"; thou := "0000"; tthou:= "0000"; hthou:= "0000"; end if; end process ; end behavior;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common.all; entity regfile is port (clk : in std_logic; addra : in std_logic_vector(4 downto 0); addrb : in std_logic_vector(4 downto 0); rega : out word; regb : out word; addrw : in std_logic_vector(4 downto 0); dataw : in word; we : in std_logic); end entity regfile; -- -- Note: Because this core is FPGA-targeted, the idea is that these registers -- will get implemented as dual-port Distributed RAM. Because there is no -- such thing as triple-port memory in an FPGA (that I know of), and we -- need 3 ports to support 2 reads and 1 write per cycle, the easiest way -- to implement that is to have two identical banks of registers that contain -- the same data. Each uses 2 ports and everybody's happy. -- architecture rtl of regfile is type regbank_t is array (0 to 31) of word; signal regbank0 : regbank_t := (others => (others => '0')); signal regbank1 : regbank_t := (others => (others => '0')); begin -- architecture Behavioral -- purpose: create registers -- type : sequential -- inputs : clk -- outputs: registers_proc : process (clk) is begin -- process registers_proc if rising_edge(clk) then if (we = '1') then regbank0(to_integer(unsigned(addrw))) <= dataw; regbank1(to_integer(unsigned(addrw))) <= dataw; end if; end if; end process registers_proc; -- asynchronous read rega <= regbank0(to_integer(unsigned(addra))); regb <= regbank1(to_integer(unsigned(addrb))); end architecture rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common.all; entity regfile is port (clk : in std_logic; addra : in std_logic_vector(4 downto 0); addrb : in std_logic_vector(4 downto 0); rega : out word; regb : out word; addrw : in std_logic_vector(4 downto 0); dataw : in word; we : in std_logic); end entity regfile; -- -- Note: Because this core is FPGA-targeted, the idea is that these registers -- will get implemented as dual-port Distributed RAM. Because there is no -- such thing as triple-port memory in an FPGA (that I know of), and we -- need 3 ports to support 2 reads and 1 write per cycle, the easiest way -- to implement that is to have two identical banks of registers that contain -- the same data. Each uses 2 ports and everybody's happy. -- architecture rtl of regfile is type regbank_t is array (0 to 31) of word; signal regbank0 : regbank_t := (others => (others => '0')); signal regbank1 : regbank_t := (others => (others => '0')); begin -- architecture Behavioral -- purpose: create registers -- type : sequential -- inputs : clk -- outputs: registers_proc : process (clk) is begin -- process registers_proc if rising_edge(clk) then if (we = '1') then regbank0(to_integer(unsigned(addrw))) <= dataw; regbank1(to_integer(unsigned(addrw))) <= dataw; end if; end if; end process registers_proc; -- asynchronous read rega <= regbank0(to_integer(unsigned(addra))); regb <= regbank1(to_integer(unsigned(addrb))); end architecture rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common.all; entity regfile is port (clk : in std_logic; addra : in std_logic_vector(4 downto 0); addrb : in std_logic_vector(4 downto 0); rega : out word; regb : out word; addrw : in std_logic_vector(4 downto 0); dataw : in word; we : in std_logic); end entity regfile; -- -- Note: Because this core is FPGA-targeted, the idea is that these registers -- will get implemented as dual-port Distributed RAM. Because there is no -- such thing as triple-port memory in an FPGA (that I know of), and we -- need 3 ports to support 2 reads and 1 write per cycle, the easiest way -- to implement that is to have two identical banks of registers that contain -- the same data. Each uses 2 ports and everybody's happy. -- architecture rtl of regfile is type regbank_t is array (0 to 31) of word; signal regbank0 : regbank_t := (others => (others => '0')); signal regbank1 : regbank_t := (others => (others => '0')); begin -- architecture Behavioral -- purpose: create registers -- type : sequential -- inputs : clk -- outputs: registers_proc : process (clk) is begin -- process registers_proc if rising_edge(clk) then if (we = '1') then regbank0(to_integer(unsigned(addrw))) <= dataw; regbank1(to_integer(unsigned(addrw))) <= dataw; end if; end if; end process registers_proc; -- asynchronous read rega <= regbank0(to_integer(unsigned(addra))); regb <= regbank1(to_integer(unsigned(addrb))); end architecture rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:35:17 04/18/2016 -- Design Name: -- Module Name: Test - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; --la IEEE in particolare tutto della STD_LOGIC_1164 use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Test is --entity e` il nome della scatola che finisce con END <scatola> definisco i segnali Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; E : out STD_LOGIC); end Test; -- contenuto della scatola -- il Maximum combinational path delay: 5.259ns e` il massimo ritardo di calcolo combinatorio architecture Behavioral of Test is signal D : std_logic; begin --primo costrutto D <= A AND B; E <= C AND D; --secondo costrutto --E <= A AND B AND C; --terzo costrutto --E <= A and B; --E <= '1' when (A='1' and B='1') -- else '0'; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/18/2015 04:45:31 PM -- Design Name: -- Module Name: HalfAdder - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity HalfAdder is Port ( A : in BIT; -- 1st bit to sum up B : in BIT; -- 2nd bit to sum up S : out BIT; -- Sum of both bits C : out BIT -- Carry flag ); end HalfAdder; architecture Behavioral of HalfAdder is begin S <= A xor B; C <= A and B; end Behavioral;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
package body fifo_pkg is end package body fifo_pkg; package body fifo_pkg is end package body fifo_pkg;
-------------------------------------------------------------------------------- -- File : tri_mode_ethernet_mac_0_example_design.vhd -- Author : Xilinx Inc. -- ----------------------------------------------------------------------------- -- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ----------------------------------------------------------------------------- -- Description: This is the Verilog example design for the Tri-Mode -- Ethernet MAC core. It is intended that this example design -- can be quickly adapted and downloaded onto an FPGA to provide -- a real hardware test environment. -- -- This level: -- -- * Instantiates the FIFO Block wrapper, containing the -- block level wrapper and an RX and TX FIFO with an -- AXI-S interface; -- -- * Instantiates a simple AXI-S example design, -- providing an address swap and a simple -- loopback function; -- -- * Instantiates transmitter clocking circuitry -- -the User side of the FIFOs are clocked at gtx_clk -- at all times -- -- * Instantiates a state machine which drives the AXI Lite -- interface to bring the TEMAC up in the correct state -- -- * Serializes the Statistics vectors to prevent logic being -- optimized out -- -- * Ties unused inputs off to reduce the number of IO -- -- Please refer to the Datasheet, Getting Started Guide, and -- the Tri-Mode Ethernet MAC User Gude for further information. -- -- -- -------------------------------------------------- -- | EXAMPLE DESIGN WRAPPER | -- | | -- | | -- | ------------------- ------------------- | -- | | | | | | -- | | Clocking | | Resets | | -- | | | | | | -- | ------------------- ------------------- | -- | -------------------------------------| -- | |FIFO BLOCK WRAPPER | -- | | | -- | | | -- | | ----------------------| -- | | | SUPPORT LEVEL | -- | -------- | | | -- | | | | | | -- | | AXI |->|------------->| | -- | | LITE | | | | -- | | SM | | | | -- | | |<-|<-------------| | -- | | | | | | -- | -------- | | | -- | | | | -- | -------- | ---------- | | -- | | | | | | | | -- | | |->|->| |->| | -- | | PAT | | | | | | -- | | GEN | | | | | | -- | |(ADDR | | | AXI-S | | | -- | | SWAP)| | | FIFO | | | -- | | | | | | | | -- | | | | | | | | -- | | | | | | | | -- | | |<-|<-| |<-| | -- | | | | | | | | -- | -------- | ---------- | | -- | | | | -- | | ----------------------| -- | -------------------------------------| -- -------------------------------------------------- -------------------------------------------------------- library unisim; use unisim.vcomponents.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------------------------------------------------- -- The entity declaration for the example_design level wrapper. -------------------------------------------------------------------------------- entity tri_mode_ethernet_mac_0_example_design is port ( -- asynchronous reset glbl_rst : in std_logic; -- 200MHz clock input from board clk_in_p : in std_logic; clk_in_n : in std_logic; phy_resetn : out std_logic; -- GMII Interface ----------------- gmii_txd : out std_logic_vector(7 downto 0); gmii_tx_en : out std_logic; gmii_tx_er : out std_logic; gmii_tx_clk : out std_logic; gmii_rxd : in std_logic_vector(7 downto 0); gmii_rx_dv : in std_logic; gmii_rx_er : in std_logic; gmii_rx_clk : in std_logic; mii_tx_clk : in std_logic; -- MDIO Interface ----------------- mdio : inout std_logic; mdc : out std_logic; -- Serialised statistics vectors -------------------------------- tx_statistics_s : out std_logic; rx_statistics_s : out std_logic; -- Serialised Pause interface controls -------------------------------------- pause_req_s : in std_logic; -- Main example design controls ------------------------------- mac_speed : in std_logic_vector(1 downto 0); update_speed : in std_logic; config_board : in std_logic; --serial_command : in std_logic; -- tied to pause_req_s serial_response : out std_logic; gen_tx_data : in std_logic; chk_tx_data : in std_logic; reset_error : in std_logic; frame_error : out std_logic; frame_errorn : out std_logic; activity_flash : out std_logic; activity_flashn : out std_logic ); end tri_mode_ethernet_mac_0_example_design; architecture wrapper of tri_mode_ethernet_mac_0_example_design is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes"; ------------------------------------------------------------------------------ -- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_fifo_block port( gtx_clk : in std_logic; -- asynchronous reset glbl_rstn : in std_logic; rx_axi_rstn : in std_logic; tx_axi_rstn : in std_logic; -- Reference clock for IDELAYCTRL's refclk : in std_logic; -- Receiver Statistics Interface ----------------------------------------- rx_mac_aclk : out std_logic; rx_reset : out std_logic; rx_statistics_vector : out std_logic_vector(27 downto 0); rx_statistics_valid : out std_logic; -- Receiver (AXI-S) Interface ------------------------------------------ rx_fifo_clock : in std_logic; rx_fifo_resetn : in std_logic; rx_axis_fifo_tdata : out std_logic_vector(7 downto 0); rx_axis_fifo_tvalid : out std_logic; rx_axis_fifo_tready : in std_logic; rx_axis_fifo_tlast : out std_logic; -- Transmitter Statistics Interface -------------------------------------------- tx_mac_aclk : out std_logic; tx_reset : out std_logic; tx_ifg_delay : in std_logic_vector(7 downto 0); tx_statistics_vector : out std_logic_vector(31 downto 0); tx_statistics_valid : out std_logic; -- Transmitter (AXI-S) Interface --------------------------------------------- tx_fifo_clock : in std_logic; tx_fifo_resetn : in std_logic; tx_axis_fifo_tdata : in std_logic_vector(7 downto 0); tx_axis_fifo_tvalid : in std_logic; tx_axis_fifo_tready : out std_logic; tx_axis_fifo_tlast : in std_logic; -- MAC Control Interface -------------------------- pause_req : in std_logic; pause_val : in std_logic_vector(15 downto 0); -- GMII Interface ------------------- gmii_txd : out std_logic_vector(7 downto 0); gmii_tx_en : out std_logic; gmii_tx_er : out std_logic; gmii_tx_clk : out std_logic; gmii_rxd : in std_logic_vector(7 downto 0); gmii_rx_dv : in std_logic; gmii_rx_er : in std_logic; gmii_rx_clk : in std_logic; mii_tx_clk : in std_logic; -- MDIO Interface ------------------- mdio : inout std_logic; mdc : out std_logic; -- AXI-Lite Interface ----------------- s_axi_aclk : in std_logic; s_axi_resetn : in std_logic; s_axi_awaddr : in std_logic_vector(11 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(11 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic ); end component; ------------------------------------------------------------------------------ -- Component Declaration for the basic pattern generator ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_basic_pat_gen generic ( DEST_ADDR : bit_vector(47 downto 0) := X"da0102030405"; SRC_ADDR : bit_vector(47 downto 0) := X"5a0102030405"; MAX_SIZE : unsigned(11 downto 0) := X"1f4"; MIN_SIZE : unsigned(11 downto 0) := X"040"; ENABLE_VLAN : boolean := false; VLAN_ID : bit_vector(11 downto 0) := X"002"; VLAN_PRIORITY : bit_vector(2 downto 0) := "010" ); port ( axi_tclk : in std_logic; axi_tresetn : in std_logic; check_resetn : in std_logic; enable_pat_gen : in std_logic; enable_pat_chk : in std_logic; enable_address_swap : in std_logic; speed : in std_logic_vector(1 downto 0); -- data from the RX data path rx_axis_tdata : in std_logic_vector(7 downto 0); rx_axis_tvalid : in std_logic; rx_axis_tlast : in std_logic; rx_axis_tuser : in std_logic; rx_axis_tready : out std_logic; -- data TO the TX data path tx_axis_tdata : out std_logic_vector(7 downto 0); tx_axis_tvalid : out std_logic; tx_axis_tlast : out std_logic; tx_axis_tready : in std_logic; frame_error : out std_logic; activity_flash : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component Declaration for the AXI-Lite State machine ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_axi_lite_sm port ( s_axi_aclk : in std_logic; s_axi_resetn : in std_logic; mac_speed : in std_logic_vector(1 downto 0); update_speed : in std_logic; serial_command : in std_logic; serial_response : out std_logic; phy_loopback : in std_logic; s_axi_awaddr : out std_logic_vector(11 downto 0); s_axi_awvalid : out std_logic; s_axi_awready : in std_logic; s_axi_wdata : out std_logic_vector(31 downto 0); s_axi_wvalid : out std_logic; s_axi_wready : in std_logic; s_axi_bresp : in std_logic_vector(1 downto 0); s_axi_bvalid : in std_logic; s_axi_bready : out std_logic; s_axi_araddr : out std_logic_vector(11 downto 0); s_axi_arvalid : out std_logic; s_axi_arready : in std_logic; s_axi_rdata : in std_logic_vector(31 downto 0); s_axi_rresp : in std_logic_vector(1 downto 0); s_axi_rvalid : in std_logic; s_axi_rready : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component declaration for the synchroniser ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_sync_block port ( clk : in std_logic; data_in : in std_logic; data_out : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component declaration for the clocking logic ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_example_design_clocks is port ( -- clocks clk_in_p : in std_logic; clk_in_n : in std_logic; -- asynchronous resets glbl_rst : in std_logic; dcm_locked : out std_logic; -- clock outputs gtx_clk_bufg : out std_logic; refclk_bufg : out std_logic; s_axi_aclk : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component declaration for the reset logic ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_example_design_resets is port ( -- clocks s_axi_aclk : in std_logic; gtx_clk : in std_logic; -- asynchronous resets glbl_rst : in std_logic; reset_error : in std_logic; rx_reset : in std_logic; tx_reset : in std_logic; dcm_locked : in std_logic; -- synchronous reset outputs glbl_rst_intn : out std_logic; gtx_resetn : out std_logic := '0'; s_axi_resetn : out std_logic := '0'; phy_resetn : out std_logic; chk_resetn : out std_logic := '0' ); end component; ------------------------------------------------------------------------------ -- internal signals used in this top level wrapper. ------------------------------------------------------------------------------ -- example design clocks signal gtx_clk_bufg : std_logic; signal refclk_bufg : std_logic; signal s_axi_aclk : std_logic; signal rx_mac_aclk : std_logic; signal tx_mac_aclk : std_logic; signal phy_resetn_int : std_logic; -- resets (and reset generation) signal s_axi_resetn : std_logic; signal chk_resetn : std_logic; signal gtx_resetn : std_logic; signal rx_reset : std_logic; signal tx_reset : std_logic; signal dcm_locked : std_logic; signal glbl_rst_int : std_logic; signal phy_reset_count : unsigned(5 downto 0) := (others => '0'); signal glbl_rst_intn : std_logic; -- USER side RX AXI-S interface signal rx_fifo_clock : std_logic; signal rx_fifo_resetn : std_logic; signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0); signal rx_axis_fifo_tvalid : std_logic; signal rx_axis_fifo_tlast : std_logic; signal rx_axis_fifo_tready : std_logic; -- USER side TX AXI-S interface signal tx_fifo_clock : std_logic; signal tx_fifo_resetn : std_logic; signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0); signal tx_axis_fifo_tvalid : std_logic; signal tx_axis_fifo_tlast : std_logic; signal tx_axis_fifo_tready : std_logic; -- RX Statistics serialisation signals signal rx_statistics_valid : std_logic; signal rx_statistics_valid_reg : std_logic; signal rx_statistics_vector : std_logic_vector(27 downto 0); signal rx_stats : std_logic_vector(27 downto 0); signal rx_stats_shift : std_logic_vector(29 downto 0); signal rx_stats_toggle : std_logic := '0'; signal rx_stats_toggle_sync : std_logic; signal rx_stats_toggle_sync_reg : std_logic := '0'; -- TX Statistics serialisation signals signal tx_statistics_valid : std_logic; signal tx_statistics_valid_reg : std_logic; signal tx_statistics_vector : std_logic_vector(31 downto 0); signal tx_stats : std_logic_vector(31 downto 0); signal tx_stats_shift : std_logic_vector(33 downto 0); signal tx_stats_toggle : std_logic := '0'; signal tx_stats_toggle_sync : std_logic; signal tx_stats_toggle_sync_reg : std_logic := '0'; -- Pause interface DESerialisation signal pause_shift : std_logic_vector(18 downto 0); signal pause_req : std_logic; signal pause_val : std_logic_vector(15 downto 0); -- AXI-Lite interface signal s_axi_awaddr : std_logic_vector(11 downto 0); signal s_axi_awvalid : std_logic; signal s_axi_awready : std_logic; signal s_axi_wdata : std_logic_vector(31 downto 0); signal s_axi_wvalid : std_logic; signal s_axi_wready : std_logic; signal s_axi_bresp : std_logic_vector(1 downto 0); signal s_axi_bvalid : std_logic; signal s_axi_bready : std_logic; signal s_axi_araddr : std_logic_vector(11 downto 0); signal s_axi_arvalid : std_logic; signal s_axi_arready : std_logic; signal s_axi_rdata : std_logic_vector(31 downto 0); signal s_axi_rresp : std_logic_vector(1 downto 0); signal s_axi_rvalid : std_logic; signal s_axi_rready : std_logic; -- signal tie offs signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example signal int_frame_error : std_logic; signal int_activity_flash : std_logic; -- set board defaults - only updated when reprogrammed signal enable_address_swap : std_logic := '1'; signal enable_phy_loopback : std_logic := '0'; ------------------------------------------------------------------------------ -- Begin architecture ------------------------------------------------------------------------------ begin frame_error <= int_frame_error; frame_errorn <= not int_frame_error; activity_flash <= int_activity_flash; activity_flashn <= not int_activity_flash; capture_board_modea : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then if config_board = '1' then enable_address_swap <= gen_tx_data; end if; end if; end process capture_board_modea; capture_board_modeb : process (s_axi_aclk) begin if s_axi_aclk'event and s_axi_aclk = '1' then if config_board = '1' then enable_phy_loopback <= chk_tx_data; end if; end if; end process capture_board_modeb; ---------------------------------------------------------------------------- -- Clock logic to generate required clocks from the 200MHz on board -- if 125MHz is available directly this can be removed ---------------------------------------------------------------------------- example_clocks : tri_mode_ethernet_mac_0_example_design_clocks port map ( -- differential clock inputs clk_in_p => clk_in_p, clk_in_n => clk_in_n, -- asynchronous control/resets glbl_rst => glbl_rst, dcm_locked => dcm_locked, -- clock outputs gtx_clk_bufg => gtx_clk_bufg, refclk_bufg => refclk_bufg, s_axi_aclk => s_axi_aclk ); -- generate the user side clocks for the axi fifos tx_fifo_clock <= gtx_clk_bufg; rx_fifo_clock <= gtx_clk_bufg; ------------------------------------------------------------------------------ -- Generate resets required for the fifo side signals etc ------------------------------------------------------------------------------ example_resets : tri_mode_ethernet_mac_0_example_design_resets port map ( -- clocks s_axi_aclk => s_axi_aclk, gtx_clk => gtx_clk_bufg, -- asynchronous resets glbl_rst => glbl_rst, reset_error => reset_error, rx_reset => rx_reset, tx_reset => tx_reset, dcm_locked => dcm_locked, -- synchronous reset outputs glbl_rst_intn => glbl_rst_intn, gtx_resetn => gtx_resetn, s_axi_resetn => s_axi_resetn, phy_resetn => phy_resetn, chk_resetn => chk_resetn ); -- generate the user side resets for the axi fifos tx_fifo_resetn <= gtx_resetn; rx_fifo_resetn <= gtx_resetn; ------------------------------------------------------------------------------ -- Serialize the stats vectors -- This is a single bit approach, retimed onto gtx_clk -- this code is only present to prevent code being stripped.. ------------------------------------------------------------------------------ -- RX STATS -- first capture the stats on the appropriate clock capture_rx_stats : process (rx_mac_aclk) begin if rx_mac_aclk'event and rx_mac_aclk = '1' then rx_statistics_valid_reg <= rx_statistics_valid; if rx_statistics_valid_reg = '0' and rx_statistics_valid = '1' then rx_stats <= rx_statistics_vector; rx_stats_toggle <= not rx_stats_toggle; end if; end if; end process capture_rx_stats; rx_stats_sync : tri_mode_ethernet_mac_0_sync_block port map ( clk => gtx_clk_bufg, data_in => rx_stats_toggle, data_out => rx_stats_toggle_sync ); reg_rx_toggle : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then rx_stats_toggle_sync_reg <= rx_stats_toggle_sync; end if; end process reg_rx_toggle; -- when an update is rxd load shifter (plus start/stop bit) -- shifter always runs (no power concerns as this is an example design) gen_shift_rx : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then if (rx_stats_toggle_sync_reg xor rx_stats_toggle_sync) = '1' then rx_stats_shift <= '1' & rx_stats & '1'; else rx_stats_shift <= rx_stats_shift(28 downto 0) & '0'; end if; end if; end process gen_shift_rx; rx_statistics_s <= rx_stats_shift(29); -- TX STATS -- first capture the stats on the appropriate clock capture_tx_stats : process (tx_mac_aclk) begin if tx_mac_aclk'event and tx_mac_aclk = '1' then tx_statistics_valid_reg <= tx_statistics_valid; if tx_statistics_valid_reg = '0' and tx_statistics_valid = '1' then tx_stats <= tx_statistics_vector; tx_stats_toggle <= not tx_stats_toggle; end if; end if; end process capture_tx_stats; tx_stats_sync : tri_mode_ethernet_mac_0_sync_block port map ( clk => gtx_clk_bufg, data_in => tx_stats_toggle, data_out => tx_stats_toggle_sync ); reg_tx_toggle : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then tx_stats_toggle_sync_reg <= tx_stats_toggle_sync; end if; end process reg_tx_toggle; -- when an update is txd load shifter (plus start bit) -- shifter always runs (no power concerns as this is an example design) gen_shift_tx : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then if (tx_stats_toggle_sync_reg /= tx_stats_toggle_sync) then tx_stats_shift <= '1' & tx_stats & '1'; else tx_stats_shift <= tx_stats_shift(32 downto 0) & '0'; end if; end if; end process gen_shift_tx; tx_statistics_s <= tx_stats_shift(33); ------------------------------------------------------------------------------ -- DESerialize the Pause interface -- This is a single bit approachtimed on gtx_clk -- this code is only present to prevent code being stripped.. ------------------------------------------------------------------------------ -- the serialised pause info has a start bit followed by the quanta and a stop bit -- capture the quanta when the start bit hits the msb and the stop bit is in the lsb gen_shift_pause : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then pause_shift <= pause_shift(17 downto 0) & pause_req_s; end if; end process gen_shift_pause; grab_pause : process (gtx_clk_bufg) begin if gtx_clk_bufg'event and gtx_clk_bufg = '1' then if (pause_shift(18) = '0' and pause_shift(17) = '1' and pause_shift(0) = '1') then pause_req <= '1'; pause_val <= pause_shift(16 downto 1); else pause_req <= '0'; pause_val <= (others => '0'); end if; end if; end process grab_pause; ------------------------------------------------------------------------------ -- Instantiate the AXI-LITE Controller ---------------------------------------------------------------------------- axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm port map ( s_axi_aclk => s_axi_aclk, s_axi_resetn => s_axi_resetn, mac_speed => mac_speed, update_speed => update_speed, serial_command => pause_req_s, serial_response => serial_response, phy_loopback => enable_phy_loopback, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); ------------------------------------------------------------------------------ -- Instantiate the TRIMAC core FIFO Block wrapper ------------------------------------------------------------------------------ trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block port map ( gtx_clk => gtx_clk_bufg, -- asynchronous reset glbl_rstn => glbl_rst_intn, rx_axi_rstn => '1', tx_axi_rstn => '1', -- Reference clock for IDELAYCTRL's refclk => refclk_bufg, -- Receiver Statistics Interface ----------------------------------------- rx_mac_aclk => rx_mac_aclk, rx_reset => rx_reset, rx_statistics_vector => rx_statistics_vector, rx_statistics_valid => rx_statistics_valid, -- Receiver => AXI-S Interface ------------------------------------------ rx_fifo_clock => rx_fifo_clock, rx_fifo_resetn => rx_fifo_resetn, rx_axis_fifo_tdata => rx_axis_fifo_tdata, rx_axis_fifo_tvalid => rx_axis_fifo_tvalid, rx_axis_fifo_tready => rx_axis_fifo_tready, rx_axis_fifo_tlast => rx_axis_fifo_tlast, -- Transmitter Statistics Interface -------------------------------------------- tx_mac_aclk => tx_mac_aclk, tx_reset => tx_reset, tx_ifg_delay => tx_ifg_delay, tx_statistics_vector => tx_statistics_vector, tx_statistics_valid => tx_statistics_valid, -- Transmitter => AXI-S Interface --------------------------------------------- tx_fifo_clock => tx_fifo_clock, tx_fifo_resetn => tx_fifo_resetn, tx_axis_fifo_tdata => tx_axis_fifo_tdata, tx_axis_fifo_tvalid => tx_axis_fifo_tvalid, tx_axis_fifo_tready => tx_axis_fifo_tready, tx_axis_fifo_tlast => tx_axis_fifo_tlast, -- MAC Control Interface -------------------------- pause_req => pause_req, pause_val => pause_val, -- GMII Interface ------------------- gmii_txd => gmii_txd, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_tx_clk => gmii_tx_clk, gmii_rxd => gmii_rxd, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rx_clk => gmii_rx_clk, mii_tx_clk => mii_tx_clk, -- MDIO Interface ------------------- mdio => mdio, mdc => mdc, -- AXI-Lite Interface ----------------- s_axi_aclk => s_axi_aclk, s_axi_resetn => s_axi_resetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); ------------------------------------------------------------------------------ -- Instantiate the address swapping module and simple pattern generator ------------------------------------------------------------------------------ basic_pat_gen_inst : tri_mode_ethernet_mac_0_basic_pat_gen port map ( axi_tclk => tx_fifo_clock, axi_tresetn => tx_fifo_resetn, check_resetn => chk_resetn, enable_pat_gen => gen_tx_data, enable_pat_chk => chk_tx_data, enable_address_swap => enable_address_swap, speed => mac_speed, rx_axis_tdata => rx_axis_fifo_tdata, rx_axis_tvalid => rx_axis_fifo_tvalid, rx_axis_tlast => rx_axis_fifo_tlast, rx_axis_tuser => '0', rx_axis_tready => rx_axis_fifo_tready, tx_axis_tdata => tx_axis_fifo_tdata, tx_axis_tvalid => tx_axis_fifo_tvalid, tx_axis_tlast => tx_axis_fifo_tlast, tx_axis_tready => tx_axis_fifo_tready, frame_error => int_frame_error, activity_flash => int_activity_flash ); end wrapper;
library verilog; use verilog.vl_types.all; entity comparator_counter is port( iCLOCK : in vl_logic; inRESET : in vl_logic; iMTIMER_WORKING : in vl_logic; iMTIMER_COUNT : in vl_logic_vector(63 downto 0); iCONF_WRITE : in vl_logic; iCONF_ENA : in vl_logic; iCONF_IRQENA : in vl_logic; iCONF_64MODE : in vl_logic; iCONF_PERIODIC : in vl_logic; iCOUNT_WRITE : in vl_logic; inCOUNT_DQM : in vl_logic_vector(1 downto 0); iCOUNT_COUNTER : in vl_logic_vector(63 downto 0); oIRQ : out vl_logic ); end comparator_counter;
---------------------------------------------------------------------------------- -- Company: UOM -- Engineer: Gihan Karunarathne -- -- Create Date: 13:42:15 08/21/2013 -- Design Name: -- Module Name: Variable_Logic_fn - Behavioral -- Project Name: Tutorial I ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Variable_Logic_fn is port( input: in STD_LOGIC_VECTOR ( 2 downto 0); D: in STD_LOGIC; Z: out STD_LOGIC ); end Variable_Logic_fn; architecture Behavioral of Variable_Logic_fn is begin Z <= '0' when input="000" else D when input="001" else '1' when input="010" else '0' when input="011" else not D when input="100" else '0' when input="101" else '0' when input="110" else '0' when input="111"; end Behavioral;
------------------------------------------------------------------------------- -- Title : Testbench for design "input_capture" ------------------------------------------------------------------------------- -- Author : Fabian Greif <fabian@kleinvieh> -- Company : Roboterclub Aachen e.V. ------------------------------------------------------------------------------- -- Description: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.input_capture_pkg.all; ------------------------------------------------------------------------------- entity input_capture_tb is end input_capture_tb; ------------------------------------------------------------------------------- architecture tb of input_capture_tb is -- component ports signal value : std_logic_vector(15 downto 0); signal step : std_logic := '0'; signal dir : std_logic := '0'; signal clk_en : std_logic := '1'; signal clk : std_logic := '0'; begin -- component instantiation input_capture_1 : input_capture port map ( value_p => value, step_p => step, dir_p => dir, clk_en_p => clk_en, clk => clk); -- clock generation clk <= not clk after 10 NS; waveform : process begin wait for 400 NS; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 400 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 200 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '1'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '1'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 1 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 2 MS; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 20 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; end process waveform; end tb;
------------------------------------------------------------------------------- -- Title : Testbench for design "input_capture" ------------------------------------------------------------------------------- -- Author : Fabian Greif <fabian@kleinvieh> -- Company : Roboterclub Aachen e.V. ------------------------------------------------------------------------------- -- Description: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.input_capture_pkg.all; ------------------------------------------------------------------------------- entity input_capture_tb is end input_capture_tb; ------------------------------------------------------------------------------- architecture tb of input_capture_tb is -- component ports signal value : std_logic_vector(15 downto 0); signal step : std_logic := '0'; signal dir : std_logic := '0'; signal clk_en : std_logic := '1'; signal clk : std_logic := '0'; begin -- component instantiation input_capture_1 : input_capture port map ( value_p => value, step_p => step, dir_p => dir, clk_en_p => clk_en, clk => clk); -- clock generation clk <= not clk after 10 NS; waveform : process begin wait for 400 NS; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 400 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 200 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '1'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '1'; wait until rising_edge(clk); step <= '0'; wait for 50 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 1 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 2 MS; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; wait for 20 US; wait until rising_edge(clk); step <= '1'; dir <= '0'; wait until rising_edge(clk); step <= '0'; end process waveform; end tb;
-- Accellera Standard V2.3 Open Verification Library (OVL). -- Accellera Copyright (c) 2008. All rights reserved. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.std_ovl.all; use work.std_ovl_procs.all; architecture rtl of ovl_zero_one_hot is constant assert_name : string := "OVL_ZERO_ONE_HOT"; constant path : string := rtl'path_name; constant all_ones : std_logic_vector(width - 1 downto 0) := (others => '1'); constant all_zeros : std_logic_vector(width - 1 downto 0) := (others => '0'); constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default); constant cover_sanity : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_SANITY); constant cover_corner : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_CORNER); signal reset_n : std_logic; signal clk : std_logic; signal fatal_sig : std_logic; signal test_expr_x01 : std_logic_vector(width - 1 downto 0); signal prev_test_expr : std_logic_vector(width - 1 downto 0); signal one_hots_checked : std_logic_vector(width - 1 downto 0); signal prev_one_hots_checked : std_logic_vector(width - 1 downto 0); shared variable error_count : natural; shared variable cover_count : natural; function check_one_hot (v : std_logic_vector) return boolean is variable v_1 : std_logic_vector((v'length - 1) downto 0); begin case ovl_is_x(v) is when false => v_1 := std_logic_vector(unsigned(v) - 1); when others => v_1 := (others => '0'); end case; if ((v and v_1) = all_zeros) then return true; else return false; end if; end function check_one_hot; begin test_expr_x01 <= to_x01(test_expr); ------------------------------------------------------------------------------ -- Gating logic -- ------------------------------------------------------------------------------ reset_gating : entity work.std_ovl_reset_gating generic map (reset_polarity => reset_polarity, gating_type => gating_type, controls => controls) port map (reset => reset, enable => enable, reset_n => reset_n); clock_gating : entity work.std_ovl_clock_gating generic map (clock_edge => clock_edge, gating_type => gating_type, controls => controls) port map (clock => clock, enable => enable, clk => clk); ------------------------------------------------------------------------------ -- Initialization message -- ------------------------------------------------------------------------------ ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls); end generate ovl_init_msg_gen; ------------------------------------------------------------------------------ -- Assertion - 2-STATE -- ------------------------------------------------------------------------------ ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate ovl_assert_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(0) <= '0'; elsif (not ovl_is_x(test_expr_x01)) then if (not check_one_hot(test_expr_x01)) then fire(0) <= '1'; ovl_error_proc("Test expression contains more than 1 asserted bits", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(0) <= '0'; end if; else fire(0) <= '0'; end if; end if; end process ovl_assert_p; ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig); end generate ovl_assert_on_gen; ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate fire(0) <= '0'; end generate ovl_assert_off_gen; ------------------------------------------------------------------------------ -- Assertion - X-CHECK -- ------------------------------------------------------------------------------ ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate ovl_xcheck_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(1) <= '0'; elsif (ovl_is_x(test_expr_x01)) then fire(1) <= '1'; ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(1) <= '0'; end if; end if; end process ovl_xcheck_p; end generate ovl_xcheck_on_gen; ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate fire(1) <= '0'; end generate ovl_xcheck_off_gen; ------------------------------------------------------------------------------ -- Coverage -- ------------------------------------------------------------------------------ ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and (cover_sanity or cover_corner)) generate ovl_cover_p : process (clk) begin if (rising_edge(clk)) then prev_one_hots_checked <= one_hots_checked; prev_test_expr <= test_expr_x01; if (reset_n = '0') then fire(2) <= '0'; one_hots_checked <= (others => '0'); else fire(2) <= '0'; if ((not ovl_is_x(test_expr_x01)) and check_one_hot(test_expr_x01)) then one_hots_checked <= one_hots_checked or test_expr_x01; end if; if (cover_sanity and (test_expr_x01 /= prev_test_expr) and not ovl_is_x(test_expr_x01) and not ovl_is_x(prev_test_expr)) then ovl_cover_proc("test_expr_change covered", assert_name, path, controls, cover_count); fire(2) <= '1'; end if; if (cover_corner and (prev_test_expr /= all_zeros) and (test_expr_x01 = all_zeros) and not ovl_is_x(prev_test_expr)) then ovl_cover_proc("test_expr_all_zeros covered", assert_name, path, controls, cover_count); fire(2) <= '1'; end if; if (cover_corner and (one_hots_checked /= prev_one_hots_checked) and (one_hots_checked = all_ones) and not ovl_is_x(one_hots_checked) and not ovl_is_x(prev_one_hots_checked)) then ovl_cover_proc("all_one_hots_checked covered", assert_name, path, controls, cover_count); fire(2) <= '1'; end if; end if; end if; end process ovl_cover_p; end generate ovl_cover_on_gen; ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not(cover_sanity) and not(cover_corner))) generate fire(2) <= '0'; end generate ovl_cover_off_gen; end architecture rtl;
-- megafunction wizard: %LPM_ADD_SUB% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_add_sub -- ============================================================ -- File Name: lpm_add_sub1.vhd -- Megafunction Name(s): -- lpm_add_sub -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2006 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_add_sub1 IS PORT ( dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); cout : OUT STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END lpm_add_sub1; ARCHITECTURE SYN OF lpm_add_sub1 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); cout : OUT STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN cout <= sub_wire0; result <= sub_wire1(7 DOWNTO 0); lpm_add_sub_component : lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", lpm_type => "LPM_ADD_SUB", lpm_width => 8 ) PORT MAP ( dataa => dataa, datab => datab, cout => sub_wire0, result => sub_wire1 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: CarryIn NUMERIC "0" -- Retrieval info: PRIVATE: CarryOut NUMERIC "1" -- Retrieval info: PRIVATE: ConstantA NUMERIC "0" -- Retrieval info: PRIVATE: ConstantB NUMERIC "0" -- Retrieval info: PRIVATE: Function NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" -- Retrieval info: PRIVATE: Latency NUMERIC "0" -- Retrieval info: PRIVATE: Overflow NUMERIC "0" -- Retrieval info: PRIVATE: RadixA NUMERIC "10" -- Retrieval info: PRIVATE: RadixB NUMERIC "10" -- Retrieval info: PRIVATE: ValidCtA NUMERIC "0" -- Retrieval info: PRIVATE: ValidCtB NUMERIC "0" -- Retrieval info: PRIVATE: WhichConstant NUMERIC "0" -- Retrieval info: PRIVATE: aclr NUMERIC "0" -- Retrieval info: PRIVATE: clken NUMERIC "0" -- Retrieval info: PRIVATE: nBit NUMERIC "8" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" -- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" -- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout -- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0] -- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0] -- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] -- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 -- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0 -- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0 -- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1_inst.vhd TRUE
------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- -- -- Copyright (c) 2009-2013 Tobias Gubener -- -- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... -- -- Subdesign fAMpIGA by TobiFlex -- -- -- -- This source file is free software: you can redistribute it and/or modify -- -- it under the terms of the GNU General Public License as published -- -- by the Free Software Foundation, either version 3 of the License, or -- -- (at your option) any later version. -- -- -- -- This source file is distributed in the hope that it will be useful, -- -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- -- MERCHANTABILITY or FITNESS For A PARTICULAR PURPOSE. See the -- -- GNU General Public License for more details. -- -- -- -- You should have received a copy of the GNU General Public License -- -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- -- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- optimize Register file -- to do 68010: -- (MOVEC) -- BKPT -- RTD -- MOVES -- -- to do 68020: -- (CALLM) -- (RETM) -- CAS, CAS2 -- CHK2 -- CMP2 -- cpXXX Coprozessor stuff -- TRAPcc -- done 020: -- PACK, UNPK -- Bitfields -- address modes -- long bra -- DIVS.L, DIVU.L -- LINK long -- MULS.L, MULU.L -- extb.l library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.ALL; use work.TG68K_Pack.ALL; entity TG68KdotC_Kernel is generic ( SR_Read : integer := 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0) VBR_Stackframe : integer := 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0) extAddr_Mode : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1) MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL, DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV, BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1) ); port ( clk : in std_logic; nReset : in std_logic; --low active clkena_in : in std_logic := '1'; data_in : in std_logic_vector(15 downto 0); IPL : in std_logic_vector( 2 downto 0) := "111"; IPL_autovector : in std_logic := '1'; -- ACTIVE LOW berr : in std_logic :='0'; -- only 68000 Stackpointer dummy CPU : in std_logic_vector( 1 downto 0) := "00"; -- 00->68000 01->68010 11->68020(only some parts - yet) addr_out : out std_logic_vector(31 downto 0); data_write : out std_logic_vector(15 downto 0); nWr : out std_logic; nUDS : out std_logic; nLDS : out std_logic; busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess nResetOut : out std_logic; FC : out std_logic_vector(2 downto 0); clr_berr : out std_logic; -- for debug skipFetch : out std_logic; regin_out : out std_logic_vector(31 downto 0); CACR_out : out std_logic_vector( 3 downto 0); VBR_out : out std_logic_vector(31 downto 0) ); end TG68KdotC_Kernel; --nBS : std_logic_vector(3 downto 0); -- nBS0 is 31..24 3 is 7..0, active LOW --SIZ : std_logic_vector(1 downto 0); --ACK for 16/32 bit transfer? architecture logic of TG68KdotC_Kernel is signal syncReset : std_logic_vector(3 downto 0); signal Reset : std_logic; signal clkena_lw : std_logic; signal TG68_PC : std_logic_vector(31 downto 0); signal tmp_TG68_PC : std_logic_vector(31 downto 0); signal TG68_PC_add : std_logic_vector(31 downto 0); signal PC_dataa : std_logic_vector(31 downto 0); signal PC_datab : std_logic_vector(31 downto 0); signal memaddr : std_logic_vector(31 downto 0); signal state : std_logic_vector(1 downto 0); signal datatype : std_logic_vector(1 downto 0); signal set_datatype : std_logic_vector(1 downto 0); signal exe_datatype : std_logic_vector(1 downto 0); signal setstate : std_logic_vector(1 downto 0); signal opcode : std_logic_vector(15 downto 0); signal exe_opcode : std_logic_vector(15 downto 0); signal exe_pc : std_logic_vector(31 downto 0); signal last_opc_pc : std_logic_vector(31 downto 0); signal sndOPC : std_logic_vector(15 downto 0); signal last_opc_read : std_logic_vector(15 downto 0); signal reg_QA : std_logic_vector(31 downto 0); signal reg_QB : std_logic_vector(31 downto 0); signal Wwrena : bit; signal Lwrena : bit; signal Bwrena : bit; signal Regwrena_now : bit; signal rf_dest_addr : std_logic_vector(3 downto 0); signal rf_source_addr : std_logic_vector(3 downto 0); signal rf_source_addrd : std_logic_vector(3 downto 0); type regfile_t is ARRAY(0 TO 15) OF std_logic_vector(31 downto 0); signal regfile : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues; signal RDindex_A : integer range 0 TO 15; signal RDindex_B : integer range 0 TO 15; signal WR_AReg : std_logic; signal addr : std_logic_vector(31 downto 0); signal memaddr_reg : std_logic_vector(31 downto 0); signal memaddr_delta : std_logic_vector(31 downto 0); signal use_base : bit; signal ea_data : std_logic_vector(31 downto 0); signal OP1out : std_logic_vector(31 downto 0); signal OP2out : std_logic_vector(31 downto 0); signal OP1outbrief : std_logic_vector(15 downto 0); signal OP1in : std_logic_vector(31 downto 0); signal ALUout : std_logic_vector(31 downto 0); signal data_write_tmp : std_logic_vector(31 downto 0); signal data_write_muxin : std_logic_vector(31 downto 0); signal data_write_mux : std_logic_vector(47 downto 0); signal nextpass : bit; signal setnextpass : bit; signal setdispbyte : bit; signal setdisp : bit; signal regdirectsource : bit; -- checken !!! signal addsub_q : std_logic_vector(31 downto 0); signal briefdata : std_logic_vector(31 downto 0); signal c_out : std_logic_vector(2 downto 0); signal mem_address : std_logic_vector(31 downto 0); signal memaddr_a : std_logic_vector(31 downto 0); signal TG68_PC_brw : bit; signal TG68_PC_word : bit; signal getbrief : bit; signal brief : std_logic_vector(15 downto 0); signal dest_areg : std_logic; signal source_areg : std_logic; signal data_is_source : bit; signal store_in_tmp : bit; signal write_back : bit; signal exec_write_back : bit; signal setstackaddr : bit; signal writePC : bit; signal writePCbig : bit; signal set_writePCbig : bit; signal setopcode : bit; signal decodeOPC : bit; signal execOPC : bit; signal setexecOPC : bit; signal endOPC : bit; signal setendOPC : bit; signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC signal FlagsSR : std_logic_vector(7 downto 0) := (others => '0'); -- T.S..III signal SRin : std_logic_vector(7 downto 0); signal exec_DIRECT : bit; signal exec_tas : std_logic; signal set_exec_tas : std_logic; signal exe_condition : std_logic; signal ea_only : bit; signal source_lowbits : bit; signal source_2ndHbits : bit; signal source_2ndLbits : bit; signal dest_2ndHbits : bit; signal dest_hbits : bit; signal rot_bits : std_logic_vector(1 downto 0); signal set_rot_bits : std_logic_vector(1 downto 0); signal rot_cnt : std_logic_vector(5 downto 0); signal set_rot_cnt : std_logic_vector(5 downto 0); signal movem_actiond : bit; signal movem_regaddr : std_logic_vector(3 downto 0); signal movem_mux : std_logic_vector(3 downto 0); signal movem_presub : bit; signal movem_run : bit; signal ea_calc_b : std_logic_vector(31 downto 0); signal set_direct_data : bit; signal use_direct_data : bit; signal direct_data : bit; signal set_V_Flag : bit; signal set_vectoraddr : bit; signal writeSR : bit; signal trap_berr : bit; signal trap_illegal : bit; signal trap_addr_error : bit; signal trap_priv : bit; signal trap_trace : bit; signal trap_1010 : bit; signal trap_1111 : bit; signal trap_trap : bit; signal trap_trapv : bit; signal trap_interrupt : bit; signal trapmake : bit; signal trapd : bit; signal trap_SR : std_logic_vector(7 downto 0); signal make_trace : std_logic; signal make_berr : std_logic; signal set_stop : bit; signal stop : bit; signal trap_vector : std_logic_vector(31 downto 0); signal trap_vector_vbr : std_logic_vector(31 downto 0); signal USP : std_logic_vector(31 downto 0); signal illegal_write_mode : bit; signal illegal_read_mode : bit; signal illegal_byteaddr : bit; signal IPL_nr : std_logic_vector(2 downto 0); signal rIPL_nr : std_logic_vector(2 downto 0); signal IPL_vec : std_logic_vector(7 downto 0); signal interrupt : bit; signal setinterrupt : bit; signal SVmode : std_logic; signal preSVmode : std_logic; signal Suppress_Base : bit; signal set_Suppress_Base : bit; signal set_Z_error : bit; signal Z_error : bit; signal ea_build_now : bit; signal build_logical : bit; signal build_bcd : bit; signal data_read : std_logic_vector(31 downto 0); signal bf_ext_in : std_logic_vector(7 downto 0); signal bf_ext_out : std_logic_vector(7 downto 0); signal byte : bit; signal long_start : bit; signal long_start_alu : bit; signal non_aligned : std_logic; signal long_done : bit; signal memmask : std_logic_vector(5 downto 0); signal set_memmask : std_logic_vector(5 downto 0); signal memread : std_logic_vector(3 downto 0); signal wbmemmask : std_logic_vector(5 downto 0); signal memmaskmux : std_logic_vector(5 downto 0); signal oddout : std_logic; signal set_oddout : std_logic; signal PCbase : std_logic; signal set_PCbase : std_logic; signal last_data_read : std_logic_vector(31 downto 0); signal last_data_in : std_logic_vector(31 downto 0); signal bf_offset : std_logic_vector(31 downto 0); signal bf_offset_l : std_logic_vector(4 downto 0); signal bf_loffset : std_logic_vector(4 downto 0); signal bf_width : std_logic_vector(4 downto 0); signal bf_bhits : std_logic_vector(5 downto 0); signal alu_bf_width : std_logic_vector(4 downto 0); signal alu_bf_offset : std_logic_vector(31 downto 0); signal alu_bf_loffset : std_logic_vector(4 downto 0); signal movec_data : std_logic_vector(31 downto 0); signal VBR : std_logic_vector(31 downto 0); signal CACR : std_logic_vector(3 downto 0); signal DFC : std_logic_vector(2 downto 0); signal SFC : std_logic_vector(2 downto 0); signal set : bit_vector(lastOpcBit downto 0); signal set_exec : bit_vector(lastOpcBit downto 0); signal exec : bit_vector(lastOpcBit downto 0); signal exec_d : rTG68K_opc; signal micro_state : micro_states; signal next_micro_state : micro_states; signal regin : std_logic_vector(31 downto 0); begin ALU : TG68K_ALU generic map( MUL_Mode => MUL_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL, DIV_Mode => DIV_Mode --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV, ) port map( clk => clk, --: in std_logic; Reset => Reset, --: in std_logic; clkena_lw => clkena_lw, --: in std_logic:='1'; execOPC => execOPC, --: in bit; exe_condition => exe_condition, --: in std_logic; exec_tas => exec_tas, --: in std_logic; long_start => long_start_alu, --: in bit; non_aligned => non_aligned, movem_presub => movem_presub, --: in bit; set_stop => set_stop, --: in bit; Z_error => Z_error, --: in bit; rot_bits => rot_bits, --: in std_logic_vector(1 downto 0); exec => exec, --: in bit_vector(lastOpcBit downto 0); OP1out => OP1out, --: in std_logic_vector(31 downto 0); OP2out => OP2out, --: in std_logic_vector(31 downto 0); reg_QA => reg_QA, --: in std_logic_vector(31 downto 0); reg_QB => reg_QB, --: in std_logic_vector(31 downto 0); opcode => opcode, --: in std_logic_vector(15 downto 0); datatype => datatype, --: in std_logic_vector(1 downto 0); exe_opcode => exe_opcode, --: in std_logic_vector(15 downto 0); exe_datatype => exe_datatype, --: in std_logic_vector(1 downto 0); sndOPC => sndOPC, --: in std_logic_vector(15 downto 0); last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0); data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0); FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0); micro_state => micro_state, --: in micro_states; bf_ext_in => bf_ext_in, bf_ext_out => bf_ext_out, bf_width => alu_bf_width, bf_offset => alu_bf_offset, bf_loffset => alu_bf_loffset, set_V_Flag_out => set_V_Flag, --: buffer bit; Flags_out => Flags, --: buffer std_logic_vector(8 downto 0); c_out_out => c_out, --: buffer std_logic_vector(2 downto 0); addsub_q_out => addsub_q, --: buffer std_logic_vector(31 downto 0); ALUout => ALUout --: buffer std_logic_vector(31 downto 0) ); long_start_alu <= to_bit(not memmaskmux(3)); process (memmaskmux) begin non_aligned <= '0'; if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then non_aligned <= '1'; end if; end process; ----------------------------------------------------------------------------- -- Bus control ----------------------------------------------------------------------------- nWr <= '0' when state = "11" else '1'; busstate <= state; nResetOut <= '0' when exec(opcRESET) = '1' else '1'; -- does shift for byte access. note active low me -- should produce address error on 68000 memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1'; nUDS <= memmaskmux(5); nLDS <= memmaskmux(4); clkena_lw <= '1' when clkena_in = '1' and memmaskmux(3) = '1' else '0'; -- step clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0'; process (clk, nReset) begin if nReset = '0' then syncReset <= "0000"; Reset <= '1'; elsif rising_edge(clk) then if clkena_in = '1' then syncReset <= syncReset(2 downto 0) & '1'; Reset <= not syncReset(3); end if; end if; end process; process (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskmux, memread, memmask, data_read) begin if memmaskmux(4) = '0' then data_read <= last_data_in(15 downto 0) & data_in; else data_read <= last_data_in(23 downto 0) & data_in(15 downto 8); end if; if memread(0) = '1' or (memread(1 downto 0) = "10" and memmaskmux(4) = '1') then data_read(31 downto 16) <= (others => data_read(15)); end if; if rising_edge(clk) then if clkena_lw = '1' and state = "10" then if memmaskmux(4) = '0' then bf_ext_in <= last_data_in(23 downto 16); else bf_ext_in <= last_data_in(31 downto 24); end if; end if; if Reset = '1' then last_data_read <= (others => '0'); elsif clkena_in = '1' then if state = "00" or exec(update_ld) = '1' then last_data_read <= data_read; if state(1) = '0' and memmask(1) = '0' then last_data_read(31 downto 16) <= last_opc_read; elsif state(1) = '0' or memread(1) = '1' then last_data_read(31 downto 16) <= (others => data_in(15)); end if; end if; last_data_in <= last_data_in(15 downto 0) & data_in(15 downto 0); end if; end if; long_start <= to_bit(not memmask(1)); long_done <= to_bit(not memread(1)); end process; process (byte, long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out, data_write_muxin, memmask, oddout, addr) begin if exec(write_reg) = '1' then data_write_muxin <= reg_QB; -- 32 bits else data_write_muxin <= data_write_tmp; end if; if BitField = 0 then if oddout = addr(0) then data_write_mux <= "XXXXXXXX" & "XXXXXXXX" & data_write_muxin; else data_write_mux <= "XXXXXXXX" & data_write_muxin & "XXXXXXXX"; end if; else if oddout = addr(0) then data_write_mux <= "XXXXXXXX" & bf_ext_out & data_write_muxin; else data_write_mux <= bf_ext_out & data_write_muxin & "XXXXXXXX"; end if; end if; if memmaskmux(1) = '0' then data_write <= data_write_mux(47 downto 32); elsif memmaskmux(3) = '0' then data_write <= data_write_mux(31 downto 16); else data_write <= data_write_mux(15 downto 0); end if; if exec(mem_byte) = '1' then --movep data_write(7 downto 0) <= data_write_tmp(15 downto 8); end if; end process; ----------------------------------------------------------------------------- -- Registerfile ----------------------------------------------------------------------------- process (clk, regfile, RDindex_A, RDindex_B, exec) begin reg_QA <= regfile(RDindex_A); reg_QB <= regfile(RDindex_B); if rising_edge(clk) then if clkena_lw = '1' then rf_source_addrd <= rf_source_addr; WR_AReg <= rf_dest_addr(3); RDindex_A <= conv_integer(rf_dest_addr(3 downto 0)); RDindex_B <= conv_integer(rf_source_addr(3 downto 0)); if Wwrena = '1' then regfile(RDindex_A) <= regin; end if; if exec(to_USP) = '1' then USP <= reg_QA; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- Write Reg ----------------------------------------------------------------------------- process (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data) begin regin <= ALUout; if exec(save_memaddr) = '1' then -- only used for movem regin <= memaddr; elsif exec(get_ea_now) = '1' and ea_only = '1' then regin <= memaddr_a; elsif exec(from_USP) = '1' then regin <= USP; elsif exec(movec_rd) = '1' then regin <= movec_data; end if; if Bwrena = '1' then regin(15 downto 8) <= reg_QA(15 downto 8); end if; if Lwrena = '0' then regin(31 downto 16) <= reg_QA(31 downto 16); end if; Bwrena <= '0'; Wwrena <= '0'; Lwrena <= '0'; if exec(presub) = '1' or exec(postadd) = '1' or exec(changeMode) = '1' then -- -(An)+ Wwrena <= '1'; Lwrena <= '1'; elsif Regwrena_now = '1' then --dbcc Wwrena <= '1'; elsif exec(Regwrena) = '1' then --read (mem) Wwrena <= '1'; case exe_datatype is when "00" => --BYTE Bwrena <= '1'; when "01" => --WorD if WR_AReg = '1' or movem_actiond = '1' then Lwrena <= '1'; end if; when others => --LONG Lwrena <= '1'; end case; end if; end process; ----------------------------------------------------------------------------- -- set dest regaddr ----------------------------------------------------------------------------- process (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits) begin if exec(movem_action) = '1' then rf_dest_addr <= rf_source_addrd; elsif set(briefext) = '1' then rf_dest_addr <= brief(15 downto 12); elsif set(get_bfoffset) = '1' then rf_dest_addr <= sndOPC(9 downto 6); elsif dest_2ndHbits = '1' then rf_dest_addr <= sndOPC(15 downto 12); elsif set(write_reminder) = '1' then rf_dest_addr <= sndOPC(3 downto 0); elsif setstackaddr = '1' then rf_dest_addr <= "1111"; elsif dest_hbits = '1' then rf_dest_addr <= dest_areg & opcode(11 downto 9); else if opcode(5 downto 3) = "000" or data_is_source = '1' then rf_dest_addr <= dest_areg & opcode(2 downto 0); else rf_dest_addr <= '1' & opcode(2 downto 0); end if; end if; end process; ----------------------------------------------------------------------------- -- set source regaddr ----------------------------------------------------------------------------- process (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits) begin if exec(movem_action) = '1' or set(movem_action) = '1' then if movem_presub = '1' then rf_source_addr <= movem_regaddr Xor "1111"; else rf_source_addr <= movem_regaddr; end if; elsif source_2ndLbits = '1' then rf_source_addr <= sndOPC(3 downto 0); elsif source_2ndHbits = '1' then rf_source_addr <= sndOPC(15 downto 12); elsif source_lowbits = '1' then rf_source_addr <= source_areg & opcode(2 downto 0); elsif exec(linksp) = '1' then rf_source_addr <= "1111"; else rf_source_addr <= source_areg & opcode(11 downto 9); end if; end process; ----------------------------------------------------------------------------- -- set OP1out ----------------------------------------------------------------------------- process (reg_QA, store_in_tmp, ea_data, long_start, addr, exec, memmaskmux) begin OP1out <= reg_QA; if exec(OP1out_zero) = '1' then OP1out <= (others => '0'); elsif exec(ea_data_OP1) = '1' and store_in_tmp = '1' then OP1out <= ea_data; elsif exec(opcPACK) = '1' then OP1out <= data_write_tmp; elsif exec(movem_action) = '1' or memmaskmux(3) = '0' or exec(OP1addr) = '1' then OP1out <= addr; end if; end process; ----------------------------------------------------------------------------- -- set OP2out ----------------------------------------------------------------------------- process ( OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data, store_in_tmp, data_write_tmp, ea_data) begin OP2out(15 downto 0) <= reg_QB(15 downto 0); OP2out(31 downto 16) <= (others => OP2out(15)); if exec(OP2out_one) = '1' then OP2out(15 downto 0) <= "1111111111111111"; elsif exec(opcEXT) = '1' then if exe_opcode(6) = '0' or exe_opcode(8) = '1' then --ext.w OP2out(15 downto 8) <= (others => OP2out(7)); end if; elsif (use_direct_data = '1' and exec(opcPACK) = '0') or (exec(exg) = '1' and execOPC = '1') or exec(get_bfoffset) = '1' then OP2out <= data_write_tmp; elsif (exec(ea_data_OP1) = '0' and store_in_tmp = '1') or exec(ea_data_OP2) = '1' then OP2out <= ea_data; elsif exec(opcMOVEQ) = '1' then OP2out(7 downto 0) <= exe_opcode(7 downto 0); OP2out(15 downto 8) <= (others => exe_opcode(7)); elsif exec(opcADDQ) = '1' then OP2out(2 downto 0) <= exe_opcode(11 downto 9); if exe_opcode(11 downto 9) = "000" then OP2out(3) <= '1'; else OP2out(3) <= '0'; end if; OP2out(15 downto 4) <= (others => '0'); elsif exe_datatype = "10" then OP2out(31 downto 16) <= reg_QB(31 downto 16); end if; end process; ----------------------------------------------------------------------------- -- handle EA_data, data_write ----------------------------------------------------------------------------- process (clk) begin if rising_edge(clk) then if Reset = '1' then store_in_tmp <= '0'; exec_write_back <= '0'; direct_data <= '0'; use_direct_data <= '0'; Z_error <= '0'; elsif clkena_lw = '1' then direct_data <= '0'; if state = "11" then exec_write_back <= '0'; elsif setstate = "10" and write_back = '1' then exec_write_back <= '1'; end if; if set_direct_data = '1' then direct_data <= '1'; if set_exec(opcPACK) = '1' then use_direct_data <= '0'; else use_direct_data <= '1'; end if; elsif endOPC = '1' then use_direct_data <= '0'; end if; exec_DIRECT <= set_exec(opcMOVE); if endOPC = '1' then store_in_tmp <= '0'; Z_error <= '0'; else if set_Z_error = '1' then Z_error <= '1'; end if; if set_exec(opcMOVE) = '1' and state = "11" then use_direct_data <= '1'; end if; if state = "10" then store_in_tmp <= '1'; end if; if direct_data = '1' and state = "00" then store_in_tmp <= '1'; end if; end if; if state = "10" then ea_data <= data_read; elsif exec(get_2ndOPC)='1' or set_PCbase='1' THEN --TH cmpi (d16,PC) fix ea_data <= addr; elsif exec(store_ea_data) = '1' or (direct_data = '1' and state = "00") then ea_data <= last_data_read; end if; if writePC = '1' then data_write_tmp <= TG68_PC; elsif exec(writePC_add) = '1' then data_write_tmp <= TG68_PC_add; elsif micro_state=trap00 THEN data_write_tmp <= exe_pc; --TH elsif micro_state = trap0 then -- this is only active for 010+ since in 000 writePC is -- true in state trap0 if trap_trace='1' then -- stack frame format #2 data_write_tmp(15 downto 0) <= "0010" & trap_vector(11 downto 0); --TH else data_write_tmp(15 downto 0) <= "0000" & trap_vector(11 downto 0); end if; elsif exec(hold_dwr) = '1' then data_write_tmp <= data_write_tmp; elsif exec(exg) = '1' then data_write_tmp <= OP1out; elsif exec(get_ea_now) = '1' and ea_only = '1' then -- ist for pea data_write_tmp <= addr; elsif execOPC = '1' or micro_state = pack2 then data_write_tmp <= ALUout; elsif (exec_DIRECT = '1' and state = "10") then data_write_tmp <= data_read; if exec(movepl) = '1' then data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0); end if; elsif exec(movepl) = '1' then data_write_tmp(15 downto 0) <= reg_QB(31 downto 16); elsif direct_data = '1' then data_write_tmp <= last_data_read; elsif writeSR = '1' then data_write_tmp(15 downto 0) <= trap_SR(7 downto 0) & Flags(7 downto 0); else data_write_tmp <= OP2out; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- brief ----------------------------------------------------------------------------- process (brief, OP1out, OP1outbrief, cpu) begin if brief(11) = '1' then OP1outbrief <= OP1out(31 downto 16); else OP1outbrief <= (others => OP1out(15)); end if; briefdata <= OP1outbrief & OP1out(15 downto 0); if extAddr_Mode = 1 or (cpu(1) = '1' and extAddr_Mode = 2) then case brief(10 downto 9) is -- mikej SCALE factor when "00" => briefdata <= OP1outbrief & OP1out(15 downto 0); when "01" => briefdata <= OP1outbrief(14 downto 0) & OP1out(15 downto 0) & '0'; when "10" => briefdata <= OP1outbrief(13 downto 0) & OP1out(15 downto 0) & "00"; when "11" => briefdata <= OP1outbrief(12 downto 0) & OP1out(15 downto 0) & "000"; when others => NULL; end case; end if; end process; ----------------------------------------------------------------------------- -- MEM_IO ----------------------------------------------------------------------------- process (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec, memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu) begin if rising_edge(clk) then if clkena_lw = '1' then trap_vector(31 downto 12) <= (others => '0'); if trap_berr='1' then trap_vector(11 downto 0) <= X"008"; end IF; if trap_addr_error = '1' then trap_vector(11 downto 0) <= X"00C"; end if; if trap_illegal = '1' then trap_vector(11 downto 0) <= X"010"; end if; if z_error = '1' then trap_vector(11 downto 0) <= X"014"; end if; if exec(trap_chk) = '1' then trap_vector(11 downto 0) <= X"018"; end if; if trap_trapv = '1' then trap_vector(11 downto 0) <= X"01C"; end if; if trap_priv = '1' then trap_vector(11 downto 0) <= X"020"; end if; if trap_trace = '1' then trap_vector(11 downto 0) <= X"024"; end if; if trap_1010 = '1' then trap_vector(11 downto 0) <= X"028"; end if; if trap_1111 = '1' then trap_vector(11 downto 0) <= X"02C"; end if; if trap_trap = '1' then trap_vector(11 downto 0) <= x"0" & "10" & opcode(3 downto 0) & "00"; end if; if trap_interrupt = '1' then trap_vector(11 downto 0) <= "00" & IPL_vec & "00"; --TH end if; -- TH TODO: non-autovector IRQs end if; end if; -- if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then trap_vector_vbr <= trap_vector; else trap_vector_vbr <= trap_vector + VBR; end if; memaddr_a(4 downto 0) <= "00000"; memaddr_a(7 downto 5) <= (others => memaddr_a(4)); memaddr_a(15 downto 8) <= (others => memaddr_a(7)); memaddr_a(31 downto 16) <= (others => memaddr_a(15)); if setdisp = '1' then if exec(briefext) = '1' then memaddr_a <= briefdata + memaddr_delta; elsif setdispbyte = '1' then memaddr_a(7 downto 0) <= last_data_read(7 downto 0); else memaddr_a <= last_data_read; end if; elsif set(presub) = '1' then if set(longaktion) = '1' then memaddr_a(4 downto 0) <= "11100"; elsif datatype = "00" and set(use_SP) = '0' then memaddr_a(4 downto 0) <= "11111"; else memaddr_a(4 downto 0) <= "11110"; end if; elsif interrupt = '1' then memaddr_a(4 downto 0) <= '1' & rIPL_nr & '0'; end if; if rising_edge(clk) then if clkena_in = '1' then if exec(get_2ndOPC) = '1' or (state = "10" and memread(0) = '1') then tmp_TG68_PC <= addr; end if; use_base <= '0'; if memmaskmux(3) = '0' then memaddr_delta <= addsub_q; elsif exec(mem_addsub) = '1' then memaddr_delta <= addsub_q; elsif state = "01" and exec_write_back = '1' then memaddr_delta <= tmp_TG68_PC; elsif exec(direct_delta) = '1' then memaddr_delta <= data_read; elsif exec(ea_to_pc) = '1' and setstate = "00" then memaddr_delta <= addr; elsif set(addrlong) = '1' then memaddr_delta <= last_data_read; elsif setstate = "00" then memaddr_delta <= TG68_PC_add; elsif exec(dispouter) = '1' then memaddr_delta <= ea_data + memaddr_a; elsif set_vectoraddr = '1' then memaddr_delta <= trap_vector_vbr; else memaddr_delta <= memaddr_a; if interrupt = '0' and Suppress_Base = '0' then -- if interrupt='0' and Suppress_Base='0' and setstate(1)='1' then use_base <= '1'; end if; end if; -- only used for movem address update --if (long_done = '0' and state(1) = '1') or movem_presub = '0' then if ((memread(0) = '1') and state(1) = '1') or movem_presub = '0' then -- fix for unaligned movem mikej memaddr <= addr; end if; end if; end if; -- if access done, and not aligned, don't increment addr <= memaddr_reg + memaddr_delta; addr_out <= memaddr_reg + memaddr_delta; if use_base = '0' then memaddr_reg <= (others => '0'); else memaddr_reg <= reg_QA; end if; end process; ----------------------------------------------------------------------------- -- PC Calc + fetch opcode ----------------------------------------------------------------------------- PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec, PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC) begin PC_dataa <= TG68_PC; if TG68_PC_brw = '1' then PC_dataa <= tmp_TG68_PC; end if; PC_datab(2 downto 0) <= (others => '0'); PC_datab(3) <= PC_datab(2); PC_datab( 7 downto 4) <= (others => PC_datab(3)); PC_datab(15 downto 8) <= (others => PC_datab(7)); PC_datab(31 downto 16) <= (others => PC_datab(15)); if interrupt = '1' then PC_datab(2 downto 1) <= "11"; end if; if exec(writePC_add) = '1' then if writePCbig = '1' then PC_datab(3) <= '1'; PC_datab(1) <= '1'; else PC_datab(2) <= '1'; end if; if trap_trap = '1' or trap_trapv = '1' or exec(trap_chk) = '1' or Z_error = '1' then PC_datab(1) <= '1'; end if; elsif state = "00" then PC_datab(1) <= '1'; end if; if TG68_PC_brw = '1' then if TG68_PC_word = '1' then PC_datab <= last_data_read; else PC_datab(7 downto 0) <= opcode(7 downto 0); end if; end if; TG68_PC_add <= PC_dataa + PC_datab; setopcode <= '0'; setendOPC <= '0'; setinterrupt <= '0'; if setstate = "00" and next_micro_state = idle and setnextpass = '0' and (exec_write_back = '0' or state = "11") and set_rot_cnt = "000001" and set_exec(opcCHK) = '0' then setendOPC <= '1'; if FlagsSR(2 downto 0)<IPL_nr or IPL_nr="111" or make_trace='1' or make_berr='1' then setinterrupt <= '1'; elsif stop = '0' then setopcode <= '1'; end if; end if; setexecOPC <= '0'; if setstate = "00" and next_micro_state = idle and set_direct_data = '0' and (exec_write_back = '0' or state = "10") then setexecOPC <= '1'; end if; IPL_nr <= not IPL; if rising_edge(clk) then if Reset = '1' then state <= "01"; opcode <= X"2E79"; --move $0,a7 trap_interrupt <= '0'; interrupt <= '0'; last_opc_read <= X"4EF9"; --jmp nn.l TG68_PC <= X"00000004"; decodeOPC <= '0'; endOPC <= '0'; TG68_PC_word <= '0'; execOPC <= '0'; stop <= '0'; rot_cnt <= "000001"; byte <= '0'; -- IPL_nr <= "000"; trap_trace <= '0'; trap_berr <= '0'; writePCbig <= '0'; -- recall_last <= '0'; Suppress_Base <= '0'; memmask <= "111111"; else -- IPL_nr <= not IPL; if clkena_in = '1' then -- MIKEJ memmask <= memmask(3 downto 0) & "11"; memread <= memread(1 downto 0) & memmaskmux(5 downto 4); -- if wbmemmask(5 downto 4)="11" then -- wbmemmask <= memmask; -- end if; if exec(directPC) = '1' then TG68_PC <= data_read; elsif exec(ea_to_pc) = '1' then TG68_PC <= addr; elsif (state = "00" or TG68_PC_brw = '1') and stop = '0' then TG68_PC <= TG68_PC_add; end if; end if; if clkena_lw = '1' then interrupt <= setinterrupt; decodeOPC <= setopcode; endOPC <= setendOPC; execOPC <= setexecOPC; exe_datatype <= set_datatype; exe_opcode <= opcode; if trap_berr = '0' then make_berr <= (berr or make_berr); else make_berr <= '0'; end if; stop <= set_stop or (stop and not setinterrupt); if setinterrupt = '1' then make_berr <= '0'; trap_berr <= '0'; if make_trace = '1' then trap_trace <= '1'; elsif make_berr='1' THEN trap_berr <= '1'; else rIPL_nr <= IPL_nr; IPL_vec <= "00011" & IPL_nr; -- TH trap_interrupt <= '1'; end if; end if; if micro_state = trap0 and IPL_autovector = '0' then IPL_vec <= last_data_read(7 downto 0); -- TH end if; if state = "00" then last_opc_read <= data_read(15 downto 0); last_opc_pc <= tg68_pc; end if; if setopcode = '1' then trap_interrupt <= '0'; trap_trace <= '0'; TG68_PC_word <= '0'; trap_berr <= '0'; elsif opcode(7 downto 0) = "00000000" or opcode(7 downto 0) = "11111111" or data_is_source = '1' then TG68_PC_word <= '1'; end if; if exec(get_bfoffset) = '1' then alu_bf_width <= bf_width; alu_bf_loffset <= bf_loffset; alu_bf_offset <= bf_offset; end if; byte <= '0'; memread <= "1111"; FC(1) <= not setstate(1) or (PCbase and not setstate(0)); FC(0) <= setstate(1) and (not PCbase or setstate(0)); if interrupt = '1' then FC(1 downto 0) <= "11"; end if; if (state = "10" and write_back = '1' and setstate /= "10") or set_rot_cnt /= "000001" or (stop = '1' and interrupt = '0') or set_exec(opcCHK) = '1' then state <= "01"; memmask <= "111111"; elsif execOPC = '1' and exec_write_back = '1' then state <= "11"; FC(1 downto 0) <= "01"; memmask <= wbmemmask; if datatype = "00" then byte <= '1'; end if; else state <= setstate; if setstate = "01" then memmask <= "111111"; wbmemmask <= "111111"; elsif exec(get_bfoffset) = '1' then memmask <= set_memmask; wbmemmask <= set_memmask; oddout <= set_oddout; elsif set(longaktion) = '1' then memmask <= "100001"; wbmemmask <= "100001"; oddout <= '0'; elsif set_datatype = "00" and setstate(1) = '1' then memmask <= "101111"; wbmemmask <= "101111"; if set(mem_byte) = '1' then oddout <= '0'; else oddout <= '1'; end if; else memmask <= "100111"; wbmemmask <= "100111"; oddout <= '0'; end if; end if; if decodeOPC = '1' then rot_bits <= set_rot_bits; writePCbig <= '0'; else writePCbig <= set_writePCbig or writePCbig; end if; if decodeOPC = '1' or exec(ld_rot_cnt) = '1' or rot_cnt /= "000001" then rot_cnt <= set_rot_cnt; end if; if setstate(1) = '1' and set_datatype = "00" then byte <= '1'; end if; if set_Suppress_Base = '1' then Suppress_Base <= '1'; elsif setstate(1) = '1' or (ea_only = '1' and set(get_ea_now) = '1') then Suppress_Base <= '0'; end if; if getbrief = '1' then if state(1) = '1' then brief <= last_opc_read(15 downto 0); else brief <= data_read(15 downto 0); end if; end if; if setopcode='1' and berr='0' then if state = "00" then opcode <= data_read(15 downto 0); exe_pc <= tg68_pc; else opcode <= last_opc_read(15 downto 0); exe_pc <= last_opc_pc; end if; nextpass <= '0'; elsif setinterrupt = '1' then opcode(15 downto 12) <= X"7"; --moveq opcode(8 downto 6) <= "001"; --word nextpass <= '0'; else -- if setnextpass='1' or (regdirectsource='1' and state="00") then if setnextpass = '1' or regdirectsource = '1' then nextpass <= '1'; end if; end if; if decodeOPC = '1' or interrupt = '1' then trap_SR <= FlagsSR; end if; end if; end if; end if; if rising_edge(clk) then if Reset = '1' then PCbase <= '1'; elsif clkena_lw = '1' then PCbase <= set_PCbase or PCbase; if setexecOPC = '1' or (state(1) = '1' and movem_run = '0') then PCbase <= '0'; end if; end if; if clkena_lw = '1' then exec <= set; exec_tas <= '0'; exec(subidx) <= set(presub) or set(subidx); if setexecOPC = '1' then exec <= set_exec or set; exec_tas <= set_exec_tas; end if; exec(get_2ndOPC) <= set(get_2ndOPC) or setopcode; end if; end if; end process; ------------------------------------------------------------------------------ --prepare Bitfield Parameters ------------------------------------------------------------------------------ process (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_offset_l, bf_bhits, opcode, setstate) begin -- the ALU needs the full real offset to return the correct result for -- bfffo if sndOPC(11) = '1' then bf_offset <= reg_QA; else bf_offset <= (others => '0'); bf_offset(4 downto 0) <= sndOPC(10 downto 6); end if; -- offset within long word bf_offset_l <= bf_offset(4 downto 0); if sndOPC(5) = '1' then bf_width <= reg_QB(4 downto 0) - 1; else bf_width <= sndOPC(4 downto 0) - 1; end if; bf_bhits <= ('0' & bf_width) + ('0' & bf_offset_l); set_oddout <= not bf_bhits(3); bf_loffset <= 31 - bf_bhits(4 downto 0); if opcode(4 downto 3) /= "00" then -- memory is being read with byte precision, thus offset -- bit 2:0 are only used in the alu bf_loffset(4 downto 3) <= "00"; bf_offset_l(4 downto 3) <= "00"; end if; case bf_bhits(5 downto 3) is when "000" => set_memmask <= "101111"; when "001" => set_memmask <= "100111"; when "010" => set_memmask <= "100011"; when "011" => set_memmask <= "100001"; when others => set_memmask <= "100000"; end case; if setstate = "00" then set_memmask <= "100111"; end if; end process; ------------------------------------------------------------------------------ --SR op ------------------------------------------------------------------------------ process (clk, Reset, FlagsSR, last_data_read, OP2out, exec) begin if exec(andisR) = '1' then SRin <= FlagsSR and last_data_read(15 downto 8); elsif exec(eorisR) = '1' then SRin <= FlagsSR Xor last_data_read(15 downto 8); elsif exec(orisR) = '1' then SRin <= FlagsSR or last_data_read(15 downto 8); else SRin <= OP2out(15 downto 8); end if; if rising_edge(clk) then if Reset = '1' then FlagsSR(5) <= '1'; FlagsSR(2 downto 0) <= "111"; FC(2) <= '1'; SVmode <= '1'; preSVmode <= '1'; make_trace <= '0'; elsif clkena_lw = '1' then if setopcode = '1' then make_trace <= FlagsSR(7); if set(changeMode) = '1' then SVmode <= not SVmode; else SVmode <= preSVmode; end if; end if; if set(changeMode) = '1' then preSVmode <= not preSVmode; FlagsSR(5) <= not preSVmode; FC(2) <= not preSVmode; end if; if micro_state = trap3 then FlagsSR(7) <= '0'; end if; if trap_trace = '1' and state = "10" then make_trace <= '0'; end if; if exec(directSR) = '1' or set_stop = '1' then FlagsSR <= data_read(15 downto 8); end if; if interrupt = '1' and trap_interrupt = '1' then FlagsSR(2 downto 0) <= rIPL_nr; end if; -- if exec(to_CCR)='1' and exec(to_SR)='1' then if exec(to_SR) = '1' then FlagsSR(7 downto 0) <= SRin; --SR FC(2) <= SRin(5); -- end if; elsif exec(update_FC) = '1' then FC(2) <= FlagsSR(5); end if; if interrupt = '1' then FC(2) <= '1'; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- decode opcode ----------------------------------------------------------------------------- process(clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical, build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt, SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype, datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr) begin TG68_PC_brw <= '0'; setstate <= "00"; Regwrena_now <= '0'; movem_presub <= '0'; setnextpass <= '0'; regdirectsource <= '0'; setdisp <= '0'; setdispbyte <= '0'; getbrief <= '0'; dest_areg <= '0'; source_areg <= '0'; data_is_source <= '0'; write_back <= '0'; setstackaddr <= '0'; writePC <= '0'; ea_build_now <= '0'; set_rot_bits <= "XX"; set_rot_cnt <= "000001"; dest_hbits <= '0'; source_lowbits <= '0'; source_2ndHbits <= '0'; source_2ndLbits <= '0'; dest_2ndHbits <= '0'; ea_only <= '0'; set_direct_data <= '0'; set_exec_tas <= '0'; trap_illegal <= '0'; trap_addr_error <= '0'; trap_priv <= '0'; trap_1010 <= '0'; trap_1111 <= '0'; trap_trap <= '0'; trap_trapv <= '0'; trapmake <= '0'; set_vectoraddr <= '0'; writeSR <= '0'; set_stop <= '0'; illegal_write_mode <= '0'; illegal_read_mode <= '0'; illegal_byteaddr <= '0'; set_Z_error <= '0'; next_micro_state <= idle; build_logical <= '0'; build_bcd <= '0'; skipFetch <= make_berr; set_writePCbig <= '0'; -- set_recall_last <= '0'; set_Suppress_Base <= '0'; set_PCbase <= '0'; if rot_cnt /= "000001" then set_rot_cnt <= rot_cnt - 1; end if; set_datatype <= datatype; set <= (others => '0'); set_exec <= (others => '0'); set(update_ld) <= '0'; -- odd_start <= '0'; ------------------------------------------------------------------------------ --Sourcepass ------------------------------------------------------------------------------ case opcode(7 downto 6) is when "00" => datatype <= "00"; --Byte when "01" => datatype <= "01"; --Word when others => datatype <= "10"; --Long end case; if trapmake = '1' and trapd = '0' then next_micro_state <= trap0; if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then set(writePC_add) <= '1'; -- set_datatype <= "10"; end if; if preSVmode = '0' then set(changeMode) <= '1'; end if; setstate <= "01"; end if; if interrupt='1' and trap_berr='1' THEN next_micro_state <= trap0; if preSVmode='0' THEN set(changeMode) <= '1'; end if; setstate <= "01"; end if; if micro_state = int1 or (interrupt = '1' and trap_trace = '1') then if trap_trace='1' AND (VBR_Stackframe=1 or (cpu(0)='1' AND VBR_Stackframe=2)) then next_micro_state <= trap00; --TH else next_micro_state <= trap0; end if; -- if cpu(0)='0' then -- set_datatype <= "10"; -- end if; if preSVmode = '0' then set(changeMode) <= '1'; end if; setstate <= "01"; end if; if setexecOPC = '1' and FlagsSR(5) /= preSVmode then set(changeMode) <= '1'; -- setstate <= "01"; -- next_micro_state <= nop; end if; if interrupt = '1' and trap_interrupt = '1' then -- skipFetch <= '1'; next_micro_state <= int1; set(update_ld) <= '1'; setstate <= "10"; end if; if set(changeMode) = '1' then set(to_USP) <= '1'; set(from_USP) <= '1'; setstackaddr <= '1'; end if; if ea_only = '0' and set(get_ea_now) = '1' then setstate <= "10"; -- set_recall_last <= '1'; -- set(update_ld) <= '0'; end if; if setstate(1) = '1' and set_datatype(1) = '1' then set(longaktion) <= '1'; end if; if (ea_build_now = '1' and decodeOPC = '1') or exec(ea_build) = '1' then case opcode(5 downto 3) is --source when "010" | "011" | "100" => -- -(An)+ set(get_ea_now) <= '1'; setnextpass <= '1'; if opcode(3) = '1' then --(An)+ set(postadd) <= '1'; if opcode(2 downto 0) = "111" then set(use_SP) <= '1'; end if; end if; if opcode(5) = '1' then -- -(An) set(presub) <= '1'; if opcode(2 downto 0) = "111" then set(use_SP) <= '1'; end if; end if; when "101" => --(d16,An) next_micro_state <= ld_dAn1; when "110" => --(d8,An,Xn) next_micro_state <= ld_AnXn1; getbrief <= '1'; when "111" => case opcode(2 downto 0) is when "000" => --(xxxx).w next_micro_state <= ld_nn; when "001" => --(xxxx).l set(longaktion) <= '1'; next_micro_state <= ld_nn; when "010" => --(d16,PC) next_micro_state <= ld_dAn1; set(dispouter) <= '1'; set_Suppress_Base <= '1'; set_PCbase <= '1'; when "011" => --(d8,PC,Xn) next_micro_state <= ld_AnXn1; getbrief <= '1'; set(dispouter) <= '1'; set_Suppress_Base <= '1'; set_PCbase <= '1'; when "100" => --#data setnextpass <= '1'; set_direct_data <= '1'; if datatype = "10" then set(longaktion) <= '1'; end if; when others => NULL; end case; when others => NULL; end case; end if; ------------------------------------------------------------------------------ --prepere opcode ------------------------------------------------------------------------------ case opcode(15 downto 12) is -- 0000 ---------------------------------------------------------------------------- when "0000" => if opcode(8) = '1' and opcode(5 downto 3) = "001" then --movep datatype <= "00"; --Byte set(use_SP) <= '1'; --addr+2 set(no_Flags) <= '1'; if opcode(7) = '0' then --to register set_exec(Regwrena) <= '1'; set_exec(opcMOVE) <= '1'; set(movepl) <= '1'; end if; if decodeOPC = '1' then if opcode(6) = '1' then set(movepl) <= '1'; end if; if opcode(7) = '0' then set_direct_data <= '1'; -- to register end if; next_micro_state <= movep1; end if; if setexecOPC = '1' then dest_hbits <= '1'; end if; else if opcode(8) = '1' or opcode(11 downto 9) = "100" then --Bits set_exec(opcBITS) <= '1'; set_exec(ea_data_OP1) <= '1'; if opcode(7 downto 6) /= "00" then if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; write_back <= '1'; end if; if opcode(5 downto 4) = "00" then datatype <= "10"; --Long else datatype <= "00"; --Byte end if; if opcode(8) = '0' then if decodeOPC = '1' then next_micro_state <= nop; set(get_2ndOPC) <= '1'; set(ea_build) <= '1'; end if; else ea_build_now <= '1'; end if; elsif opcode(11 downto 9) = "111" then --MOVES not in 68000 trap_illegal <= '1'; -- trap_addr_error <= '1'; trapmake <= '1'; else --andi, ...xxxi if opcode(11 downto 9) = "000" then --orI set_exec(opcor) <= '1'; end if; if opcode(11 downto 9) = "001" then --andI set_exec(opcand) <= '1'; end if; if opcode(11 downto 9) = "010" or opcode(11 downto 9) = "011" then --SUBI, ADDI set_exec(opcADD) <= '1'; end if; if opcode(11 downto 9) = "101" then --EorI set_exec(opcEor) <= '1'; end if; if opcode(11 downto 9) = "110" then --CMPI set_exec(opcCMP) <= '1'; end if; if opcode(7) = '0' and opcode(5 downto 0) = "111100" and (set_exec(opcand) or set_exec(opcor) or set_exec(opcEor)) = '1' then --SR if decodeOPC = '1' and SVmode = '0' and opcode(6) = '1' then --SR trap_priv <= '1'; trapmake <= '1'; else set(no_Flags) <= '1'; if decodeOPC = '1' then if opcode(6) = '1' then set(to_SR) <= '1'; end if; set(to_CCR) <= '1'; set(andisR) <= set_exec(opcand); set(eorisR) <= set_exec(opcEor); set(orisR) <= set_exec(opcor); setstate <= "01"; next_micro_state <= nopnop; end if; end if; else if decodeOPC = '1' then next_micro_state <= andi; set(ea_build) <= '1'; set_direct_data <= '1'; if datatype = "10" then set(longaktion) <= '1'; end if; end if; if opcode(5 downto 4) /= "00" then set_exec(ea_data_OP1) <= '1'; end if; if opcode(11 downto 9) /= "110" then --CMPI if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; write_back <= '1'; end if; if opcode(10 downto 9) = "10" then --CMPI, SUBI set(addsub) <= '1'; end if; end if; end if; end if; -- 0001, 0010, 0011 ----------------------------------------------------------------- when "0001" | "0010" | "0011" => --move.b, move.l, move.w set_exec(opcMOVE) <= '1'; ea_build_now <= '1'; if opcode(8 downto 6) = "001" then set(no_Flags) <= '1'; end if; if opcode(5 downto 4) = "00" then --Dn, An if opcode(8 downto 7) = "00" then set_exec(Regwrena) <= '1'; end if; end if; case opcode(13 downto 12) is when "01" => datatype <= "00"; --Byte when "10" => datatype <= "10"; --Long when others => datatype <= "01"; --Word end case; source_lowbits <= '1'; -- Dn=> An=> if opcode(3) = '1' then source_areg <= '1'; end if; if nextpass = '1' or opcode(5 downto 4) = "00" then dest_hbits <= '1'; if opcode(8 downto 6) /= "000" then dest_areg <= '1'; end if; end if; -- if setstate="10" then -- set(update_ld) <= '0'; -- end if; -- if micro_state = idle and (nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1')) then case opcode(8 downto 6) is --destination when "000" | "001" => --Dn,An set_exec(Regwrena) <= '1'; when "010" | "011" | "100" => --destination -(an)+ if opcode(6) = '1' then --(An)+ set(postadd) <= '1'; if opcode(11 downto 9) = "111" then set(use_SP) <= '1'; end if; end if; if opcode(8) = '1' then -- -(An) set(presub) <= '1'; if opcode(11 downto 9) = "111" then set(use_SP) <= '1'; end if; end if; setstate <= "11"; next_micro_state <= nop; if nextpass = '0' then set(write_reg) <= '1'; end if; when "101" => --(d16,An) next_micro_state <= st_dAn1; -- getbrief <= '1'; when "110" => --(d8,An,Xn) next_micro_state <= st_AnXn1; getbrief <= '1'; when "111" => case opcode(11 downto 9) is when "000" => --(xxxx).w next_micro_state <= st_nn; when "001" => --(xxxx).l set(longaktion) <= '1'; next_micro_state <= st_nn; when others => NULL; end case; when others => NULL; end case; end if; ---- 0100 ---------------------------------------------------------------------------- when "0100" => --rts_group if opcode(8) = '1' then --lea if opcode(6) = '1' then --lea if opcode(7) = '1' then source_lowbits <= '1'; -- if opcode(5 downto 3)="000" and opcode(10)='0' then --ext if opcode(5 downto 4) = "00" then --extb.l set_exec(opcEXT) <= '1'; set_exec(opcMOVE) <= '1'; set_exec(Regwrena) <= '1'; -- if opcode(6)='0' then -- datatype <= "01"; --WorD -- end if; else source_areg <= '1'; ea_only <= '1'; set_exec(Regwrena) <= '1'; set_exec(opcMOVE) <= '1'; set(no_Flags) <= '1'; if opcode(5 downto 3) = "010" then --lea (Am),An dest_areg <= '1'; dest_hbits <= '1'; else ea_build_now <= '1'; end if; if set(get_ea_now) = '1' then setstate <= "01"; set_direct_data <= '1'; end if; if setexecOPC = '1' then dest_areg <= '1'; dest_hbits <= '1'; end if; end if; else trap_illegal <= '1'; trapmake <= '1'; end if; else --chk IF opcode(7)='1' AND opcode(5 downto 0) /= "111111" THEN datatype <= "01"; --Word set(trap_chk) <= '1'; if (c_out(1) = '0' or OP1out(15) = '1' or OP2out(15) = '1') and exec(opcCHK) = '1' then trapmake <= '1'; end if; elsif cpu(1) = '1' then --chk long for 68020 datatype <= "10"; --Long set(trap_chk) <= '1'; if (c_out(2) = '1' or OP1out(31) = '1' or OP2out(31) = '1') and exec(opcCHK) = '1' then trapmake <= '1'; end if; else trap_illegal <= '1'; -- chk long for 68020 trapmake <= '1'; end if; if opcode(7) = '1' or cpu(1) = '1' then if (nextpass = '1' or opcode(5 downto 4) = "00") and exec(opcCHK) = '0' and micro_state = idle then set_exec(opcCHK) <= '1'; end if; ea_build_now <= '1'; set(addsub) <= '1'; if setexecOPC = '1' then dest_hbits <= '1'; source_lowbits <= '1'; end if; end if; end if; else case opcode(11 downto 9) is when "000" => if opcode(7 downto 6) = "11" then --move from SR if SR_Read = 0 or (cpu(0) = '0' and SR_Read = 2) or SVmode = '1' then -- if SVmode='1' then ea_build_now <= '1'; set_exec(opcMOVESR) <= '1'; datatype <= "01"; write_back <= '1'; -- 68000 also reads first if cpu(0) = '1' and state = "10" then skipFetch <= '1'; end if; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; else trap_priv <= '1'; trapmake <= '1'; end if; else --negx ea_build_now <= '1'; set_exec(use_XZFlag) <= '1'; write_back <= '1'; set_exec(opcADD) <= '1'; set(addsub) <= '1'; source_lowbits <= '1'; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; if setexecOPC = '1' then set(OP1out_zero) <= '1'; end if; end if; when "001" => if opcode(7 downto 6) = "11" then --move from CCR 68010 if SR_Read = 1 or (cpu(0) = '1' and SR_Read = 2) then ea_build_now <= '1'; set_exec(opcMOVECCR) <= '1'; --datatype <= "00"; -- WRONG, should be WORD zero extended. datatype <= "01"; -- WRONG, should be WORD zero extended. write_back <= '1'; -- 68000 also reads first if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; else trap_illegal <= '1'; trapmake <= '1'; end if; else --clr ea_build_now <= '1'; write_back <= '1'; set_exec(opcand) <= '1'; if cpu(0) = '1' and state = "10" then skipFetch <= '1'; end if; if setexecOPC = '1' then set(OP1out_zero) <= '1'; end if; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; end if; when "010" => ea_build_now <= '1'; if opcode(7 downto 6) = "11" then --move to CCR datatype <= "01"; source_lowbits <= '1'; if (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then set(to_CCR) <= '1'; end if; else --neg write_back <= '1'; set_exec(opcADD) <= '1'; set(addsub) <= '1'; source_lowbits <= '1'; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; if setexecOPC = '1' then set(OP1out_zero) <= '1'; end if; end if; when "011" => --not, move toSR if opcode(7 downto 6) = "11" then --move to SR if SVmode = '1' then ea_build_now <= '1'; datatype <= "01"; source_lowbits <= '1'; if (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then set(to_SR) <= '1'; set(to_CCR) <= '1'; end if; if exec(to_SR) = '1' or (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then setstate <= "01"; end if; else trap_priv <= '1'; trapmake <= '1'; end if; else --not ea_build_now <= '1'; write_back <= '1'; set_exec(opcEor) <= '1'; set_exec(ea_data_OP1) <= '1'; if opcode(5 downto 3) = "000" then set_exec(Regwrena) <= '1'; end if; if setexecOPC = '1' then set(OP2out_one) <= '1'; end if; end if; when "100" | "110" => if opcode(7) = '1' then --movem, ext if opcode(5 downto 3) = "000" and opcode(10) = '0' then --ext source_lowbits <= '1'; set_exec(opcEXT) <= '1'; set_exec(opcMOVE) <= '1'; set_exec(Regwrena) <= '1'; if opcode(6) = '0' then datatype <= "01"; --WorD end if; else --movem -- if opcode(11 downto 7)="10001" or opcode(11 downto 7)="11001" then --MOVEM ea_only <= '1'; set(no_Flags) <= '1'; if opcode(6) = '0' then datatype <= "01"; --Word transfer end if; if (opcode(5 downto 3) = "100" or opcode(5 downto 3) = "011") and state = "01" then -- -(An), (An)+ set_exec(save_memaddr) <= '1'; set_exec(Regwrena) <= '1'; end if; if opcode(5 downto 3) = "100" then -- -(An) movem_presub <= '1'; set(subidx) <= '1'; end if; if state = "10" then set(Regwrena) <= '1'; set(opcMOVE) <= '1'; end if; if decodeOPC = '1' then set(get_2ndOPC) <= '1'; if opcode(5 downto 3) = "010" or opcode(5 downto 3) = "011" or opcode(5 downto 3) = "100" then next_micro_state <= movem1; else next_micro_state <= nop; set(ea_build) <= '1'; end if; end if; if set(get_ea_now) = '1' then if movem_run = '1' then set(movem_action) <= '1'; if opcode(10) = '0' then setstate <= "11"; set(write_reg) <= '1'; else setstate <= "10"; end if; next_micro_state <= movem2; set(mem_addsub) <= '1'; else setstate <= "01"; end if; end if; end if; else if opcode(10) = '1' then --MUL.L, DIV.L 68020 -- if cpu(1)='1' then if (opcode(6) = '1' and (DIV_Mode = 1 or (cpu(1) = '1' and DIV_Mode = 2))) or (opcode(6) = '0' and (MUL_Mode = 1 or (cpu(1) = '1' and MUL_Mode = 2))) then if decodeOPC = '1' then next_micro_state <= nop; set(get_2ndOPC) <= '1'; set(ea_build) <= '1'; end if; if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and exec(ea_build) = '1') then setstate <= "01"; dest_2ndHbits <= '1'; source_2ndLbits <= '1'; if opcode(6) = '1' then next_micro_state <= div1; else next_micro_state <= mul1; set(ld_rot_cnt) <= '1'; end if; end if; if z_error = '0' and set_V_Flag = '0' and set(opcDIVU) = '1' then set(Regwrena) <= '1'; end if; source_lowbits <= '1'; if nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1') then dest_hbits <= '1'; end if; datatype <= "10"; else trap_illegal <= '1'; trapmake <= '1'; end if; else --pea, swap if opcode(6) = '1' then datatype <= "10"; if opcode(5 downto 3) = "000" then --swap set_exec(opcSWAP) <= '1'; set_exec(Regwrena) <= '1'; elsif opcode(5 downto 3) = "001" then --bkpt else --pea ea_only <= '1'; ea_build_now <= '1'; if nextpass = '1' and micro_state = idle then set(presub) <= '1'; setstackaddr <= '1'; setstate <= "11"; next_micro_state <= nop; end if; if set(get_ea_now) = '1' then setstate <= "01"; end if; end if; else if opcode(5 downto 3) = "001" then --link.l datatype <= "10"; set_exec(opcADD) <= '1'; --for displacement set_exec(Regwrena) <= '1'; set(no_Flags) <= '1'; if decodeOPC = '1' then set(linksp) <= '1'; set(longaktion) <= '1'; next_micro_state <= link1; set(presub) <= '1'; setstackaddr <= '1'; set(mem_addsub) <= '1'; source_lowbits <= '1'; source_areg <= '1'; set(store_ea_data) <= '1'; end if; else --nbcd ea_build_now <= '1'; set_exec(use_XZFlag) <= '1'; write_back <= '1'; set_exec(opcADD) <= '1'; set_exec(opcSBCD) <= '1'; source_lowbits <= '1'; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; if setexecOPC = '1' then set(OP1out_zero) <= '1'; end if; end if; end if; end if; end if; -- when "101" => --tst, tas 4aFC - illegal if opcode(7 downto 2) = "111111" then --illegal trap_illegal <= '1'; trapmake <= '1'; else ea_build_now <= '1'; if setexecOPC = '1' then source_lowbits <= '1'; if opcode(3) = '1' then --MC68020... source_areg <= '1'; end if; end if; set_exec(opcMOVE) <= '1'; if opcode(7 downto 6) = "11" then --tas set_exec_tas <= '1'; write_back <= '1'; datatype <= "00"; --Byte if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; end if; end if; ---- when "110"=> when "111" => --4EXX -- -- ea_only <= '1'; -- ea_build_now <= '1'; -- if nextpass='1' and micro_state=idle then -- set(presub) <= '1'; -- setstackaddr <='1'; -- set(mem_addsub) <= '1'; -- setstate <="11"; -- next_micro_state <= nop; -- end if; -- if set(get_ea_now)='1' then -- setstate <="01"; -- end if; -- if opcode(7) = '1' then --jsr, jmp datatype <= "10"; ea_only <= '1'; ea_build_now <= '1'; if exec(ea_to_pc) = '1' then next_micro_state <= nop; end if; if nextpass = '1' and micro_state = idle and opcode(6) = '0' then set(presub) <= '1'; setstackaddr <= '1'; setstate <= "11"; next_micro_state <= nopnop; end if; -- achtung buggefahr if micro_state = ld_AnXn1 and brief(8) = '0' then --JMP/JSR n(Ax,Dn) skipFetch <= '1'; end if; if state = "00" then writePC <= '1'; end if; set(hold_dwr) <= '1'; if set(get_ea_now) = '1' then --jsr if exec(longaktion) = '0' or long_done = '1' then skipFetch <= '1'; end if; setstate <= "01"; set(ea_to_pc) <= '1'; end if; else -- case opcode(6 downto 0) is when "1000000" | "1000001" | "1000010" | "1000011" | "1000100" | "1000101" | "1000110" | "1000111" | --trap "1001000" | "1001001" | "1001010" | "1001011" | "1001100" | "1001101" | "1001110" | "1001111" => --trap trap_trap <= '1'; trapmake <= '1'; when "1010000" | "1010001" | "1010010" | "1010011" | "1010100" | "1010101" | "1010110" | "1010111" => --link datatype <= "10"; set_exec(opcADD) <= '1'; --for displacement set_exec(Regwrena) <= '1'; set(no_Flags) <= '1'; if decodeOPC = '1' then next_micro_state <= link1; set(presub) <= '1'; setstackaddr <= '1'; set(mem_addsub) <= '1'; source_lowbits <= '1'; source_areg <= '1'; set(store_ea_data) <= '1'; end if; when "1011000" | "1011001" | "1011010" | "1011011" | "1011100" | "1011101" | "1011110" | "1011111" => --unlink datatype <= "10"; set_exec(Regwrena) <= '1'; set_exec(opcMOVE) <= '1'; set(no_Flags) <= '1'; if decodeOPC = '1' then setstate <= "01"; next_micro_state <= unlink1; set(opcMOVE) <= '1'; set(Regwrena) <= '1'; setstackaddr <= '1'; source_lowbits <= '1'; source_areg <= '1'; end if; when "1100000" | "1100001" | "1100010" | "1100011" | "1100100" | "1100101" | "1100110" | "1100111" => --move An,USP if SVmode = '1' then -- set(no_Flags) <= '1'; set(to_USP) <= '1'; source_lowbits <= '1'; source_areg <= '1'; datatype <= "10"; else trap_priv <= '1'; trapmake <= '1'; end if; when "1101000" | "1101001" | "1101010" | "1101011" | "1101100" | "1101101" | "1101110" | "1101111" => --move USP,An if SVmode = '1' then -- set(no_Flags) <= '1'; set(from_USP) <= '1'; datatype <= "10"; set_exec(Regwrena) <= '1'; else trap_priv <= '1'; trapmake <= '1'; end if; when "1110000" => --reset if SVmode = '0' then trap_priv <= '1'; trapmake <= '1'; else set(opcRESET) <= '1'; if decodeOPC = '1' then set(ld_rot_cnt) <= '1'; set_rot_cnt <= "000000"; end if; end if; when "1110001" => --nop when "1110010" => --stop if SVmode = '0' then trap_priv <= '1'; trapmake <= '1'; else if decodeOPC = '1' then setnextpass <= '1'; set_stop <= '1'; end if; if stop = '1' then skipFetch <= '1'; end if; end if; when "1110011" | "1110111" => --rte/rtr if SVmode = '1' or opcode(2) = '1' then if decodeOPC = '1' then setstate <= "10"; set(postadd) <= '1'; setstackaddr <= '1'; if opcode(2) = '1' then set(directCCR) <= '1'; else set(directSR) <= '1'; end if; next_micro_state <= rte1; end if; else trap_priv <= '1'; trapmake <= '1'; end if; when "1110101" => --rts datatype <= "10"; if decodeOPC = '1' then setstate <= "10"; set(postadd) <= '1'; setstackaddr <= '1'; set(direct_delta) <= '1'; set(directPC) <= '1'; next_micro_state <= nopnop; end if; when "1110110" => --trapv if decodeOPC = '1' then setstate <= "01"; end if; if Flags(1) = '1' and state = "01" then trap_trapv <= '1'; trapmake <= '1'; end if; when "1111010" | "1111011" => --movec if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then trap_illegal <= '1'; trapmake <= '1'; elsif SVmode = '0' then trap_priv <= '1'; trapmake <= '1'; else datatype <= "10"; --Long if last_data_read(11 downto 0) = X"800" then set(from_USP) <= '1'; if opcode(0) = '1' then set(to_USP) <= '1'; end if; end if; if opcode(0) = '0' then set_exec(movec_rd) <= '1'; else set_exec(movec_wr) <= '1'; end if; if decodeOPC = '1' then next_micro_state <= movec1; getbrief <= '1'; end if; end if; when others => trap_illegal <= '1'; trapmake <= '1'; end case; end if; when others => NULL; end case; end if; -- ---- 0101 ---------------------------------------------------------------------------- when "0101" => --subq, addq if opcode(7 downto 6) = "11" then --dbcc if opcode(5 downto 3) = "001" then --dbcc if decodeOPC = '1' then next_micro_state <= dbcc1; set(OP2out_one) <= '1'; data_is_source <= '1'; end if; else --Scc datatype <= "00"; --Byte ea_build_now <= '1'; write_back <= '1'; set_exec(opcScc) <= '1'; if cpu(0) = '1' and state = "10" then skipFetch <= '1'; end if; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; end if; else --addq, subq ea_build_now <= '1'; if opcode(5 downto 3) = "001" then set(no_Flags) <= '1'; end if; if opcode(8) = '1' then set(addsub) <= '1'; end if; write_back <= '1'; set_exec(opcADDQ) <= '1'; set_exec(opcADD) <= '1'; set_exec(ea_data_OP1) <= '1'; if opcode(5 downto 4) = "00" then set_exec(Regwrena) <= '1'; end if; end if; -- ---- 0110 ---------------------------------------------------------------------------- when "0110" => --bra,bsr,bcc datatype <= "10"; if micro_state = idle then if opcode(11 downto 8) = "0001" then --bsr set(presub) <= '1'; setstackaddr <= '1'; if opcode(7 downto 0) = "11111111" then next_micro_state <= bsr2; set(longaktion) <= '1'; elsif opcode(7 downto 0) = "00000000" then next_micro_state <= bsr2; else next_micro_state <= bsr1; setstate <= "11"; writePC <= '1'; end if; else --bra if opcode(7 downto 0) = "11111111" then next_micro_state <= bra1; set(longaktion) <= '1'; elsif opcode(7 downto 0) = "00000000" then next_micro_state <= bra1; else setstate <= "01"; next_micro_state <= bra1; end if; end if; end if; -- 0111 ---------------------------------------------------------------------------- when "0111" => --moveq -- if opcode(8)='0' then -- Cloanto's Amiga Forver ROMs have mangled movq instructions with a 1 here... if trap_interrupt = '0' and trap_trace = '0' then datatype <= "10"; --Long set_exec(Regwrena) <= '1'; set_exec(opcMOVEQ) <= '1'; set_exec(opcMOVE) <= '1'; dest_hbits <= '1'; end if; -- else -- trap_illegal <= '1'; -- trapmake <= '1'; -- end if; ---- 1000 ---------------------------------------------------------------------------- when "1000" => --or if opcode(7 downto 6) = "11" then --divu, divs if DIV_Mode /= 3 then if opcode(5 downto 4) = "00" then --Dn, An regdirectsource <= '1'; end if; if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then setstate <= "01"; next_micro_state <= div1; end if; ea_build_now <= '1'; if z_error = '0' and set_V_Flag = '0' then set_exec(Regwrena) <= '1'; end if; source_lowbits <= '1'; if nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1') then dest_hbits <= '1'; end if; datatype <= "01"; else trap_illegal <= '1'; trapmake <= '1'; end if; elsif opcode(8) = '1' and opcode(5 downto 4) = "00" then --sbcd, pack , unpack if opcode(7 downto 6) = "00" then --sbcd build_bcd <= '1'; set_exec(opcADD) <= '1'; set_exec(opcSBCD) <= '1'; elsif cpu(1) = '1' and (opcode(7 downto 6) = "01" or opcode(7 downto 6) = "10") then --pack, unpack datatype <= "01"; --Word set_exec(opcPACK) <= '1'; set(no_Flags) <= '1'; -- this command modifies no flags -- immediate value is kept in op1 -- source value is in op2 if opcode(3) = '0' then -- R/M bit = 0 -> Dy->Dy, 1 -(Ax),-(Ay) dest_hbits <= '1'; -- dest register is encoded in bits 9-11 source_lowbits <= '1'; -- source register is encoded in bits 0-2 set_exec(Regwrena) <= '1'; -- write result into register set_exec(ea_data_OP1) <= '1'; -- immediate value goes into op2 set(hold_dwr) <= '1'; -- pack writes a byte only if opcode(7 downto 6) = "01" then datatype <= "00"; --Byte else datatype <= "01"; --Word end if; if decodeOPC = '1' then next_micro_state <= nop; set_direct_data <= '1'; end if; else set_exec(ea_data_OP1) <= '1'; source_lowbits <= '1'; -- source register is encoded in bits 0-2 if decodeOPC = '1' then -- first step: read source value if opcode(7 downto 6) = "10" then -- UNPK reads a byte datatype <= "00"; -- Byte end if; set_direct_data <= '1'; setstate <= "10"; set(update_ld) <= '1'; set(presub) <= '1'; next_micro_state <= pack1; dest_areg <= '1'; --??? end if; end if; else trap_illegal <= '1'; trapmake <= '1'; end if; else --or set_exec(opcor) <= '1'; build_logical <= '1'; end if; ---- 1001, 1101 ----------------------------------------------------------------------- when "1001" | "1101" => --sub, add set_exec(opcADD) <= '1'; ea_build_now <= '1'; if opcode(14) = '0' then set(addsub) <= '1'; end if; if opcode(7 downto 6) = "11" then -- --adda, suba if opcode(8) = '0' then --adda.w, suba.w datatype <= "01"; --Word end if; set_exec(Regwrena) <= '1'; source_lowbits <= '1'; if opcode(3) = '1' then source_areg <= '1'; end if; set(no_Flags) <= '1'; if setexecOPC = '1' then dest_areg <= '1'; dest_hbits <= '1'; end if; else if opcode(8) = '1' and opcode(5 downto 4) = "00" then --addx, subx build_bcd <= '1'; else --sub, add build_logical <= '1'; end if; end if; -- ---- 1010 ---------------------------------------------------------------------------- when "1010" => --Trap 1010 trap_1010 <= '1'; trapmake <= '1'; ---- 1011 ---------------------------------------------------------------------------- when "1011" => --eor, cmp ea_build_now <= '1'; if opcode(7 downto 6) = "11" then --CMPA if opcode(8) = '0' then --cmpa.w datatype <= "01"; --Word set_exec(opcCPMAW) <= '1'; end if; set_exec(opcCMP) <= '1'; if setexecOPC = '1' then source_lowbits <= '1'; if opcode(3) = '1' then source_areg <= '1'; end if; dest_areg <= '1'; dest_hbits <= '1'; end if; set(addsub) <= '1'; else if opcode(8) = '1' then if opcode(5 downto 3) = "001" then --cmpm set_exec(opcCMP) <= '1'; if decodeOPC = '1' then setstate <= "10"; set(update_ld) <= '1'; set(postadd) <= '1'; next_micro_state <= cmpm; end if; set_exec(ea_data_OP1) <= '1'; set(addsub) <= '1'; else --Eor build_logical <= '1'; set_exec(opcEor) <= '1'; end if; else --CMP build_logical <= '1'; set_exec(opcCMP) <= '1'; set(addsub) <= '1'; end if; end if; -- ---- 1100 ---------------------------------------------------------------------------- when "1100" => --and, exg if opcode(7 downto 6) = "11" then --mulu, muls if MUL_Mode /= 3 then if opcode(5 downto 4) = "00" then --Dn, An regdirectsource <= '1'; end if; if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then setstate <= "01"; set(ld_rot_cnt) <= '1'; next_micro_state <= mul1; end if; ea_build_now <= '1'; set_exec(Regwrena) <= '1'; source_lowbits <= '1'; if (nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then dest_hbits <= '1'; end if; datatype <= "01"; else trap_illegal <= '1'; trapmake <= '1'; end if; elsif opcode(8) = '1' and opcode(5 downto 4) = "00" then --exg, abcd if opcode(7 downto 6) = "00" then --abcd build_bcd <= '1'; set_exec(opcADD) <= '1'; set_exec(opcABCD) <= '1'; else --exg datatype <= "10"; set(Regwrena) <= '1'; set(exg) <= '1'; if opcode(6) = '1' and opcode(3) = '1' then dest_areg <= '1'; source_areg <= '1'; end if; if decodeOPC = '1' then setstate <= "01"; else dest_hbits <= '1'; end if; end if; else --and set_exec(opcand) <= '1'; build_logical <= '1'; end if; -- ---- 1110 ---------------------------------------------------------------------------- when "1110" => --rotation / bitfield if opcode(7 downto 6) = "11" then if opcode(11) = '0' then set_exec(opcROT) <= '1'; ea_build_now <= '1'; datatype <= "01"; set_rot_bits <= opcode(10 downto 9); set_exec(ea_data_OP1) <= '1'; write_back <= '1'; else --bitfield if BitField = 0 or (cpu(1) = '0' and BitField = 2) then trap_illegal <= '1'; trapmake <= '1'; else if decodeOPC = '1' then next_micro_state <= nop; set(get_2ndOPC) <= '1'; set(ea_build) <= '1'; end if; set_exec(opcBF) <= '1'; -- BFCLR, BFSET, BFINS, BFCHG, BFFFO, BFTST if opcode(10) = '1' or opcode(8) = '0' then set_exec(opcBFwb) <= '1'; -- BFFFO operating on memory if opcode(10 downto 8) = "101" and opcode(4 downto 3) /= "00" then set_exec(ea_data_OP2) <= '1'; end if; set_exec(ea_data_OP1) <= '1'; end if; -- BFCHG, BFCLR, BFSET, BFINS if opcode(10 downto 8) = "010" or opcode(10 downto 8) = "100" or opcode(10 downto 8) = "110" or opcode(10 downto 8) = "111" then write_back <= '1'; end if; ea_only <= '1'; -- BFEXTU, BFEXTS, BFFFO if opcode(10 downto 8) = "001" or opcode(10 downto 8) = "011" or opcode(10 downto 8) = "101" then set_exec(Regwrena) <= '1'; end if; -- register destination if opcode(4 downto 3) = "00" then -- bftst doesn't write if opcode(10 downto 8) /= "000" then set_exec(Regwrena) <= '1'; end if; if exec(ea_build) = '1' then dest_2ndHbits <= '1'; source_2ndLbits <= '1'; set(get_bfoffset) <= '1'; setstate <= "01"; end if; end if; if set(get_ea_now) = '1' then setstate <= "01"; end if; if exec(get_ea_now) = '1' then dest_2ndHbits <= '1'; source_2ndLbits <= '1'; set(get_bfoffset) <= '1'; setstate <= "01"; set(mem_addsub) <= '1'; next_micro_state <= bf1; end if; if setexecOPC = '1' then if opcode(10 downto 8) = "111" then --BFINS source_2ndHbits <= '1'; elsif opcode(10 downto 8)="001" or opcode(10 downto 8)="011" or opcode(10 downto 8)="101" THEN --BFEXTU, BFEXTS, BFFFO source_lowbits <= '1'; dest_2ndHbits <= '1'; end if; end if; end if; end if; else set_exec(opcROT) <= '1'; set_rot_bits <= opcode(4 downto 3); data_is_source <= '1'; set_exec(Regwrena) <= '1'; if decodeOPC = '1' then if opcode(5) = '1' then next_micro_state <= rota1; set(ld_rot_cnt) <= '1'; setstate <= "01"; else set_rot_cnt(2 downto 0) <= opcode(11 downto 9); if opcode(11 downto 9) = "000" then set_rot_cnt(3) <= '1'; else set_rot_cnt(3) <= '0'; end if; end if; end if; end if; -- ---- ---------------------------------------------------------------------------- when others => trap_1111 <= '1'; trapmake <= '1'; end case; -- use for and, or, Eor, CMP if build_logical = '1' then ea_build_now <= '1'; if set_exec(opcCMP) = '0' and (opcode(8) = '0' or opcode(5 downto 4) = "00" ) then set_exec(Regwrena) <= '1'; end if; if opcode(8) = '1' then write_back <= '1'; set_exec(ea_data_OP1) <= '1'; else source_lowbits <= '1'; if opcode(3) = '1' then --use for cmp source_areg <= '1'; end if; if setexecOPC = '1' then dest_hbits <= '1'; end if; end if; end if; -- use for ABCD, SBCD if build_bcd = '1' then set_exec(use_XZFlag) <= '1'; set_exec(ea_data_OP1) <= '1'; write_back <= '1'; source_lowbits <= '1'; if opcode(3) = '1' then if decodeOPC = '1' then setstate <= "10"; set(update_ld) <= '1'; set(presub) <= '1'; next_micro_state <= op_AxAy; dest_areg <= '1'; --??? end if; else dest_hbits <= '1'; set_exec(Regwrena) <= '1'; end if; end if; ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ if set_Z_error = '1' then -- divu by zero trapmake <= '1'; --wichtig for USP if trapd = '0' then writePC <= '1'; end if; end if; ----------------------------------------------------------------------------- -- execute microcode ----------------------------------------------------------------------------- if rising_edge(clk) THEN if Reset='1' THEN micro_state <= ld_nn; elsif clkena_lw='1' THEN trapd <= trapmake; micro_state <= next_micro_state; end if; end if; case micro_state is when ld_nn => -- (nnnn).w/l=> set(get_ea_now) <= '1'; setnextpass <= '1'; set(addrlong) <= '1'; when st_nn => -- =>(nnnn).w/l setstate <= "11"; set(addrlong) <= '1'; next_micro_state <= nop; when ld_dAn1 => -- d(An)=>, --d(PC)=> set(get_ea_now) <= '1'; setdisp <= '1'; --word setnextpass <= '1'; when ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=> if brief(8) = '0' or extAddr_Mode = 0 or (cpu(1) = '0' and extAddr_Mode = 2) then -- mikej brief extension word only setdisp <= '1'; --byte setdispbyte <= '1'; setstate <= "01"; set(briefext) <= '1'; next_micro_state <= ld_AnXn2; else if brief(7) = '1' then --suppress Base set_suppress_base <= '1'; elsif exec(dispouter) = '1' then set(dispouter) <= '1'; end if; if brief(5) = '0' then --NULL Base Displacement setstate <= "01"; else --WorD Base Displacement if brief(4) = '1' then set(longaktion) <= '1'; --LONG Base Displacement end if; end if; next_micro_state <= ld_229_1; end if; when ld_AnXn2 => set(get_ea_now) <= '1'; setdisp <= '1'; --brief setnextpass <= '1'; ------------------------------------------------------------------------------------- when ld_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> if brief(5) = '1' then --Base Displacement setdisp <= '1'; --add last_data_read end if; if brief(6) = '0' and brief(2) = '0' then --Preindex or Index set(briefext) <= '1'; setstate <= "01"; if brief(1 downto 0) = "00" then next_micro_state <= ld_AnXn2; else next_micro_state <= ld_229_2; end if; else if brief(1 downto 0) = "00" then set(get_ea_now) <= '1'; setnextpass <= '1'; else setstate <= "10"; set(longaktion) <= '1'; next_micro_state <= ld_229_3; end if; end if; when ld_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> setdisp <= '1'; -- add Index setstate <= "10"; set(longaktion) <= '1'; next_micro_state <= ld_229_3; when ld_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> set_suppress_base <= '1'; set(dispouter) <= '1'; if brief(1) = '0' then --NULL Outer Displacement setstate <= "01"; else --WORD Outer Displacement if brief(0) = '1' then set(longaktion) <= '1'; --LONG Outer Displacement end if; end if; next_micro_state <= ld_229_4; when ld_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> if brief(1) = '1' then -- Outer Displacement setdisp <= '1'; --add last_data_read end if; if brief(6) = '0' and brief(2) = '1' then --Postindex set(briefext) <= '1'; setstate <= "01"; next_micro_state <= ld_AnXn2; else set(get_ea_now) <= '1'; setnextpass <= '1'; end if; ---------------------------------------------------------------------------------------- when st_dAn1 => -- =>d(An) setstate <= "11"; setdisp <= '1'; --word next_micro_state <= nop; when st_AnXn1 => -- =>d(An,Xn) if brief(8) = '0' or extAddr_Mode = 0 or (cpu(1) = '0' and extAddr_Mode = 2) then setdisp <= '1'; --byte setdispbyte <= '1'; setstate <= "01"; set(briefext) <= '1'; next_micro_state <= st_AnXn2; else if brief(7) = '1' then --suppress Base set_suppress_base <= '1'; -- elsif exec(dispouter)='1' then -- set(dispouter) <= '1'; end if; if brief(5) = '0' then --NULL Base Displacement setstate <= "01"; else --WorD Base Displacement if brief(4) = '1' then set(longaktion) <= '1'; --LONG Base Displacement end if; end if; next_micro_state <= st_229_1; end if; when st_AnXn2 => setstate <= "11"; setdisp <= '1'; --brief next_micro_state <= nop; ------------------------------------------------------------------------------------- when st_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> if brief(5) = '1' then --Base Displacement setdisp <= '1'; --add last_data_read end if; if brief(6) = '0' and brief(2) = '0' then --Preindex or Index set(briefext) <= '1'; setstate <= "01"; if brief(1 downto 0) = "00" then next_micro_state <= st_AnXn2; else next_micro_state <= st_229_2; end if; else if brief(1 downto 0) = "00" then setstate <= "11"; next_micro_state <= nop; else set(hold_dwr) <= '1'; setstate <= "10"; set(longaktion) <= '1'; next_micro_state <= st_229_3; end if; end if; when st_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> setdisp <= '1'; -- add Index set(hold_dwr) <= '1'; setstate <= "10"; set(longaktion) <= '1'; next_micro_state <= st_229_3; when st_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> set(hold_dwr) <= '1'; set_suppress_base <= '1'; set(dispouter) <= '1'; if brief(1) = '0' then --NULL Outer Displacement setstate <= "01"; else --WorD Outer Displacement if brief(0) = '1' then set(longaktion) <= '1'; --LONG Outer Displacement end if; end if; next_micro_state <= st_229_4; when st_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=> set(hold_dwr) <= '1'; if brief(1) = '1' then -- Outer Displacement setdisp <= '1'; --add last_data_read end if; if brief(6) = '0' and brief(2) = '1' then --Postindex set(briefext) <= '1'; setstate <= "01"; next_micro_state <= st_AnXn2; else setstate <= "11"; next_micro_state <= nop; end if; ---------------------------------------------------------------------------------------- when bra1 => --bra if exe_condition = '1' then TG68_PC_brw <= '1'; --pc+0000 next_micro_state <= nop; skipFetch <= '1'; end if; when bsr1 => --bsr short TG68_PC_brw <= '1'; next_micro_state <= nop; when bsr2 => --bsr if long_start = '0' then TG68_PC_brw <= '1'; end if; skipFetch <= '1'; set(longaktion) <= '1'; writePC <= '1'; setstate <= "11"; next_micro_state <= nopnop; setstackaddr <= '1'; when nopnop => --bsr next_micro_state <= nop; when dbcc1 => --dbcc if exe_condition = '0' then Regwrena_now <= '1'; if c_out(1) = '1' then skipFetch <= '1'; next_micro_state <= nop; TG68_PC_brw <= '1'; end if; end if; when movem1 => --movem if last_data_read(15 downto 0) /= X"0000" then setstate <= "01"; if opcode(5 downto 3) = "100" then set(mem_addsub) <= '1'; end if; next_micro_state <= movem2; end if; when movem2 => --movem if movem_run = '0' then setstate <= "01"; else set(movem_action) <= '1'; set(mem_addsub) <= '1'; next_micro_state <= movem2; if opcode(10) = '0' then setstate <= "11"; set(write_reg) <= '1'; else setstate <= "10"; end if; end if; when andi => --andi if opcode(5 downto 4) /= "00" then setnextpass <= '1'; end if; when op_AxAy => -- op -(Ax),-(Ay) set_direct_data <= '1'; set(presub) <= '1'; dest_hbits <= '1'; dest_areg <= '1'; setstate <= "10"; when cmpm => -- cmpm (Ay)+,(Ax)+ set_direct_data <= '1'; set(postadd) <= '1'; dest_hbits <= '1'; dest_areg <= '1'; setstate <= "10"; when link1 => -- link setstate <= "11"; source_areg <= '1'; set(opcMOVE) <= '1'; set(Regwrena) <= '1'; next_micro_state <= link2; when link2 => -- link setstackaddr <= '1'; set(ea_data_OP2) <= '1'; when unlink1 => -- unlink setstate <= "10"; setstackaddr <= '1'; set(postadd) <= '1'; next_micro_state <= unlink2; when unlink2 => -- unlink set(ea_data_OP2) <= '1'; when trap00 => -- TRAP format #2 next_micro_state <= trap0; set(presub) <= '1'; setstackaddr <='1'; setstate <= "11"; datatype <= "10"; when trap0 => -- TRAP set(presub) <= '1'; setstackaddr <= '1'; setstate <= "11"; if VBR_Stackframe = 1 or (cpu(0) = '1' and VBR_Stackframe = 2) then --68010 set(writePC_add) <= '1'; datatype <= "01"; -- set_datatype <= "10"; next_micro_state <= trap1; else if trap_interrupt='1' or trap_trace='1' or trap_berr='1' THEN writePC <= '1'; end if; datatype <= "10"; next_micro_state <= trap2; end if; when trap1 => -- TRAP -- additional word for 68020 if trap_interrupt = '1' or trap_trace = '1' then writePC <= '1'; end if; set(presub) <= '1'; setstackaddr <= '1'; setstate <= "11"; datatype <= "10"; next_micro_state <= trap2; when trap2 => -- TRAP set(presub) <= '1'; setstackaddr <= '1'; setstate <= "11"; datatype <= "01"; writeSR <= '1'; if trap_berr='1' THEN next_micro_state <= trap4; else next_micro_state <= trap3; end if; when trap3 => -- TRAP set_vectoraddr <= '1'; datatype <= "10"; set(direct_delta) <= '1'; set(directPC) <= '1'; setstate <= "10"; next_micro_state <= nopnop; when trap4 => -- TRAP set(presub) <= '1'; setstackaddr <='1'; setstate <= "11"; datatype <= "01"; writeSR <= '1'; next_micro_state <= trap5; when trap5 => -- TRAP set(presub) <= '1'; setstackaddr <='1'; setstate <= "11"; datatype <= "10"; writeSR <= '1'; next_micro_state <= trap6; when trap6 => -- TRAP set(presub) <= '1'; setstackaddr <='1'; setstate <= "11"; datatype <= "01"; writeSR <= '1'; next_micro_state <= trap3; -- return from exception - RTE -- fetch PC and status register from stack -- 010+ fetches another word containing -- the 12 bit vector offset and the -- frame format. If the frame format is -- 2 another two words have to be taken -- from the stack when rte1 => -- RTE datatype <= "10"; setstate <= "10"; set(postadd) <= '1'; setstackaddr <= '1'; if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then set(direct_delta) <= '1'; end if; set(directPC) <= '1'; next_micro_state <= rte2; when rte2 => -- RTE datatype <= "01"; set(update_FC) <= '1'; if VBR_Stackframe = 1 or (cpu(0) = '1' and VBR_Stackframe = 2) then -- 010+ reads another word setstate <= "10"; set(postadd) <= '1'; setstackaddr <= '1'; next_micro_state <= rte3; else next_micro_state <= nop; end if; when rte3 => -- RTE setstate <= "01"; -- idle state to wait -- for input data to -- arrive next_micro_state <= rte4; WHEN rte4 => -- RTE -- check for stack frame format #2 if last_data_in(15 downto 12)="0010" then -- read another 32 bits in this case setstate <= "10"; -- read datatype <= "10"; -- long word set(postadd) <= '1'; setstackaddr <= '1'; next_micro_state <= rte5; else datatype <= "01"; next_micro_state <= nop; end if; WHEN rte5 => -- RTE next_micro_state <= nop; when movec1 => -- MOVEC set(briefext) <= '1'; set_writePCbig <= '1'; if (brief(11 downto 0) = X"000" or brief(11 downto 0) = X"001" or brief(11 downto 0) = X"800" or brief(11 downto 0) = X"801") or (cpu(1) = '1' and (brief(11 downto 0) = X"002" or brief(11 downto 0) = X"802" or brief(11 downto 0) = X"803" or brief(11 downto 0) = X"804")) then if opcode(0) = '0' then set(Regwrena) <= '1'; end if; -- elsif brief(11 downto 0)=X"800"or brief(11 downto 0)=X"001" or brief(11 downto 0)=X"000" then -- trap_addr_error <= '1'; -- trapmake <= '1'; else trap_illegal <= '1'; trapmake <= '1'; end if; when movep1 => -- MOVEP d(An) setdisp <= '1'; set(mem_addsub) <= '1'; set(mem_byte) <= '1'; set(OP1addr) <= '1'; if opcode(6) = '1' then set(movepl) <= '1'; end if; if opcode(7) = '0' then setstate <= "10"; else setstate <= "11"; end if; next_micro_state <= movep2; when movep2 => if opcode(6) = '1' then set(mem_addsub) <= '1'; set(OP1addr) <= '1'; end if; if opcode(7) = '0' then setstate <= "10"; else setstate <= "11"; end if; next_micro_state <= movep3; when movep3 => if opcode(6) = '1' then set(mem_addsub) <= '1'; set(OP1addr) <= '1'; set(mem_byte) <= '1'; if opcode(7) = '0' then setstate <= "10"; else setstate <= "11"; end if; next_micro_state <= movep4; else datatype <= "01"; --Word end if; when movep4 => if opcode(7) = '0' then setstate <= "10"; else setstate <= "11"; end if; next_micro_state <= movep5; when movep5 => datatype <= "10"; --Long when mul1 => -- mulu if opcode(15) = '1' or MUL_Mode = 0 then set_rot_cnt <= "001110"; else set_rot_cnt <= "011110"; end if; setstate <= "01"; next_micro_state <= mul2; when mul2 => -- mulu setstate <= "01"; if rot_cnt = "00001" then next_micro_state <= mul_end1; else next_micro_state <= mul2; end if; when mul_end1 => -- mulu datatype <= "10"; set(opcMULU) <= '1'; if opcode(15) = '0' and (MUL_Mode = 1 or MUL_Mode = 2) then dest_2ndHbits <= '1'; source_2ndLbits <= '1';--??? set(write_lowlong) <= '1'; if sndOPC(10) = '1' then setstate <= "01"; next_micro_state <= mul_end2; end if; set(Regwrena) <= '1'; end if; datatype <= "10"; when mul_end2 => -- divu set(write_reminder) <= '1'; set(Regwrena) <= '1'; set(opcMULU) <= '1'; when div1 => -- divu setstate <= "01"; next_micro_state <= div2; when div2 => -- divu if (OP2out(31 downto 16) = x"0000" or opcode(15) = '1' or DIV_Mode = 0) and OP2out(15 downto 0) = x"0000" then --div zero set_Z_error <= '1'; else next_micro_state <= div3; end if; set(ld_rot_cnt) <= '1'; setstate <= "01"; when div3 => -- divu if opcode(15) = '1' or DIV_Mode = 0 then set_rot_cnt <= "001101"; else set_rot_cnt <= "011101"; end if; setstate <= "01"; next_micro_state <= div4; when div4 => -- divu setstate <= "01"; if rot_cnt = "00001" then next_micro_state <= div_end1; else next_micro_state <= div4; end if; when div_end1 => -- divu if opcode(15) = '0' and (DIV_Mode = 1 or DIV_Mode = 2) then set(write_reminder) <= '1'; next_micro_state <= div_end2; setstate <= "01"; end if; set(opcDIVU) <= '1'; datatype <= "10"; when div_end2 => -- divu dest_2ndHbits <= '1'; source_2ndLbits <= '1';--??? set(opcDIVU) <= '1'; when rota1 => if OP2out(5 downto 0) /= "000000" then set_rot_cnt <= OP2out(5 downto 0); else set_exec(rot_nop) <= '1'; end if; when bf1 => setstate <= "10"; when pack1 => -- result computation if opcode(7 downto 6) = "10" then -- UNPK reads a byte datatype <= "00"; -- Byte end if; set(ea_data_OP2) <= '1'; set(opcPACK) <= '1'; next_micro_state <= pack2; when pack2 => -- write result if opcode(7 downto 6) = "01" then -- PACK writes a byte datatype <= "00"; end if; set(presub) <= '1'; setstate <= "11"; dest_hbits <= '1'; dest_areg <= '1'; next_micro_state <= pack3; when pack3 => -- this is just to keep datatype == 00 -- for byte writes -- write result if opcode(7 downto 6) = "01" then -- PACK writes a byte datatype <= "00"; end if; when others => NULL; end case; end process; ----------------------------------------------------------------------------- -- MOVEC ----------------------------------------------------------------------------- process (clk, VBR, CACR, brief) begin -- all other hexa codes should give illegal isntruction exception if rising_edge(clk) then if Reset = '1' then VBR <= (others => '0'); CACR <= (others => '0'); elsif clkena_lw = '1' and exec(movec_wr) = '1' then case brief(11 downto 0) is when X"000" => NULL; -- SFC -- 68010+ when X"001" => NULL; -- DFC -- 68010+ when X"002" => CACR <= reg_QA(3 downto 0); -- 68020+ when X"800" => NULL; -- USP -- 68010+ when X"801" => VBR <= reg_QA; -- 68010+ when X"802" => NULL; -- CAAR -- 68020+ when X"803" => NULL; -- MSP -- 68020+ when X"804" => NULL; -- isP -- 68020+ when others => NULL; end case; end if; end if; movec_data <= (others => '0'); case brief(11 downto 0) is when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011"); when X"801" => --if VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) then movec_data <= VBR; --end if; when others => NULL; end case; end process; CACR_out <= CACR; VBR_out <= VBR; ----------------------------------------------------------------------------- -- Conditions ----------------------------------------------------------------------------- process (exe_opcode, Flags) begin case exe_opcode(11 downto 8) is when X"0" => exe_condition <= '1'; when X"1" => exe_condition <= '0'; when X"2" => exe_condition <= not Flags(0) and not Flags(2); when X"3" => exe_condition <= Flags(0) or Flags(2); when X"4" => exe_condition <= not Flags(0); when X"5" => exe_condition <= Flags(0); when X"6" => exe_condition <= not Flags(2); when X"7" => exe_condition <= Flags(2); when X"8" => exe_condition <= not Flags(1); when X"9" => exe_condition <= Flags(1); when X"a" => exe_condition <= not Flags(3); when X"b" => exe_condition <= Flags(3); when X"c" => exe_condition <= (Flags(3) and Flags(1)) or (not Flags(3) and not Flags(1)); when X"d" => exe_condition <= (Flags(3) and not Flags(1)) or (not Flags(3) and Flags(1)); when X"e" => exe_condition <= (Flags(3) and Flags(1) and not Flags(2)) or (not Flags(3) and not Flags(1) and not Flags(2)); when X"f" => exe_condition <= (Flags(3) and not Flags(1)) or (not Flags(3) and Flags(1)) or Flags(2); when others => NULL; end case; end process; ----------------------------------------------------------------------------- -- Movem ----------------------------------------------------------------------------- process (clk) begin if rising_edge(clk) then if clkena_lw = '1' then movem_actiond <= exec(movem_action); if decodeOPC = '1' then sndOPC <= data_read(15 downto 0); elsif exec(movem_action) = '1' or set(movem_action) = '1' then case movem_regaddr is when "0000" => sndOPC(0) <= '0'; when "0001" => sndOPC(1) <= '0'; when "0010" => sndOPC(2) <= '0'; when "0011" => sndOPC(3) <= '0'; when "0100" => sndOPC(4) <= '0'; when "0101" => sndOPC(5) <= '0'; when "0110" => sndOPC(6) <= '0'; when "0111" => sndOPC(7) <= '0'; when "1000" => sndOPC(8) <= '0'; when "1001" => sndOPC(9) <= '0'; when "1010" => sndOPC(10) <= '0'; when "1011" => sndOPC(11) <= '0'; when "1100" => sndOPC(12) <= '0'; when "1101" => sndOPC(13) <= '0'; when "1110" => sndOPC(14) <= '0'; when "1111" => sndOPC(15) <= '0'; when others => NULL; end case; end if; end if; end if; end process; process (sndOPC, movem_mux) begin movem_regaddr <= "0000"; movem_run <= '1'; if sndOPC(3 downto 0) = "0000" then if sndOPC(7 downto 4) = "0000" then movem_regaddr(3) <= '1'; if sndOPC(11 downto 8) = "0000" then if sndOPC(15 downto 12) = "0000" then movem_run <= '0'; end if; movem_regaddr(2) <= '1'; movem_mux <= sndOPC(15 downto 12); else movem_mux <= sndOPC(11 downto 8); end if; else movem_mux <= sndOPC(7 downto 4); movem_regaddr(2) <= '1'; end if; else movem_mux <= sndOPC(3 downto 0); end if; if movem_mux(1 downto 0) = "00" then movem_regaddr(1) <= '1'; if movem_mux(2) = '0' then movem_regaddr(0) <= '1'; end if; else if movem_mux(0) = '0' then movem_regaddr(0) <= '1'; end if; end if; end process; exec_d.opcMOVE <= exec(opcMOVE); exec_d.opcMOVEQ <= exec(opcMOVEQ); exec_d.opcMOVESR <= exec(opcMOVESR); exec_d.opcMOVECCR <= exec(opcMOVECCR); exec_d.opcADD <= exec(opcADD); exec_d.opcADDQ <= exec(opcADDQ); exec_d.opcor <= exec(opcor); exec_d.opcand <= exec(opcand); exec_d.opcEor <= exec(opcEor); exec_d.opcCMP <= exec(opcCMP); exec_d.opcROT <= exec(opcROT); exec_d.opcCPMAW <= exec(opcCPMAW); exec_d.opcEXT <= exec(opcEXT); exec_d.opcABCD <= exec(opcABCD); exec_d.opcSBCD <= exec(opcSBCD); exec_d.opcBITS <= exec(opcBITS); exec_d.opcSWAP <= exec(opcSWAP); exec_d.opcScc <= exec(opcScc); exec_d.andisR <= exec(andisR); exec_d.eorisR <= exec(eorisR); exec_d.orisR <= exec(orisR); exec_d.opcMULU <= exec(opcMULU); exec_d.opcDIVU <= exec(opcDIVU); exec_d.dispouter <= exec(dispouter); exec_d.rot_nop <= exec(rot_nop); exec_d.ld_rot_cnt <= exec(ld_rot_cnt); exec_d.writePC_add <= exec(writePC_add); exec_d.ea_data_OP1 <= exec(ea_data_OP1); exec_d.ea_data_OP2 <= exec(ea_data_OP2); exec_d.use_XZFlag <= exec(use_XZFlag); exec_d.get_bfoffset <= exec(get_bfoffset); exec_d.save_memaddr <= exec(save_memaddr); exec_d.opcCHK <= exec(opcCHK); exec_d.movec_rd <= exec(movec_rd); exec_d.movec_wr <= exec(movec_wr); exec_d.Regwrena <= exec(Regwrena); exec_d.update_FC <= exec(update_FC); exec_d.linksp <= exec(linksp); exec_d.movepl <= exec(movepl); exec_d.update_ld <= exec(update_ld); exec_d.OP1addr <= exec(OP1addr); exec_d.write_reg <= exec(write_reg); exec_d.changeMode <= exec(changeMode); exec_d.ea_build <= exec(ea_build); exec_d.trap_chk <= exec(trap_chk); exec_d.store_ea_data <= exec(store_ea_data); exec_d.addrlong <= exec(addrlong); exec_d.postadd <= exec(postadd); exec_d.presub <= exec(presub); exec_d.subidx <= exec(subidx); exec_d.no_Flags <= exec(no_Flags); exec_d.use_SP <= exec(use_SP); exec_d.to_CCR <= exec(to_CCR); exec_d.to_SR <= exec(to_SR); exec_d.OP2out_one <= exec(OP2out_one); exec_d.OP1out_zero <= exec(OP1out_zero); exec_d.mem_addsub <= exec(mem_addsub); exec_d.addsub <= exec(addsub); exec_d.directPC <= exec(directPC); exec_d.direct_delta <= exec(direct_delta); exec_d.directSR <= exec(directSR); exec_d.directCCR <= exec(directCCR); exec_d.exg <= exec(exg); exec_d.get_ea_now <= exec(get_ea_now); exec_d.ea_to_pc <= exec(ea_to_pc); exec_d.hold_dwr <= exec(hold_dwr); exec_d.to_USP <= exec(to_USP); exec_d.from_USP <= exec(from_USP); exec_d.write_lowlong <= exec(write_lowlong); exec_d.write_reminder <= exec(write_reminder); exec_d.movem_action <= exec(movem_action); exec_d.briefext <= exec(briefext); exec_d.get_2ndOPC <= exec(get_2ndOPC); exec_d.mem_byte <= exec(mem_byte); exec_d.longaktion <= exec(longaktion); exec_d.opcRESET <= exec(opcRESET); exec_d.opcBF <= exec(opcBF); exec_d.opcBFwb <= exec(opcBFwb); exec_d.opcPACK <= exec(opcPACK); --when the instruction has completed, the decremented address --register contains the address of the last operand stored. For --the MC68020, MC68030, and MC68040, if the addressing --register is also moved to memory, the value written is the --initial register value decremented by the size of the oper- --ation. The MC68000 writes the initial register value --(not decremented). regin_out <= regin; end;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; package version_pkg is constant c_FW_VERSION : std_logic_vector(31 downto 0) := x"0f4ef308"; end version_pkg;
-- $Id: rblib.vhd 405 2011-08-14 08:16:28Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Package Name: rblib -- Description: Definitions for rbus interface and bus entities -- -- Dependencies: - -- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment -- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports -- 2010-12-26 349 3.0.2 add rb_sel -- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb; -- 2010-12-04 343 3.0 extracted from rrilib and rritblib; -- rbus V3 interface: use aval,re,we -- ... rrilib history removed ... -- 2007-09-09 81 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; package rblib is type rb_mreq_type is record -- rbus - master request aval : slbit; -- address valid re : slbit; -- read enable we : slbit; -- write enable init : slbit; -- init addr : slv8; -- address din : slv16; -- data (input to slave) end record rb_mreq_type; constant rb_mreq_init : rb_mreq_type := ('0','0','0','0', -- aval, re, we, init (others=>'0'), -- addr (others=>'0')); -- din type rb_sres_type is record -- rbus - slave response ack : slbit; -- acknowledge busy : slbit; -- busy err : slbit; -- error dout : slv16; -- data (output from slave) end record rb_sres_type; constant rb_sres_init : rb_sres_type := ('0','0','0', -- ack, busy, err (others=>'0')); -- dout component rb_sel is -- rbus address select logic generic ( RB_ADDR : slv8; -- rbus address base SAWIDTH : natural := 0); -- device subaddress space width port ( CLK : in slbit; -- clock RB_MREQ : in rb_mreq_type; -- rbus request SEL : out slbit -- select state bit ); end component; component rb_sres_or_2 is -- rbus result or, 2 input port ( RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output ); end component; component rb_sres_or_3 is -- rbus result or, 3 input port ( RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output ); end component; component rb_sres_or_4 is -- rbus result or, 4 input port ( RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output ); end component; component rbus_aif is -- rbus, abstract interface port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : out rb_sres_type; -- rbus: response RB_LAM : out slv16; -- rbus: look at me RB_STAT : out slv3 -- rbus: status flags ); end component; component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select generic ( DWIDTH : positive := 16); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset FADDR : in slv3; -- field address SEL : in slbit; -- select DATA : out slv(DWIDTH-1 downto 0); -- data RB_MREQ : in rb_mreq_type; -- rbus request RB_SRES : out rb_sres_type -- rbus response ); end component; component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select generic ( DWIDTH : positive := 16); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset FADDR : in slv3; -- field address SEL : in slbit; -- select DATA : out slv(DWIDTH-1 downto 0); -- data RB_MREQ : in rb_mreq_type; -- rbus request RB_SRES : out rb_sres_type -- rbus response ); end component; component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select generic ( DWIDTH : positive := 16); port ( FADDR : in slv3; -- field address SEL : in slbit; -- select DATA : in slv(DWIDTH-1 downto 0); -- data RB_SRES : out rb_sres_type -- rbus response ); end component; -- -- components for use in test benches (not synthesizable) -- component rb_sres_or_mon is -- rbus result or monitor port ( RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 ); end component; -- simbus sb_cntl field usage for rbus constant sbcntl_sbf_rbmon : integer := 14; component rb_mon is -- rbus monitor generic ( DBASE : positive := 2); -- base for writing data values port ( CLK : in slbit; -- clock CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number ENA : in slbit := '1'; -- enable monitor output RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : in rb_sres_type; -- rbus: response RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me RB_STAT : in slv3 -- rbus: status flags ); end component; component rb_mon_sb is -- simbus wrapper for rbus monitor generic ( DBASE : positive := 2; -- base for writing data values ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable port ( CLK : in slbit; -- clock RB_MREQ : in rb_mreq_type; -- rbus: request RB_SRES : in rb_sres_type; -- rbus: response RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me RB_STAT : in slv3 -- rbus: status flags ); end component; end package rblib;
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : adaptations_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.standard_textio_additions.all; use work.types_pkg.all; package adaptations_pkg is constant C_ALERT_FILE_NAME : string := "_Alert.txt"; constant C_LOG_FILE_NAME : string := "_Log.txt"; constant C_SHOW_BITVIS_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info constant C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info ------------------------------------------------------------------------------- -- Log format ------------------------------------------------------------------------------- --Bitvis: [<ID>] <time> <Scope> Msg --PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM constant C_LOG_PREFIX : string := "Bitvis: "; -- Note: ': ' is recommended as final characters constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length; constant C_LOG_MSG_ID_WIDTH : natural := 20; constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns" constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps) constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE constant C_LOG_SCOPE_WIDTH : natural := 16; constant C_LOG_LINE_WIDTH : natural := 150; constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH; constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line. constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line. constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none signal global_show_log_id : boolean := true; signal global_show_log_scope : boolean := true; -- UVVM dedicated. May be moved to separate UVVM adaptation package signal global_show_msg_for_uvvm_cmd : boolean := true; -- End of UVVM dedicated ------------------------------------------------------------------------------- -- Verbosity control -- NOTE: Do not enter new IDs without proper evaluation: -- 1. Is it - or could it be covered by an existing ID -- 2. Could it be combined with other needs for a more general new ID -- Feel free to suggest new ID for future versions of Bitvis Utility Library ([email protected]) ------------------------------------------------------------------------------- type t_msg_id is ( -- Bitvis utility methods NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside ID_UTIL_SETUP, -- Used for Utility setup ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs. ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts. ID_NEVER, -- Used for avoiding log entry. Cannot be enabled. ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal -- General ID_POS_ACK, -- To write a positive acknowledge on a check -- Directly inside test sequencers ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers) ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer -- BFMs ID_BFM, -- Used inside a BFM (to log BFM access) ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready) -- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments. -- Segment Ids, finest granularity of packet data ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge) -- Packet Ids, medium granularity of packet data ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge) -- Frame Ids, roughest granularity of packet data ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge) -- Distributed command systems ID_UVVM_SEND_CMD, ID_UVVM_CMD_ACK, ID_UVVM_CMD_RESULT, ID_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command ID_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command ID_IMMEDIATE, -- Message from VVC interpreter that an IMMEDIATE command has been executed ID_IMMEDIATE_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete ID_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution ID_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command -- VVC system ID_VVC_CONSTRUCTOR, -- Constructor message from VVCs -- Special purpose - Not really IDs ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER ); type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled; constant C_DEFAULT_MSG_ID_PANEL : t_msg_id_panel := ( ID_NEVER => DISABLED, ID_UTIL_BURIED => DISABLED, others => ENABLED ); type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4); constant C_MSG_ID_INDENT : t_msg_id_indent := ( ID_IMMEDIATE_WAIT => " ..", ID_INTERPRETER => " " & NUL & NUL, ID_INTERPRETER_WAIT => " ..", ID_EXECUTOR => " " & NUL & NUL, ID_EXECUTOR_WAIT => " ..", ID_UVVM_SEND_CMD => "->" & NUL & NUL, ID_UVVM_CMD_ACK => " ", others => "" & NUL & NUL & NUL & NUL ); ------------------------------------------------------------------------- -- Alert counters ------------------------------------------------------------------------- -- Default values. These can be overwritten in each sequencer by using -- set_alert_attention or set_alert_stop_limit (see quick ref). constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD); -- 0 = Never stop constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0, others => 1); ------------------------------------------------------------------------- -- Deprecate ------------------------------------------------------------------------- -- These values are used to indicate outdated sub-programs constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE; shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' ')); end package adaptations_pkg; package body adaptations_pkg is end package body adaptations_pkg;
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : adaptations_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.standard_textio_additions.all; use work.types_pkg.all; package adaptations_pkg is constant C_ALERT_FILE_NAME : string := "_Alert.txt"; constant C_LOG_FILE_NAME : string := "_Log.txt"; constant C_SHOW_BITVIS_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info constant C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info ------------------------------------------------------------------------------- -- Log format ------------------------------------------------------------------------------- --Bitvis: [<ID>] <time> <Scope> Msg --PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM constant C_LOG_PREFIX : string := "Bitvis: "; -- Note: ': ' is recommended as final characters constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length; constant C_LOG_MSG_ID_WIDTH : natural := 20; constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns" constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps) constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE constant C_LOG_SCOPE_WIDTH : natural := 16; constant C_LOG_LINE_WIDTH : natural := 150; constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH; constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line. constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line. constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none signal global_show_log_id : boolean := true; signal global_show_log_scope : boolean := true; -- UVVM dedicated. May be moved to separate UVVM adaptation package signal global_show_msg_for_uvvm_cmd : boolean := true; -- End of UVVM dedicated ------------------------------------------------------------------------------- -- Verbosity control -- NOTE: Do not enter new IDs without proper evaluation: -- 1. Is it - or could it be covered by an existing ID -- 2. Could it be combined with other needs for a more general new ID -- Feel free to suggest new ID for future versions of Bitvis Utility Library ([email protected]) ------------------------------------------------------------------------------- type t_msg_id is ( -- Bitvis utility methods NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside ID_UTIL_SETUP, -- Used for Utility setup ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs. ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts. ID_NEVER, -- Used for avoiding log entry. Cannot be enabled. ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal -- General ID_POS_ACK, -- To write a positive acknowledge on a check -- Directly inside test sequencers ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers) ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer -- BFMs ID_BFM, -- Used inside a BFM (to log BFM access) ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready) -- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments. -- Segment Ids, finest granularity of packet data ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge) -- Packet Ids, medium granularity of packet data ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge) -- Frame Ids, roughest granularity of packet data ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge) -- Distributed command systems ID_UVVM_SEND_CMD, ID_UVVM_CMD_ACK, ID_UVVM_CMD_RESULT, ID_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command ID_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command ID_IMMEDIATE, -- Message from VVC interpreter that an IMMEDIATE command has been executed ID_IMMEDIATE_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete ID_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution ID_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command -- VVC system ID_VVC_CONSTRUCTOR, -- Constructor message from VVCs -- Special purpose - Not really IDs ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER ); type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled; constant C_DEFAULT_MSG_ID_PANEL : t_msg_id_panel := ( ID_NEVER => DISABLED, ID_UTIL_BURIED => DISABLED, others => ENABLED ); type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4); constant C_MSG_ID_INDENT : t_msg_id_indent := ( ID_IMMEDIATE_WAIT => " ..", ID_INTERPRETER => " " & NUL & NUL, ID_INTERPRETER_WAIT => " ..", ID_EXECUTOR => " " & NUL & NUL, ID_EXECUTOR_WAIT => " ..", ID_UVVM_SEND_CMD => "->" & NUL & NUL, ID_UVVM_CMD_ACK => " ", others => "" & NUL & NUL & NUL & NUL ); ------------------------------------------------------------------------- -- Alert counters ------------------------------------------------------------------------- -- Default values. These can be overwritten in each sequencer by using -- set_alert_attention or set_alert_stop_limit (see quick ref). constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD); -- 0 = Never stop constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0, others => 1); ------------------------------------------------------------------------- -- Deprecate ------------------------------------------------------------------------- -- These values are used to indicate outdated sub-programs constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE; shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' ')); end package adaptations_pkg; package body adaptations_pkg is end package body adaptations_pkg;
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : adaptations_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.standard_textio_additions.all; use work.types_pkg.all; package adaptations_pkg is constant C_ALERT_FILE_NAME : string := "_Alert.txt"; constant C_LOG_FILE_NAME : string := "_Log.txt"; constant C_SHOW_BITVIS_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info constant C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info ------------------------------------------------------------------------------- -- Log format ------------------------------------------------------------------------------- --Bitvis: [<ID>] <time> <Scope> Msg --PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM constant C_LOG_PREFIX : string := "Bitvis: "; -- Note: ': ' is recommended as final characters constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length; constant C_LOG_MSG_ID_WIDTH : natural := 20; constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns" constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps) constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE constant C_LOG_SCOPE_WIDTH : natural := 16; constant C_LOG_LINE_WIDTH : natural := 150; constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH; constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line. constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line. constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none signal global_show_log_id : boolean := true; signal global_show_log_scope : boolean := true; -- UVVM dedicated. May be moved to separate UVVM adaptation package signal global_show_msg_for_uvvm_cmd : boolean := true; -- End of UVVM dedicated ------------------------------------------------------------------------------- -- Verbosity control -- NOTE: Do not enter new IDs without proper evaluation: -- 1. Is it - or could it be covered by an existing ID -- 2. Could it be combined with other needs for a more general new ID -- Feel free to suggest new ID for future versions of Bitvis Utility Library ([email protected]) ------------------------------------------------------------------------------- type t_msg_id is ( -- Bitvis utility methods NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside ID_UTIL_SETUP, -- Used for Utility setup ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs. ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts. ID_NEVER, -- Used for avoiding log entry. Cannot be enabled. ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal -- General ID_POS_ACK, -- To write a positive acknowledge on a check -- Directly inside test sequencers ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers) ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer -- BFMs ID_BFM, -- Used inside a BFM (to log BFM access) ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready) -- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments. -- Segment Ids, finest granularity of packet data ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge) -- Packet Ids, medium granularity of packet data ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge) -- Frame Ids, roughest granularity of packet data ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge) -- Distributed command systems ID_UVVM_SEND_CMD, ID_UVVM_CMD_ACK, ID_UVVM_CMD_RESULT, ID_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command ID_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command ID_IMMEDIATE, -- Message from VVC interpreter that an IMMEDIATE command has been executed ID_IMMEDIATE_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete ID_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution ID_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command -- VVC system ID_VVC_CONSTRUCTOR, -- Constructor message from VVCs -- Special purpose - Not really IDs ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER ); type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled; constant C_DEFAULT_MSG_ID_PANEL : t_msg_id_panel := ( ID_NEVER => DISABLED, ID_UTIL_BURIED => DISABLED, others => ENABLED ); type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4); constant C_MSG_ID_INDENT : t_msg_id_indent := ( ID_IMMEDIATE_WAIT => " ..", ID_INTERPRETER => " " & NUL & NUL, ID_INTERPRETER_WAIT => " ..", ID_EXECUTOR => " " & NUL & NUL, ID_EXECUTOR_WAIT => " ..", ID_UVVM_SEND_CMD => "->" & NUL & NUL, ID_UVVM_CMD_ACK => " ", others => "" & NUL & NUL & NUL & NUL ); ------------------------------------------------------------------------- -- Alert counters ------------------------------------------------------------------------- -- Default values. These can be overwritten in each sequencer by using -- set_alert_attention or set_alert_stop_limit (see quick ref). constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD); -- 0 = Never stop constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0, others => 1); ------------------------------------------------------------------------- -- Deprecate ------------------------------------------------------------------------- -- These values are used to indicate outdated sub-programs constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE; shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' ')); end package adaptations_pkg; package body adaptations_pkg is end package body adaptations_pkg;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart_baudgen is PORT( CLK_I : in std_logic; RST_I : in std_logic; RD : in std_logic; WR : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_SEROUT : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_READY : out std_logic; TX_BUSY : out std_logic ); end uart_baudgen; architecture Behavioral of uart_baudgen is COMPONENT baudgen Generic(bg_clock_freq : integer; bg_baud_rate : integer); PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : OUT std_logic ); END COMPONENT; COMPONENT uart PORT( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); END COMPONENT; signal CE_16 : std_logic; signal RX_FLAG : std_logic; signal RX_OLD_FLAG : std_logic; signal TX_FLAG : std_logic; signal TX_FLAGQ : std_logic; signal LTX_DATA : std_logic_vector(7 downto 0); signal LRX_READY : std_logic; begin RX_READY <= LRX_READY; TX_BUSY <= TX_FLAG xor TX_FLAGQ; baud: baudgen GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200) PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16 ); urt: uart PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, TX_DATA => LTX_DATA, TX_FLAG => TX_FLAG, TX_SEROUT => TX_SEROUT, TX_FLAGQ => TX_FLAGQ, RX_SERIN => RX_SERIN, RX_DATA => RX_DATA, RX_FLAG => RX_FLAG ); process(CLK_I) begin if (rising_edge(CLK_I)) then if (RST_I = '1') then TX_FLAG <= '0'; LTX_DATA <= X"33"; else if (RD = '1') then -- read Rx data LRX_READY <= '0'; end if; if (WR = '1') then -- write Tx data TX_FLAG <= not TX_FLAG; LTX_DATA <= TX_DATA; end if; if (RX_FLAG /= RX_OLD_FLAG) then LRX_READY <= '1'; end if; RX_OLD_FLAG <= RX_FLAG; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart_baudgen is PORT( CLK_I : in std_logic; RST_I : in std_logic; RD : in std_logic; WR : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_SEROUT : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_READY : out std_logic; TX_BUSY : out std_logic ); end uart_baudgen; architecture Behavioral of uart_baudgen is COMPONENT baudgen Generic(bg_clock_freq : integer; bg_baud_rate : integer); PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : OUT std_logic ); END COMPONENT; COMPONENT uart PORT( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); END COMPONENT; signal CE_16 : std_logic; signal RX_FLAG : std_logic; signal RX_OLD_FLAG : std_logic; signal TX_FLAG : std_logic; signal TX_FLAGQ : std_logic; signal LTX_DATA : std_logic_vector(7 downto 0); signal LRX_READY : std_logic; begin RX_READY <= LRX_READY; TX_BUSY <= TX_FLAG xor TX_FLAGQ; baud: baudgen GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200) PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16 ); urt: uart PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, TX_DATA => LTX_DATA, TX_FLAG => TX_FLAG, TX_SEROUT => TX_SEROUT, TX_FLAGQ => TX_FLAGQ, RX_SERIN => RX_SERIN, RX_DATA => RX_DATA, RX_FLAG => RX_FLAG ); process(CLK_I) begin if (rising_edge(CLK_I)) then if (RST_I = '1') then TX_FLAG <= '0'; LTX_DATA <= X"33"; else if (RD = '1') then -- read Rx data LRX_READY <= '0'; end if; if (WR = '1') then -- write Tx data TX_FLAG <= not TX_FLAG; LTX_DATA <= TX_DATA; end if; if (RX_FLAG /= RX_OLD_FLAG) then LRX_READY <= '1'; end if; RX_OLD_FLAG <= RX_FLAG; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart_baudgen is PORT( CLK_I : in std_logic; RST_I : in std_logic; RD : in std_logic; WR : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_SEROUT : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_READY : out std_logic; TX_BUSY : out std_logic ); end uart_baudgen; architecture Behavioral of uart_baudgen is COMPONENT baudgen Generic(bg_clock_freq : integer; bg_baud_rate : integer); PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : OUT std_logic ); END COMPONENT; COMPONENT uart PORT( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); END COMPONENT; signal CE_16 : std_logic; signal RX_FLAG : std_logic; signal RX_OLD_FLAG : std_logic; signal TX_FLAG : std_logic; signal TX_FLAGQ : std_logic; signal LTX_DATA : std_logic_vector(7 downto 0); signal LRX_READY : std_logic; begin RX_READY <= LRX_READY; TX_BUSY <= TX_FLAG xor TX_FLAGQ; baud: baudgen GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200) PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16 ); urt: uart PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, TX_DATA => LTX_DATA, TX_FLAG => TX_FLAG, TX_SEROUT => TX_SEROUT, TX_FLAGQ => TX_FLAGQ, RX_SERIN => RX_SERIN, RX_DATA => RX_DATA, RX_FLAG => RX_FLAG ); process(CLK_I) begin if (rising_edge(CLK_I)) then if (RST_I = '1') then TX_FLAG <= '0'; LTX_DATA <= X"33"; else if (RD = '1') then -- read Rx data LRX_READY <= '0'; end if; if (WR = '1') then -- write Tx data TX_FLAG <= not TX_FLAG; LTX_DATA <= TX_DATA; end if; if (RX_FLAG /= RX_OLD_FLAG) then LRX_READY <= '1'; end if; RX_OLD_FLAG <= RX_FLAG; end if; end if; end process; end Behavioral;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END tri_intersect_ap_fsub_7_full_dsp_32; ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 1, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 7, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END tri_intersect_ap_fsub_7_full_dsp_32_arch;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END tri_intersect_ap_fsub_7_full_dsp_32; ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 1, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 7, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END tri_intersect_ap_fsub_7_full_dsp_32_arch;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END tri_intersect_ap_fsub_7_full_dsp_32; ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 1, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 7, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END tri_intersect_ap_fsub_7_full_dsp_32_arch;