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package pkg is
type INTEGER is range -2147483648 to 2147483647;
type MY_FILE is file of INTEGER;
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
begin end;
-- @elab foo(bar)
|
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
-- CREATED "Wed Oct 23 06:50:47 2013"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FPGA4U IS
PORT
(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
in_buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
);
END FPGA4U;
ARCHITECTURE bdf_type OF FPGA4U IS
COMPONENT buttons
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
write : IN STD_LOGIC;
address : IN STD_LOGIC;
buttons : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT decoder
PORT(address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
cs_RAM : OUT STD_LOGIC;
cs_ROM : OUT STD_LOGIC;
cs_Buttons : OUT STD_LOGIC;
cs_LEDs : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cpu
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
rddata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
write : OUT STD_LOGIC;
read : OUT STD_LOGIC;
address : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
wrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT leds
PORT(clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
LEDs : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT ram
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
write : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wrdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT rom
PORT(clk : IN STD_LOGIC;
cs : IN STD_LOGIC;
read : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rddata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL address : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL cs_Buttons : STD_LOGIC;
SIGNAL cs_LEDs : STD_LOGIC;
SIGNAL cs_RAM : STD_LOGIC;
SIGNAL cs_ROM : STD_LOGIC;
SIGNAL rddata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL wrdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
BEGIN
b2v_buttons_0 : buttons
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_Buttons,
read => SYNTHESIZED_WIRE_7,
write => SYNTHESIZED_WIRE_8,
address => address(2),
buttons => in_buttons,
wrdata => wrdata,
rddata => rddata);
b2v_decoder_0 : decoder
PORT MAP(address => address,
cs_RAM => cs_RAM,
cs_ROM => cs_ROM,
cs_Buttons => cs_Buttons,
cs_LEDs => cs_LEDs);
b2v_inst : cpu
PORT MAP(clk => clk,
reset_n => reset_n,
rddata => rddata,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address,
wrdata => wrdata);
b2v_LEDs_0 : leds
PORT MAP(clk => clk,
reset_n => reset_n,
cs => cs_LEDs,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(3 DOWNTO 2),
wrdata => wrdata,
LEDs => out_LEDs,
rddata => rddata);
b2v_RAM_0 : ram
PORT MAP(clk => clk,
cs => cs_RAM,
write => SYNTHESIZED_WIRE_8,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
wrdata => wrdata,
rddata => rddata);
b2v_ROM_0 : rom
PORT MAP(clk => clk,
cs => cs_ROM,
read => SYNTHESIZED_WIRE_7,
address => address(11 DOWNTO 2),
rddata => rddata);
END bdf_type; |
library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______________-____") port map (clk, a);
SEQ_B : sequencer generic map ("--___--__----________") port map (clk, b);
SEQ_C : sequencer generic map ("_____-___---_____----") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
assert_NEXT_EVENT_a : assert always ((a and b) -> next_event_a(c)[1 to 4](b));
end architecture psl; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port (
a : in std_logic;
b : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic;
for_augend : out std_logic;
for_addend : out std_logic;
for_c_in : out std_logic;
for_c_out : out std_logic;
for_sum : out std_logic
);
end full_adder;
architecture Behavioral of full_adder is
signal s1, s2 ,s3: std_logic;
begin
s1 <= a xor b;
s2 <= c_in and s1;
s3 <= a and b;
sum <= s1 xor c_in;
c_out <= s2 or s3;
for_augend <= a;
for_addend <= b;
for_c_in <= c_in;
for_c_out <= s2 or s3;
for_sum <= s1 xor c_in;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-rtl-a_2.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ab_e-rtl-a_2.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ab_e
--
architecture rtl of inst_ab_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY d_ff IS
PORT(d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END d_ff;
ARCHITECTURE behave OF d_ff IS
BEGIN
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
q<=d;
END IF;
END PROCESS;
END behave; |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_b_e
case_b_p : in std_ulogic
-- End of Generated Port for Entity inst_b_e
);
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--
-- USB Full-Speed/Hi-Speed Device Controller core - extra_pkg.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
package USBExtra is
component blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end component;
component blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end component;
component sync_fifo
generic (
constant FIFO_WIDTH : positive;
constant FIFO_DEPTH : positive;
constant PROG_FULL_VALUE: positive
);
port (
clk : in std_logic;
rst : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : out std_logic;
prog_full : out std_logic
);
end component;
end USBExtra; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is
component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is
component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is
component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is
component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.1 2006/04/10 15:42:04 wig Exp $
-- $Date: 2006/04/10 15:42:04 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:04 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_e_e
p_mix_unsplice_a1_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0)
-- End of Generated Port for Entity inst_e_e
);
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_ad-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ad
--
architecture rtl of ent_ad is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.seven_seg_pkg.all;
library tb;
use tb.bus_tb_pkg.all;
entity seven_seg_controller_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of seven_seg_controller_tb is
constant clk_period : time := 20 ns;
constant ss1_ticks : natural := 1;
constant ss1_digit_count : natural := 1;
constant ss2_ticks : natural := 10;
constant ss2_digit_count : natural := 4;
constant all_one_digit : digit_info_type := (others => '1');
constant digit_others_zeros : std_logic_vector(bus_data_type'high - digit_info_type'high - 1 downto 0) := (others => '0');
signal mst2ss1 : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss1_2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal mst2ss2 : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss2_2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ss1_digit_anodes : std_logic_vector(ss1_digit_count - 1 downto 0);
signal ss1_kathode : seven_seg_kath_type;
signal ss2_digit_anodes : std_logic_vector(ss2_digit_count - 1 downto 0);
signal ss2_kathode : seven_seg_kath_type;
begin
clk <= not clk after (clk_period/2);
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Address out of range") then
wait until falling_edge(clk);
mst2ss1 <= bus_tb_mst2slv(address => 10, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '1');
check(ss1_2mst.ack = '1');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= bus_tb_mst2slv(address => 1, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '1');
check(ss1_2mst.ack = '1');
end if;
if run("Memory check") then
wait until falling_edge(clk);
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 255, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
check(to_integer(unsigned(ss1_2mst.readData)) = 255);
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 0, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
check(to_integer(unsigned(ss1_2mst.readData)) = 0);
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
end if;
if run("Single output check") then
wait until rising_edge(clk);
wait until falling_edge(clk);
-- Default register content should be all zeros.
check(ss1_digit_anodes(0) = '0');
check(ss1_kathode = "11000000");
-- Only enable the dot
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 16#10#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_digit_anodes(0) = '0');
check(ss1_kathode = "01000000");
end if;
if run("Multiple output check") then
wait until falling_edge(clk);
-- First, enter all values
-- Digit 1: 1, with dot
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#11#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 2: 8, no dot
mst2ss2 <= bus_tb_mst2slv(address => 1, writeData => 16#08#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 3: a, with dot
mst2ss2 <= bus_tb_mst2slv(address => 2, writeData => 16#1a#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 4: f, no dot
mst2ss2 <= bus_tb_mst2slv(address => 3, writeData => 16#0f#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
-- Check the actual outputs. We expect digit 1 to be active right now
check(ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
-- Wait the timeout for the next digit to activate..
wait for ss2_ticks * clk_period;
-- We expect digit 2 to be active right now.
check(ss2_digit_anodes = "1101");
check(ss2_kathode = "10000000");
wait for ss2_ticks * clk_period;
-- We expect digit 3 to be active right now.
check(ss2_digit_anodes = "1011");
check(ss2_kathode = "00001000");
wait for ss2_ticks * clk_period;
-- We expect digit 4 to be active right now.
check(ss2_digit_anodes = "0111");
check(ss2_kathode = "10001110");
end if;
if run("Multiple byte write") then
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Check the actual outputs. We expect digit 1 to be active right now
check(ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
-- Wait the timeout for the next digit to activate..
wait for ss2_ticks * clk_period;
-- We expect digit 2 to be active right now.
check(ss2_digit_anodes = "1101");
check(ss2_kathode = "00100100");
wait for ss2_ticks * clk_period;
-- We expect digit 3 to be active right now.
check(ss2_digit_anodes = "1011");
check(ss2_kathode = "00110000");
wait for ss2_ticks * clk_period;
-- We expect digit 4 to be active right now.
check(ss2_digit_anodes = "0111");
check(ss2_kathode = "00011001");
mst2ss2 <= bus_tb_mst2slv(address => 1, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
wait until (ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1101");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1011");
check(ss2_kathode = "00100100");
wait until (ss2_digit_anodes = "0111");
check(ss2_kathode = "00110000");
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 2, writeData => 16#18181818#, writeEnable => '1', writeMask => 16#9#);
wait until (ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1101");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1011");
check(ss2_kathode = "00000000");
wait until (ss2_digit_anodes = "0111");
check(ss2_kathode = "00110000");
end if;
if run("Multiple byte read") then
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#14131211#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 1, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#141312#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 2, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#1413#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 3, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#14#);
mst2ss2 <= BUS_MST2SLV_IDLE;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
ss_1 : entity src.seven_seg_controller
generic map (
hold_count => ss1_ticks,
digit_count => ss1_digit_count
)
port map (
clk => clk,
rst => rst,
mst2slv => mst2ss1,
slv2mst => ss1_2mst,
digit_anodes => ss1_digit_anodes,
kathode => ss1_kathode
);
ss_2 : entity src.seven_seg_controller
generic map (
hold_count => ss2_ticks,
digit_count => ss2_digit_count
)
port map (
clk => clk,
rst => rst,
mst2slv => mst2ss2,
slv2mst => ss2_2mst,
digit_anodes => ss2_digit_anodes,
kathode => ss2_kathode
);
end architecture;
|
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15 : in std_logic_vector(31 downto 0);
-- Done : out std_logic;
-- Hash_1, Hash_2, Hash_3, Hash_4 : out std_logic_vector(31 downto 0));
--end MD5;
--
--architecture Behavioral of MD5 is
--
----Initial Constants for Words A, B, C, and D
--constant aa : std_logic_vector(31 downto 0) := x"67452301";
--constant bb : std_logic_vector(31 downto 0) := x"EFCDAB89";
--constant cc : std_logic_vector(31 downto 0) := x"98BADCFE";
--constant dd : std_logic_vector(31 downto 0) := x"10325476";
--
--subtype arr8 is STD_LOGIC_VECTOR (7 downto 0);
--subtype arr32 is STD_LOGIC_VECTOR (31 downto 0);
--
----R[64] is used to determine the amount of left rotation
--type Rarray is array (63 downto 0) of arr8;
--constant R : Rarray :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
-- x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
-- x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
-- x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
--
--
----K[64] = floor(abs(sin(i)) * 2^32)
--type Karray is array (63 downto 0) of arr32;
--constant K : Karray :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
-- x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
-- x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
-- x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
-- x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
-- x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
-- x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
-- x"d76aa478");
--
--type Warray is array (15 downto 0) of arr32;
--signal W : Warray;
--signal a, b, c, d, f : std_logic_vector(31 downto 0);
--signal g : integer range 0 to 15;
--signal i : integer range 0 to 64;
--
--type ctrl_state is (Halt, Process_1, Process_2, Process_3, Process_4, Waiting, Finished);
--signal State, Next_state : ctrl_state;
--
--begin
-- Assign_Next_State : process (Clk, Reset)
-- begin
-- if (Reset = '1') then
-- State <= Halt;
-- elsif (rising_edge(clk)) then
-- State <= Next_State;
-- end if;
-- end process;
--
-- Get_Next_State : process (State, Run, FirstRun, i)
-- begin
-- case State is
-- when Halt =>
-- if (FirstRun = '0') then
-- Next_state <= Halt;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_1 => --Each Process is one of the four stages in the MD5 Algorithm
-- if(i = 15) then
-- Next_state <= Process_2;
-- else
-- Next_state <= Process_1;
-- end if;
-- when Process_2 =>
-- if(i = 31) then
-- Next_state <= Process_3;
-- else
-- Next_state <= Process_2;
-- end if;
-- when Process_3 =>
-- if(i = 47) then
-- Next_state <= Process_4;
-- else
-- Next_state <= Process_3;
-- end if;
-- when Process_4 =>
-- if(i = 63) then
-- Next_state <= Finished;
-- else
-- Next_state <= Process_4;
-- end if;
-- when Finished =>
-- Next_state <= Waiting;
-- when Waiting =>
-- if (Run = '0') then
-- Next_state <= Waiting;
-- else
-- Next_state <= Process_1;
-- end if;
-- when others =>
-- Next_state <= Halt;
-- end case;
-- end process;
--
-- Control_States : process (state, a, b, c, d, i)
-- begin
-- Done <= '0';
-- Hash_1 <= x"00000000";
-- Hash_2 <= x"00000000";
-- Hash_3 <= x"00000000";
-- Hash_4 <= x"00000000";
--
-- f <= x"00000000";
-- g <= 0;
-- case State is
-- when Process_1 =>
-- f <= (b and c) or ((not b) and d);
-- g <= i;
-- when Process_2 =>
-- f <= (d and b) or ((not d) and c);
-- g <= (((5*i) + 1) mod 16);
-- when Process_3 =>
-- f <= b xor c xor d;
-- g <= ((3*i) + 5) mod 16;
-- when Process_4 =>
-- f <= c xor (b or (not d));
-- g <= (7*i) mod 16;
-- when Finished =>
-- Done <= '1';
-- Hash_1 <= aa + a;
-- Hash_2 <= bb + b;
-- Hash_3 <= cc + c;
-- Hash_4 <= dd + d;
-- when others =>
-- NULL;
-- end case;
-- end process;
-- Process_MD5 : process (state, a, b, c, d, i, W, clk)
-- begin
-- if (rising_edge(clk)) then
-- case State is
-- when Halt =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when Process_1 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_2 =>
-- d <= c;
-- c <= b;
-- --Shift Left OR'ed with the Equivalent Shift Right is the same as Left Rotation
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_3 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Process_4 =>
-- d <= c;
-- c <= b;
-- b <= b + (SHL((a + f + K(i) + W(g)), R(i)) or SHR((a + f + K(i) + W(g)), ("00100000" - R(i))));
-- a <= d;
-- i <= i + 1;
-- when Waiting =>
-- i <= 0;
-- a <= aa;
-- b <= bb;
-- c <= cc;
-- d <= dd;
--
-- W(0) <= w0;
-- W(1) <= w1;
-- W(2) <= w2;
-- W(3) <= w3;
-- W(4) <= w4;
-- W(5) <= w5;
-- W(6) <= w6;
-- W(7) <= w7;
-- W(8) <= w8;
-- W(9) <= w9;
-- W(10) <= w10;
-- W(11) <= w11;
-- W(12) <= w12;
-- W(13) <= w13;
-- W(14) <= w14;
-- W(15) <= w15;
-- when others =>
-- NULL;
-- end case;
-- end if;
-- end process;
--end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.numeric_bit.all;
entity MD5 is
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end MD5;
architecture Behavioral of MD5 is
-- the initialization values of the loop variables --
constant a_init : unsigned(31 downto 0) := x"67452301";
constant b_init : unsigned(31 downto 0) := x"EFCDAB89";
constant c_init : unsigned(31 downto 0) := x"98BADCFE";
constant d_init : unsigned(31 downto 0) := x"10325476";
-- the array with the init values --
type w_array is array(15 downto 0) of unsigned(31 downto 0);
signal w_c, w_n : w_array; --w_n
-- loop signals --
signal a_c, a_n, b_c, b_n, c_c, c_n, d_c, d_n, f : unsigned(31 downto 0);
signal i_c, i_n : integer range 0 to 63;
signal g : integer range 0 to 15;
-- the states for the main loop --
type state is (stage_1, stage_2, stage_3, stage_4, waiting, finished, set_output);
signal state_c, state_n : state;
-- Specifies the amount to shift in the main loop, use rotate_left() --
type s_array is array(63 downto 0) of unsigned(7 downto 0);
constant s : s_array :=( x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06", x"15", x"0F", x"0A", x"06",
x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04", x"17", x"10", x"0B", x"04",
x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05", x"14", x"0E", x"09", x"05",
x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07", x"16", x"11", x"0C", x"07");
-- 15 0f 0a 06 17 10 0b 04 14 0e 09 05 16 11 0c 07
-- fixed amount to add during the rotation --
type k_array is array(63 downto 0) of unsigned(31 downto 0);
constant k : k_array :=( x"eb86d391", x"2ad7d2bb", x"bd3af235", x"f7537e82", x"4e0811a1", x"a3014314", x"fe2ce6e0", x"6fa87e4f", x"85845dd1",
x"ffeff47d", x"8f0ccc92", x"655b59c3", x"fc93a039", x"ab9423a7", x"432aff97", x"f4292244", x"c4ac5665", x"1fa27cf8",
x"e6db99e5", x"d9d4d039", x"04881d05", x"d4ef3085", x"eaa127fa", x"289b7ec6", x"bebfbc70", x"f6bb4b60", x"4bdecfa9",
x"a4beea44", x"fde5380c", x"6d9d6122", x"8771f681", x"fffa3942", x"8d2a4c8a", x"676f02d9", x"fcefa3f8", x"a9e3e905",
x"455a14ed", x"f4d50d87", x"c33707d6", x"21e1cde6", x"e7d3fbc8", x"d8a1e681", x"02441453", x"d62f105d", x"e9b6c7aa",
x"265e5a51", x"c040b340", x"f61e2562", x"49b40821", x"a679438e", x"fd987193", x"6b901122", x"895cd7be", x"ffff5bb1",
x"8b44f7af", x"698098d8", x"fd469501", x"a8304613", x"4787c62a", x"f57c0faf", x"c1bdceee", x"242070db", x"e8c7b756",
x"d76aa478");
-- begin the Behavioral --
begin
-- the clock process --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= waiting;
-- reset the main loop signals --
i_c <= 0;
a_c <= a_init;
b_c <= b_init;
c_c <= c_init;
d_c <= d_init;
w_c <= (others => (others => '0'));
else
state_c <= state_n;
i_c <= i_n;
a_c <= a_n;
b_c <= b_n;
c_c <= c_n;
d_c <= d_n;
w_c <= w_n;
end if;
end if;
end process;
-- the state control --
FSM: process(state_c, i_start, i_c)
begin
-- defaults --
state_n <= state_c;
case state_c is
when waiting =>
if i_start = '0' then
state_n <= waiting;
else
state_n <= stage_1;
end if;
when stage_1 =>
if i_c = 15 then -- state change depending on the counter
state_n <= stage_2;
else
state_n <= stage_1;
end if;
when stage_2 =>
if i_c = 31 then
state_n <= stage_3;
else
state_n <= stage_2;
end if;
when stage_3 =>
if i_c = 47 then
state_n <= stage_4;
else
state_n <= stage_3;
end if;
when stage_4 =>
if i_c = 63 then
state_n <= finished;
else
state_n <= stage_4;
end if;
when finished =>
state_n <= waiting;
when others =>
null;
end case;
end process;
-- set the outputs and update f & g --
data_path: process(a_c, b_c, c_c, d_c, f, g, i_c, w_c, state_c, i_data_0, i_data_1, i_length)
begin
-- set standard values --
o_done <= '0';
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
f <= (others => '0');
g <= 0;
w_n <= w_c;
-- set init vector-data values --
-- --w(0) <= i_data_0;
-- --w(1) <= i_data_1;
-- w_n(0) <= (others => '0');
-- w_n(1) <= (others => '0');
-- w_n(2) <= (others => '0');
-- w_n(3) <= (others => '0');
-- w_n(4) <= (others => '0');
-- w_n(5) <= (others => '0');
-- w_n(6) <= (others => '0');
-- w_n(7) <= (others => '0');
-- w_n(8) <= (others => '0');
-- w_n(9) <= (others => '0');
-- w_n(10) <= (others => '0');
-- w_n(11) <= (others => '0');
-- w_n(12) <= (others => '0');
-- w_n(13) <= (others => '0');
-- w_n(14) <= (others => '0');
-- --w_n(14) <= unsigned(x"000000" & i_length);
-- w_n(15) <= (others => '0');
-- main loop signals calc set as standard values --
d_n <= c_c;
c_n <= b_c;
b_n <= b_c + rotate_left(a_c + k(i_c) + w_c(g) + f, to_integer(s(i_c)));
a_n <= d_c;
if i_c < 63 then
i_n <= i_c + 1;
else
i_n <= i_c;
end if;
case state_c is
when waiting =>
i_n <= 0;
a_n <= a_init;
b_n <= b_init;
c_n <= c_init;
d_n <= d_init;
w_n(0) <= i_data_0;
w_n(1) <= i_data_1;
w_n(14) <= unsigned(x"000000" & i_length);
when stage_1 =>
f <= (b_c and c_c) or ((not b_c) and d_c);
g <= i_c;-- mod 16; CHECK THIS!!
when stage_2 =>
f <= (d_c and b_c) or ((not d_c) and c_c);
g <= ((5 * i_c) + 1) mod 16;
when stage_3 =>
f <= b_c xor c_c xor d_c;
g <= ((3 * i_c) + 5) mod 16;
when stage_4 =>
f <= c_c xor (b_c or (not d_c));
g <= (7 * i_c) mod 16;
when finished =>
o_done <= '1';
o_hash_0 <= (a_init + a_c);
o_hash_1 <= (b_init + b_c);
o_hash_2 <= (c_init + c_c);
o_hash_3 <= (d_init + d_c);
when others => null;
end case;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY design_1_axi_vdma_0_4 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC
);
END design_1_axi_vdma_0_4;
ARCHITECTURE design_1_axi_vdma_0_4_arch OF design_1_axi_vdma_0_4 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "axi_vdma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_vdma_0_4_arch : ARCHITECTURE IS "design_1_axi_vdma_0_4,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "design_1_axi_vdma_0_4,axi_vdma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=3,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=512,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 3,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 512,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_S2MM_GENLOCK_MODE => 2,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut
);
END design_1_axi_vdma_0_4_arch;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNA3ETEQ66 is
generic (
DECODE : string := "00";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNA3ETEQ66;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNA3ETEQ66_0: if ((DECODE = "00") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNA3ETEQ66_0: alt_dspbuilder_decoder_GNA3ETEQ66
generic map(DECODE => "00", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNSCEXJCJK_1: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_1: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_2: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_2: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "00") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:32 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_zed_audio_ctrl_0_0/ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl
-- Design : ip_design_zed_audio_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_address_decoder is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WVALID_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
\DataTx_R_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
s_axi_bvalid_i_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_address_decoder : entity is "address_decoder";
end ip_design_zed_audio_ctrl_0_0_address_decoder;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^datatx_r_reg[0]\ : STD_LOGIC;
signal \^datatx_r_reg[0]_0\ : STD_LOGIC;
signal \^datatx_r_reg[0]_1\ : STD_LOGIC;
signal \^datatx_r_reg[0]_2\ : STD_LOGIC;
signal \^datatx_r_reg[0]_3\ : STD_LOGIC;
signal \^datatx_r_reg[0]_4\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ : STD_LOGIC;
signal S_AXI_ARREADY_INST_0_i_1_n_0 : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_4 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal s_axi_bvalid_i0 : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[10]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[11]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[12]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[13]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[14]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[15]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[16]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[17]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[18]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[19]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[20]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[21]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[22]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal start : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of S_AXI_ARREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of S_AXI_AWREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of data_rdy_bit_i_2 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_bvalid_i_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_rvalid_i_i_2 : label is "soft_lutpair0";
begin
\DataTx_R_reg[0]\ <= \^datatx_r_reg[0]\;
\DataTx_R_reg[0]_0\ <= \^datatx_r_reg[0]_0\;
\DataTx_R_reg[0]_1\ <= \^datatx_r_reg[0]_1\;
\DataTx_R_reg[0]_2\ <= \^datatx_r_reg[0]_2\;
\DataTx_R_reg[0]_3\ <= \^datatx_r_reg[0]_3\;
\DataTx_R_reg[0]_4\ <= \^datatx_r_reg[0]_4\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF02020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
I5 => \^datatx_r_reg[0]_4\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^datatx_r_reg[0]_4\,
R => '0'
);
\DataTx_L[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_0\,
I1 => \^datatx_r_reg[0]_1\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => \DataTx_L_reg[0]\(0)
);
\DataTx_R[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_1\,
I1 => \^datatx_r_reg[0]_0\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => E(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202020202FF02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_4
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_4,
Q => \^datatx_r_reg[0]_3\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_3,
Q => \^datatx_r_reg[0]_2\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(1),
I2 => S_AXI_ARADDR(0),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(1),
I5 => S_AXI_AWADDR(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_2,
Q => \^datatx_r_reg[0]_1\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_ARADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_WVALID,
I2 => S_AXI_AWVALID,
I3 => Q(1),
I4 => Q(0),
I5 => S_AXI_AWADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_1,
Q => \^datatx_r_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => S_AXI_ARESETN,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => S_AXI_ARREADY_INST_0_i_1_n_0,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
O => start
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\,
I2 => S_AXI_AWADDR(1),
I3 => S_AXI_AWADDR(2),
I4 => S_AXI_AWADDR(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => S_AXI_ARADDR(0),
I1 => S_AXI_ARADDR(2),
I2 => S_AXI_ARADDR(1),
I3 => S_AXI_ARVALID,
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_AWVALID,
I3 => S_AXI_WVALID,
I4 => S_AXI_ARVALID,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_0,
Q => \^datatx_r_reg[0]\,
R => cs_ce_clr
);
S_AXI_ARREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_ARREADY
);
S_AXI_ARREADY_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]_1\,
O => S_AXI_ARREADY_INST_0_i_1_n_0
);
S_AXI_AWREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_AWREADY
);
data_rdy_bit_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg_0
);
data_rdy_bit_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^datatx_r_reg[0]_3\,
I1 => \^datatx_r_reg[0]_2\,
I2 => \^datatx_r_reg[0]_1\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]\,
I5 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_bvalid_i0,
I1 => S_AXI_BREADY,
I2 => s_axi_bvalid_i_reg_1,
O => s_axi_bvalid_i_reg
);
s_axi_bvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(1),
I4 => Q(0),
O => s_axi_bvalid_i0
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAAEAAAEAAAEAAA"
)
port map (
I0 => \s_axi_rdata_i[0]_i_2_n_0\,
I1 => data_rdy_bit,
I2 => \^datatx_r_reg[0]\,
I3 => \s_axi_rdata_i[0]_i_3_n_0\,
I4 => \^datatx_r_reg[0]_0\,
I5 => \DataTx_R_reg[31]\(0),
O => \s_axi_rdata_i_reg[31]\(0)
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \s_axi_rdata_i[0]_i_4_n_0\,
I1 => \DataTx_L_reg[31]\(0),
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(0),
I4 => \DataRx_L_reg[23]\(0),
I5 => \s_axi_rdata_i[23]_i_2_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_1\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(10),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(10),
I4 => \s_axi_rdata_i[10]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(10)
);
\s_axi_rdata_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(10),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(10),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[10]_i_2_n_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(11),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(11),
I4 => \s_axi_rdata_i[11]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(11)
);
\s_axi_rdata_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(11),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(11),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[11]_i_2_n_0\
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(12),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(12),
I4 => \s_axi_rdata_i[12]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(12)
);
\s_axi_rdata_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(12),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(12),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[12]_i_2_n_0\
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(13),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(13),
I4 => \s_axi_rdata_i[13]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(13)
);
\s_axi_rdata_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(13),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(13),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[13]_i_2_n_0\
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(14),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(14),
I4 => \s_axi_rdata_i[14]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(14)
);
\s_axi_rdata_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(14),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(14),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[14]_i_2_n_0\
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(15),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(15),
I4 => \s_axi_rdata_i[15]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(15)
);
\s_axi_rdata_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(15),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(15),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[15]_i_2_n_0\
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(16),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(16),
I4 => \s_axi_rdata_i[16]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(16)
);
\s_axi_rdata_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(16),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(16),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[16]_i_2_n_0\
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(17),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(17),
I4 => \s_axi_rdata_i[17]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(17)
);
\s_axi_rdata_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(17),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(17),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[17]_i_2_n_0\
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(18),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(18),
I4 => \s_axi_rdata_i[18]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(18)
);
\s_axi_rdata_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(18),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(18),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[18]_i_2_n_0\
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(19),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(19),
I4 => \s_axi_rdata_i[19]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(19)
);
\s_axi_rdata_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(19),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(19),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[19]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(1),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(1),
I4 => \s_axi_rdata_i[1]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(1)
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(1),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(20),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(20),
I4 => \s_axi_rdata_i[20]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(20)
);
\s_axi_rdata_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(20),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(20),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[20]_i_2_n_0\
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(21),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(21),
I4 => \s_axi_rdata_i[21]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(21)
);
\s_axi_rdata_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(21),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(21),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[21]_i_2_n_0\
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(22),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(22),
I4 => \s_axi_rdata_i[22]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(22)
);
\s_axi_rdata_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(22),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(22),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[22]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(23),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(23),
I4 => \s_axi_rdata_i[23]_i_4_n_0\,
O => \s_axi_rdata_i_reg[31]\(23)
);
\s_axi_rdata_i[23]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_3\,
O => \s_axi_rdata_i[23]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_2\,
O => \s_axi_rdata_i[23]_i_3_n_0\
);
\s_axi_rdata_i[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(23),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(23),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[23]_i_4_n_0\
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(24),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(24),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(25),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(25),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(26),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(26),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(27),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(27),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(28),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(28),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(29),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(29),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(2),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(2),
I4 => \s_axi_rdata_i[2]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(2)
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(2),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(2),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(30),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(30),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(31),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(31),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(31)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(3),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(3),
I4 => \s_axi_rdata_i[3]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(3)
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(3),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(3),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(4),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(4),
I4 => \s_axi_rdata_i[4]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(4)
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(4),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(4),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(5),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(5),
I4 => \s_axi_rdata_i[5]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(5)
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(5),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(5),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(6),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(6),
I4 => \s_axi_rdata_i[6]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(6)
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(6),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(6),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(7),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(7),
I4 => \s_axi_rdata_i[7]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(7)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(7),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(7),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[7]_i_2_n_0\
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(8),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(8),
I4 => \s_axi_rdata_i[8]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(8)
);
\s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(8),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(8),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[8]_i_2_n_0\
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(9),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(9),
I4 => \s_axi_rdata_i[9]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(9)
);
\s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(9),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(9),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[9]_i_2_n_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => S_AXI_RREADY,
I2 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(0),
I4 => Q(1),
O => s_axi_rvalid_i0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARVALID,
I2 => s_axi_bvalid_i0,
I3 => s_axi_bvalid_i_reg_0,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4454"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_WVALID_0,
I3 => S_AXI_ARVALID,
I4 => \state_reg[1]\,
I5 => s_axi_rvalid_i0,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_iis_deser is
port (
lrclk_d1 : out STD_LOGIC;
sclk_d1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\rdata_reg_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bit_cntr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sdata_reg_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]_0\ : out STD_LOGIC;
\DataRx_L_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_R_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
data_rdy_bit : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
SDATA_I : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_iis_deser : entity is "iis_deser";
end ip_design_zed_audio_ctrl_0_0_iis_deser;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_iis_deser is
signal \^datarx_l_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^datarx_r_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_sequential_iis_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_4_n_0\ : STD_LOGIC;
signal \bit_cntr[4]_i_1_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal bit_rdy : STD_LOGIC;
signal data_rdy_bit_i_4_n_0 : STD_LOGIC;
signal eqOp : STD_LOGIC;
signal iis_state : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of iis_state : signal is "yes";
signal ldata_reg : STD_LOGIC;
signal ldata_reg0 : STD_LOGIC;
signal \^lrclk_d1\ : STD_LOGIC;
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rdata_reg0 : STD_LOGIC;
signal \^sclk_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DataRx_L[23]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \FSM_sequential_iis_state[2]_i_4\ : label is "soft_lutpair8";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[0]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[1]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[2]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_2__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of sdata_reg_i_2 : label is "soft_lutpair10";
begin
\DataRx_L_reg[23]\(23 downto 0) <= \^datarx_l_reg[23]\(23 downto 0);
\DataRx_R_reg[23]\(23 downto 0) <= \^datarx_r_reg[23]\(23 downto 0);
E(0) <= \^e\(0);
lrclk_d1 <= \^lrclk_d1\;
sclk_d1 <= \^sclk_d1\;
\DataRx_L[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => eqOp,
I1 => iis_state(2),
I2 => iis_state(1),
I3 => iis_state(0),
O => \^e\(0)
);
\DataRx_L[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(2),
O => eqOp
);
\FSM_onehot_iis_state[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(1),
O => \FSM_onehot_iis_state_reg[0]_0\
);
\FSM_onehot_iis_state[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(0),
O => \FSM_onehot_iis_state_reg[0]\
);
\FSM_sequential_iis_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75777F7745444044"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(0),
O => \FSM_sequential_iis_state[0]_i_1_n_0\
);
\FSM_sequential_iis_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3A7B3F7B0A480048"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(1),
O => \FSM_sequential_iis_state[1]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FB33FB30F800080"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(2),
O => \FSM_sequential_iis_state[2]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFA33FF000A330F"
)
port map (
I0 => bit_rdy,
I1 => \FSM_sequential_iis_state[2]_i_4_n_0\,
I2 => iis_state(2),
I3 => iis_state(0),
I4 => iis_state(1),
I5 => eqOp,
O => \FSM_sequential_iis_state[2]_i_2_n_0\
);
\FSM_sequential_iis_state[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22A222A2EEAE22A2"
)
port map (
I0 => bit_rdy,
I1 => iis_state(2),
I2 => iis_state(0),
I3 => iis_state(1),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_3_n_0\
);
\FSM_sequential_iis_state[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(1),
I1 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_4_n_0\
);
\FSM_sequential_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[0]_i_1_n_0\,
Q => iis_state(0),
R => '0'
);
\FSM_sequential_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[1]_i_1_n_0\,
Q => iis_state(1),
R => '0'
);
\FSM_sequential_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[2]_i_1_n_0\,
Q => iis_state(2),
R => '0'
);
\bit_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(0)
);
\bit_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__1\(1)
);
\bit_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(2)
);
\bit_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(3),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(3)
);
\bit_cntr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D7"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => bit_rdy
);
\bit_cntr[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^sclk_d1\,
I1 => Q(0),
O => \bit_cntr_reg[4]_0\(0)
);
\bit_cntr[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"78F0F0F0"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(2),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1_n_0\
);
data_rdy_bit_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC00EA0000000000"
)
port map (
I0 => data_rdy_bit,
I1 => \^e\(0),
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => data_rdy_bit_i_4_n_0,
I5 => S_AXI_ARESETN,
O => data_rdy_bit_reg
);
data_rdy_bit_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => eqOp,
I3 => iis_state(2),
I4 => iis_state(1),
I5 => iis_state(0),
O => data_rdy_bit_i_4_n_0
);
\ldata_reg[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => ldata_reg
);
\ldata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(2),
I1 => iis_state(0),
I2 => iis_state(1),
I3 => Q(0),
I4 => \^sclk_d1\,
O => ldata_reg0
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => SDATA_I,
Q => \^datarx_l_reg[23]\(0),
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(9),
Q => \^datarx_l_reg[23]\(10),
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(10),
Q => \^datarx_l_reg[23]\(11),
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(11),
Q => \^datarx_l_reg[23]\(12),
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(12),
Q => \^datarx_l_reg[23]\(13),
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(13),
Q => \^datarx_l_reg[23]\(14),
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(14),
Q => \^datarx_l_reg[23]\(15),
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(15),
Q => \^datarx_l_reg[23]\(16),
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(16),
Q => \^datarx_l_reg[23]\(17),
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(17),
Q => \^datarx_l_reg[23]\(18),
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(18),
Q => \^datarx_l_reg[23]\(19),
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(0),
Q => \^datarx_l_reg[23]\(1),
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(19),
Q => \^datarx_l_reg[23]\(20),
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(20),
Q => \^datarx_l_reg[23]\(21),
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(21),
Q => \^datarx_l_reg[23]\(22),
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(22),
Q => \^datarx_l_reg[23]\(23),
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(1),
Q => \^datarx_l_reg[23]\(2),
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(2),
Q => \^datarx_l_reg[23]\(3),
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(3),
Q => \^datarx_l_reg[23]\(4),
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(4),
Q => \^datarx_l_reg[23]\(5),
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(5),
Q => \^datarx_l_reg[23]\(6),
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(6),
Q => \^datarx_l_reg[23]\(7),
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(7),
Q => \^datarx_l_reg[23]\(8),
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(8),
Q => \^datarx_l_reg[23]\(9),
R => ldata_reg
);
lrclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(1),
Q => \^lrclk_d1\,
R => '0'
);
\rdata_reg[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(0),
I1 => iis_state(1),
I2 => iis_state(2),
I3 => Q(0),
I4 => \^sclk_d1\,
O => rdata_reg0
);
\rdata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
I2 => \out\(2),
I3 => \out\(0),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \rdata_reg_reg[23]_0\(0)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => SDATA_I,
Q => \^datarx_r_reg[23]\(0),
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(9),
Q => \^datarx_r_reg[23]\(10),
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(10),
Q => \^datarx_r_reg[23]\(11),
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(11),
Q => \^datarx_r_reg[23]\(12),
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(12),
Q => \^datarx_r_reg[23]\(13),
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(13),
Q => \^datarx_r_reg[23]\(14),
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(14),
Q => \^datarx_r_reg[23]\(15),
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(15),
Q => \^datarx_r_reg[23]\(16),
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(16),
Q => \^datarx_r_reg[23]\(17),
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(17),
Q => \^datarx_r_reg[23]\(18),
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(18),
Q => \^datarx_r_reg[23]\(19),
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(0),
Q => \^datarx_r_reg[23]\(1),
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(19),
Q => \^datarx_r_reg[23]\(20),
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(20),
Q => \^datarx_r_reg[23]\(21),
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(21),
Q => \^datarx_r_reg[23]\(22),
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(22),
Q => \^datarx_r_reg[23]\(23),
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(1),
Q => \^datarx_r_reg[23]\(2),
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(2),
Q => \^datarx_r_reg[23]\(3),
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(3),
Q => \^datarx_r_reg[23]\(4),
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(4),
Q => \^datarx_r_reg[23]\(5),
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(5),
Q => \^datarx_r_reg[23]\(6),
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(6),
Q => \^datarx_r_reg[23]\(7),
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(7),
Q => \^datarx_r_reg[23]\(8),
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(8),
Q => \^datarx_r_reg[23]\(9),
R => ldata_reg
);
sclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(0),
Q => \^sclk_d1\,
R => '0'
);
sdata_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => sdata_reg_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_iis_ser is
port (
SDATA_O : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
sclk_d1 : in STD_LOGIC;
lrclk_d1 : in STD_LOGIC;
\DataTx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataTx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\clk_cntr_reg[4]\ : in STD_LOGIC;
lrclk_d1_reg : in STD_LOGIC;
lrclk_d1_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
sclk_d1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_iis_ser : entity is "iis_ser";
end ip_design_zed_audio_ctrl_0_0_iis_ser;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_iis_ser is
signal \FSM_onehot_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_2_n_0\ : STD_LOGIC;
signal \^sdata_o\ : STD_LOGIC;
signal \bit_cntr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal eqOp : STD_LOGIC;
signal ldata_reg : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of ldata_reg : signal is "yes";
signal \ldata_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[17]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[18]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[21]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[22]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_2__0_n_0\ : STD_LOGIC;
signal \ldata_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_0_in2_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in2_in : signal is "yes";
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 0 );
signal p_2_in : STD_LOGIC;
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \rdata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[23]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal sdata_reg_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_4\ : label is "soft_lutpair11";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[0]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[1]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[2]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[3]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[4]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3__0\ : label is "soft_lutpair11";
begin
SDATA_O <= \^sdata_o\;
\out\(2 downto 0) <= \^out\(2 downto 0);
\FSM_onehot_iis_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAABA"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(2),
I3 => \^out\(1),
I4 => \^out\(0),
O => \FSM_onehot_iis_state[1]_i_1_n_0\
);
\FSM_onehot_iis_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0ACA"
)
port map (
I0 => p_0_in2_in,
I1 => \^out\(0),
I2 => \FSM_onehot_iis_state[4]_i_1_n_0\,
I3 => ldata_reg,
O => \FSM_onehot_iis_state[2]_i_1_n_0\
);
\FSM_onehot_iis_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_0_in2_in,
I1 => ldata_reg,
I2 => \^out\(0),
O => \FSM_onehot_iis_state[3]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFFFEEEFFFF"
)
port map (
I0 => ldata_reg,
I1 => lrclk_d1_reg,
I2 => \^out\(2),
I3 => eqOp,
I4 => lrclk_d1_reg_0,
I5 => p_0_in2_in,
O => \FSM_onehot_iis_state[4]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(1),
I3 => \^out\(0),
O => \FSM_onehot_iis_state[4]_i_2_n_0\
);
\FSM_onehot_iis_state[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(2),
I3 => \bit_cntr_reg__0\(4),
I4 => \bit_cntr_reg__0\(3),
O => eqOp
);
\FSM_onehot_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => '0',
Q => ldata_reg,
R => '0'
);
\FSM_onehot_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[1]_i_1_n_0\,
Q => \^out\(0),
R => '0'
);
\FSM_onehot_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_onehot_iis_state[2]_i_1_n_0\,
Q => p_0_in2_in,
R => '0'
);
\FSM_onehot_iis_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[3]_i_1_n_0\,
Q => \^out\(1),
R => '0'
);
\FSM_onehot_iis_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[4]_i_2_n_0\,
Q => \^out\(2),
R => '0'
);
\bit_cntr[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__2\(0)
);
\bit_cntr[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__2\(1)
);
\bit_cntr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__2\(2)
);
\bit_cntr[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \bit_cntr_reg__0\(2),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(1),
I3 => \bit_cntr_reg__0\(3),
O => \plusOp__2\(3)
);
\bit_cntr[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(2),
I1 => p_0_in2_in,
O => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr[4]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
I4 => \bit_cntr_reg__0\(4),
O => \plusOp__2\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1__0_n_0\
);
\ldata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_L_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => \ldata_reg[0]_i_1_n_0\
);
\ldata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(10),
O => \ldata_reg[10]_i_1_n_0\
);
\ldata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(11),
O => \ldata_reg[11]_i_1_n_0\
);
\ldata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(12),
O => \ldata_reg[12]_i_1_n_0\
);
\ldata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(13),
O => \ldata_reg[13]_i_1_n_0\
);
\ldata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(14),
O => \ldata_reg[14]_i_1_n_0\
);
\ldata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(15),
O => \ldata_reg[15]_i_1_n_0\
);
\ldata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(16),
O => \ldata_reg[16]_i_1_n_0\
);
\ldata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(17),
O => \ldata_reg[17]_i_1_n_0\
);
\ldata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(18),
O => \ldata_reg[18]_i_1_n_0\
);
\ldata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(19),
O => \ldata_reg[19]_i_1_n_0\
);
\ldata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(1),
O => \ldata_reg[1]_i_1_n_0\
);
\ldata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(20),
O => \ldata_reg[20]_i_1_n_0\
);
\ldata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(21),
O => \ldata_reg[21]_i_1_n_0\
);
\ldata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(22),
O => \ldata_reg[22]_i_1_n_0\
);
\ldata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => p_0_in2_in,
I1 => Q(0),
I2 => sclk_d1,
I3 => \^out\(0),
I4 => Q(1),
I5 => lrclk_d1,
O => \ldata_reg[23]_i_1__0_n_0\
);
\ldata_reg[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(23),
O => \ldata_reg[23]_i_2__0_n_0\
);
\ldata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(2),
O => \ldata_reg[2]_i_1_n_0\
);
\ldata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(3),
O => \ldata_reg[3]_i_1_n_0\
);
\ldata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(4),
O => \ldata_reg[4]_i_1_n_0\
);
\ldata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(5),
O => \ldata_reg[5]_i_1_n_0\
);
\ldata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(6),
O => \ldata_reg[6]_i_1_n_0\
);
\ldata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(7),
O => \ldata_reg[7]_i_1_n_0\
);
\ldata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(8),
O => \ldata_reg[8]_i_1_n_0\
);
\ldata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(9),
O => \ldata_reg[9]_i_1_n_0\
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[0]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[10]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[11]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[12]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[13]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[14]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[15]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[16]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[17]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[18]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[19]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[1]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[20]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[21]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[22]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[23]_i_2__0_n_0\,
Q => p_2_in,
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[2]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[3]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[4]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[5]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[6]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[7]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[8]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[9]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[9]\,
R => ldata_reg
);
\rdata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_R_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => p_1_in(0)
);
\rdata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(10),
O => p_1_in(10)
);
\rdata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(11),
O => p_1_in(11)
);
\rdata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(12),
O => p_1_in(12)
);
\rdata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(13),
O => p_1_in(13)
);
\rdata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(14),
O => p_1_in(14)
);
\rdata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(15),
O => p_1_in(15)
);
\rdata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(16),
O => p_1_in(16)
);
\rdata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(17),
O => p_1_in(17)
);
\rdata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(18),
O => p_1_in(18)
);
\rdata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(19),
O => p_1_in(19)
);
\rdata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(1),
O => p_1_in(1)
);
\rdata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(20),
O => p_1_in(20)
);
\rdata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(21),
O => p_1_in(21)
);
\rdata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(22),
O => p_1_in(22)
);
\rdata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(23),
O => p_1_in(23)
);
\rdata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(2),
O => p_1_in(2)
);
\rdata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(3),
O => p_1_in(3)
);
\rdata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(4),
O => p_1_in(4)
);
\rdata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(5),
O => p_1_in(5)
);
\rdata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(6),
O => p_1_in(6)
);
\rdata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(7),
O => p_1_in(7)
);
\rdata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(8),
O => p_1_in(8)
);
\rdata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(9),
O => p_1_in(9)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(0),
Q => \rdata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(10),
Q => \rdata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(11),
Q => \rdata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(12),
Q => \rdata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(13),
Q => \rdata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(14),
Q => \rdata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(15),
Q => \rdata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(16),
Q => \rdata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(17),
Q => \rdata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(18),
Q => \rdata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(19),
Q => \rdata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(1),
Q => \rdata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(20),
Q => \rdata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(21),
Q => \rdata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(22),
Q => \rdata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(23),
Q => \rdata_reg_reg_n_0_[23]\,
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(2),
Q => \rdata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(3),
Q => \rdata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(4),
Q => \rdata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(5),
Q => \rdata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(6),
Q => \rdata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(7),
Q => \rdata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(8),
Q => \rdata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(9),
Q => \rdata_reg_reg_n_0_[9]\,
R => ldata_reg
);
sdata_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCCAF0000CCA0"
)
port map (
I0 => \rdata_reg_reg_n_0_[23]\,
I1 => p_2_in,
I2 => \^out\(2),
I3 => p_0_in2_in,
I4 => \clk_cntr_reg[4]\,
I5 => \^sdata_o\,
O => sdata_reg_i_1_n_0
);
sdata_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => sdata_reg_i_1_n_0,
Q => \^sdata_o\,
R => ldata_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_slave_attachment is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_slave_attachment : entity is "slave_attachment";
end ip_design_zed_audio_ctrl_0_0_slave_attachment;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal I_DECODER_n_46 : STD_LOGIC;
signal I_DECODER_n_47 : STD_LOGIC;
signal I_DECODER_n_7 : STD_LOGIC;
signal I_DECODER_n_8 : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal timeout : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair4";
begin
S_AXI_BVALID <= \^s_axi_bvalid\;
S_AXI_RVALID <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => timeout,
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(3),
Q => timeout,
R => p_2_out
);
I_DECODER: entity work.ip_design_zed_audio_ctrl_0_0_address_decoder
port map (
D(1) => I_DECODER_n_7,
D(0) => I_DECODER_n_8,
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \DataTx_R_reg[0]\,
\DataTx_R_reg[0]_0\ => \DataTx_R_reg[0]_0\,
\DataTx_R_reg[0]_1\ => \DataTx_R_reg[0]_1\,
\DataTx_R_reg[0]_2\ => \DataTx_R_reg[0]_2\,
\DataTx_R_reg[0]_3\ => \DataTx_R_reg[0]_3\,
\DataTx_R_reg[0]_4\ => \DataTx_R_reg[0]_4\,
\DataTx_R_reg[31]\(31 downto 0) => Q(31 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0) => timeout,
Q(1 downto 0) => state(1 downto 0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WVALID_0 => \state[1]_i_2_n_0\,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0,
s_axi_bvalid_i_reg => I_DECODER_n_47,
s_axi_bvalid_i_reg_0 => \state[0]_i_2_n_0\,
s_axi_bvalid_i_reg_1 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[31]\(31 downto 0) => IP2Bus_Data(31 downto 0),
s_axi_rvalid_i_reg => I_DECODER_n_46,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
\state_reg[1]\ => \state[1]_i_3_n_0\
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => SR(0),
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_47,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => S_AXI_RDATA(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => S_AXI_RDATA(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => S_AXI_RDATA(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => S_AXI_RDATA(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => S_AXI_RDATA(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => S_AXI_RDATA(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => S_AXI_RDATA(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => S_AXI_RDATA(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => S_AXI_RDATA(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => S_AXI_RDATA(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => S_AXI_RDATA(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => S_AXI_RDATA(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => S_AXI_RDATA(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => S_AXI_RDATA(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => S_AXI_RDATA(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => S_AXI_RDATA(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => S_AXI_RDATA(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => S_AXI_RDATA(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => S_AXI_RDATA(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => S_AXI_RDATA(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => S_AXI_RDATA(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => S_AXI_RDATA(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => S_AXI_RDATA(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => S_AXI_RDATA(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => S_AXI_RDATA(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => S_AXI_RDATA(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => S_AXI_RDATA(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => S_AXI_RDATA(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => S_AXI_RDATA(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => S_AXI_RDATA(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => S_AXI_RDATA(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => S_AXI_RDATA(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_46,
Q => \^s_axi_rvalid\,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07770000FFFF0000"
)
port map (
I0 => \^s_axi_bvalid\,
I1 => S_AXI_BREADY,
I2 => S_AXI_RREADY,
I3 => \^s_axi_rvalid\,
I4 => state(0),
I5 => state(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => S_AXI_RREADY,
I3 => S_AXI_BREADY,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_8,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_7,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_user_logic is
port (
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
data_rdy_bit : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_user_logic : entity is "user_logic";
end ip_design_zed_audio_ctrl_0_0_user_logic;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_user_logic is
signal Inst_iis_deser_n_3 : STD_LOGIC;
signal Inst_iis_deser_n_33 : STD_LOGIC;
signal Inst_iis_deser_n_34 : STD_LOGIC;
signal Inst_iis_deser_n_35 : STD_LOGIC;
signal Inst_iis_deser_n_36 : STD_LOGIC;
signal Inst_iis_deser_n_37 : STD_LOGIC;
signal Inst_iis_deser_n_38 : STD_LOGIC;
signal Inst_iis_deser_n_39 : STD_LOGIC;
signal Inst_iis_deser_n_40 : STD_LOGIC;
signal Inst_iis_deser_n_41 : STD_LOGIC;
signal Inst_iis_deser_n_42 : STD_LOGIC;
signal Inst_iis_deser_n_43 : STD_LOGIC;
signal Inst_iis_deser_n_44 : STD_LOGIC;
signal Inst_iis_deser_n_45 : STD_LOGIC;
signal Inst_iis_deser_n_46 : STD_LOGIC;
signal Inst_iis_deser_n_47 : STD_LOGIC;
signal Inst_iis_deser_n_48 : STD_LOGIC;
signal Inst_iis_deser_n_49 : STD_LOGIC;
signal Inst_iis_deser_n_5 : STD_LOGIC;
signal Inst_iis_deser_n_50 : STD_LOGIC;
signal Inst_iis_deser_n_51 : STD_LOGIC;
signal Inst_iis_deser_n_52 : STD_LOGIC;
signal Inst_iis_deser_n_53 : STD_LOGIC;
signal Inst_iis_deser_n_54 : STD_LOGIC;
signal Inst_iis_deser_n_55 : STD_LOGIC;
signal Inst_iis_deser_n_56 : STD_LOGIC;
signal Inst_iis_deser_n_6 : STD_LOGIC;
signal Inst_iis_deser_n_7 : STD_LOGIC;
signal Inst_iis_deser_n_8 : STD_LOGIC;
signal Inst_iis_ser_n_1 : STD_LOGIC;
signal Inst_iis_ser_n_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \clk_cntr[10]_i_2_n_0\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[0]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[1]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[2]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[3]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[5]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[6]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[7]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[8]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[9]\ : STD_LOGIC;
signal data_rdy : STD_LOGIC;
signal \^data_rdy_bit\ : STD_LOGIC;
signal ldata_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal lrclk_d1 : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^s_axi_rdata_i_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rdata_i_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal sclk_d1 : STD_LOGIC;
signal write_bit : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \clk_cntr[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[7]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[8]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \clk_cntr[9]_i_1\ : label is "soft_lutpair15";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
SR(0) <= \^sr\(0);
data_rdy_bit <= \^data_rdy_bit\;
\s_axi_rdata_i_reg[31]\(31 downto 0) <= \^s_axi_rdata_i_reg[31]\(31 downto 0);
\s_axi_rdata_i_reg[31]_0\(31 downto 0) <= \^s_axi_rdata_i_reg[31]_0\(31 downto 0);
\DataRx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(0),
Q => \s_axi_rdata_i_reg[23]\(0),
R => '0'
);
\DataRx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(10),
Q => \s_axi_rdata_i_reg[23]\(10),
R => '0'
);
\DataRx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(11),
Q => \s_axi_rdata_i_reg[23]\(11),
R => '0'
);
\DataRx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(12),
Q => \s_axi_rdata_i_reg[23]\(12),
R => '0'
);
\DataRx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(13),
Q => \s_axi_rdata_i_reg[23]\(13),
R => '0'
);
\DataRx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(14),
Q => \s_axi_rdata_i_reg[23]\(14),
R => '0'
);
\DataRx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(15),
Q => \s_axi_rdata_i_reg[23]\(15),
R => '0'
);
\DataRx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(16),
Q => \s_axi_rdata_i_reg[23]\(16),
R => '0'
);
\DataRx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(17),
Q => \s_axi_rdata_i_reg[23]\(17),
R => '0'
);
\DataRx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(18),
Q => \s_axi_rdata_i_reg[23]\(18),
R => '0'
);
\DataRx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(19),
Q => \s_axi_rdata_i_reg[23]\(19),
R => '0'
);
\DataRx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(1),
Q => \s_axi_rdata_i_reg[23]\(1),
R => '0'
);
\DataRx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(20),
Q => \s_axi_rdata_i_reg[23]\(20),
R => '0'
);
\DataRx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(21),
Q => \s_axi_rdata_i_reg[23]\(21),
R => '0'
);
\DataRx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(22),
Q => \s_axi_rdata_i_reg[23]\(22),
R => '0'
);
\DataRx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(23),
Q => \s_axi_rdata_i_reg[23]\(23),
R => '0'
);
\DataRx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(2),
Q => \s_axi_rdata_i_reg[23]\(2),
R => '0'
);
\DataRx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(3),
Q => \s_axi_rdata_i_reg[23]\(3),
R => '0'
);
\DataRx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(4),
Q => \s_axi_rdata_i_reg[23]\(4),
R => '0'
);
\DataRx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(5),
Q => \s_axi_rdata_i_reg[23]\(5),
R => '0'
);
\DataRx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(6),
Q => \s_axi_rdata_i_reg[23]\(6),
R => '0'
);
\DataRx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(7),
Q => \s_axi_rdata_i_reg[23]\(7),
R => '0'
);
\DataRx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(8),
Q => \s_axi_rdata_i_reg[23]\(8),
R => '0'
);
\DataRx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(9),
Q => \s_axi_rdata_i_reg[23]\(9),
R => '0'
);
\DataRx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_56,
Q => \s_axi_rdata_i_reg[23]_0\(0),
R => '0'
);
\DataRx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_46,
Q => \s_axi_rdata_i_reg[23]_0\(10),
R => '0'
);
\DataRx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_45,
Q => \s_axi_rdata_i_reg[23]_0\(11),
R => '0'
);
\DataRx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_44,
Q => \s_axi_rdata_i_reg[23]_0\(12),
R => '0'
);
\DataRx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_43,
Q => \s_axi_rdata_i_reg[23]_0\(13),
R => '0'
);
\DataRx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_42,
Q => \s_axi_rdata_i_reg[23]_0\(14),
R => '0'
);
\DataRx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_41,
Q => \s_axi_rdata_i_reg[23]_0\(15),
R => '0'
);
\DataRx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_40,
Q => \s_axi_rdata_i_reg[23]_0\(16),
R => '0'
);
\DataRx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_39,
Q => \s_axi_rdata_i_reg[23]_0\(17),
R => '0'
);
\DataRx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_38,
Q => \s_axi_rdata_i_reg[23]_0\(18),
R => '0'
);
\DataRx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_37,
Q => \s_axi_rdata_i_reg[23]_0\(19),
R => '0'
);
\DataRx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_55,
Q => \s_axi_rdata_i_reg[23]_0\(1),
R => '0'
);
\DataRx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_36,
Q => \s_axi_rdata_i_reg[23]_0\(20),
R => '0'
);
\DataRx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_35,
Q => \s_axi_rdata_i_reg[23]_0\(21),
R => '0'
);
\DataRx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_34,
Q => \s_axi_rdata_i_reg[23]_0\(22),
R => '0'
);
\DataRx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_33,
Q => \s_axi_rdata_i_reg[23]_0\(23),
R => '0'
);
\DataRx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_54,
Q => \s_axi_rdata_i_reg[23]_0\(2),
R => '0'
);
\DataRx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_53,
Q => \s_axi_rdata_i_reg[23]_0\(3),
R => '0'
);
\DataRx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_52,
Q => \s_axi_rdata_i_reg[23]_0\(4),
R => '0'
);
\DataRx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_51,
Q => \s_axi_rdata_i_reg[23]_0\(5),
R => '0'
);
\DataRx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_50,
Q => \s_axi_rdata_i_reg[23]_0\(6),
R => '0'
);
\DataRx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_49,
Q => \s_axi_rdata_i_reg[23]_0\(7),
R => '0'
);
\DataRx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_48,
Q => \s_axi_rdata_i_reg[23]_0\(8),
R => '0'
);
\DataRx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_47,
Q => \s_axi_rdata_i_reg[23]_0\(9),
R => '0'
);
\DataTx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]\(0),
R => \^sr\(0)
);
\DataTx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]\(10),
R => \^sr\(0)
);
\DataTx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]\(11),
R => \^sr\(0)
);
\DataTx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]\(12),
R => \^sr\(0)
);
\DataTx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]\(13),
R => \^sr\(0)
);
\DataTx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]\(14),
R => \^sr\(0)
);
\DataTx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]\(15),
R => \^sr\(0)
);
\DataTx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]\(16),
R => \^sr\(0)
);
\DataTx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]\(17),
R => \^sr\(0)
);
\DataTx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]\(18),
R => \^sr\(0)
);
\DataTx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]\(19),
R => \^sr\(0)
);
\DataTx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]\(1),
R => \^sr\(0)
);
\DataTx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]\(20),
R => \^sr\(0)
);
\DataTx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]\(21),
R => \^sr\(0)
);
\DataTx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]\(22),
R => \^sr\(0)
);
\DataTx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]\(23),
R => \^sr\(0)
);
\DataTx_L_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]\(24),
R => \^sr\(0)
);
\DataTx_L_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]\(25),
R => \^sr\(0)
);
\DataTx_L_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]\(26),
R => \^sr\(0)
);
\DataTx_L_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]\(27),
R => \^sr\(0)
);
\DataTx_L_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]\(28),
R => \^sr\(0)
);
\DataTx_L_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]\(29),
R => \^sr\(0)
);
\DataTx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]\(2),
R => \^sr\(0)
);
\DataTx_L_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]\(30),
R => \^sr\(0)
);
\DataTx_L_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]\(31),
R => \^sr\(0)
);
\DataTx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]\(3),
R => \^sr\(0)
);
\DataTx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]\(4),
R => \^sr\(0)
);
\DataTx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]\(5),
R => \^sr\(0)
);
\DataTx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]\(6),
R => \^sr\(0)
);
\DataTx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]\(7),
R => \^sr\(0)
);
\DataTx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]\(8),
R => \^sr\(0)
);
\DataTx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]\(9),
R => \^sr\(0)
);
\DataTx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]_0\(0),
R => \^sr\(0)
);
\DataTx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]_0\(10),
R => \^sr\(0)
);
\DataTx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]_0\(11),
R => \^sr\(0)
);
\DataTx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]_0\(12),
R => \^sr\(0)
);
\DataTx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]_0\(13),
R => \^sr\(0)
);
\DataTx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]_0\(14),
R => \^sr\(0)
);
\DataTx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]_0\(15),
R => \^sr\(0)
);
\DataTx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]_0\(16),
R => \^sr\(0)
);
\DataTx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]_0\(17),
R => \^sr\(0)
);
\DataTx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]_0\(18),
R => \^sr\(0)
);
\DataTx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]_0\(19),
R => \^sr\(0)
);
\DataTx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]_0\(1),
R => \^sr\(0)
);
\DataTx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]_0\(20),
R => \^sr\(0)
);
\DataTx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]_0\(21),
R => \^sr\(0)
);
\DataTx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]_0\(22),
R => \^sr\(0)
);
\DataTx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]_0\(23),
R => \^sr\(0)
);
\DataTx_R_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]_0\(24),
R => \^sr\(0)
);
\DataTx_R_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]_0\(25),
R => \^sr\(0)
);
\DataTx_R_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]_0\(26),
R => \^sr\(0)
);
\DataTx_R_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]_0\(27),
R => \^sr\(0)
);
\DataTx_R_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]_0\(28),
R => \^sr\(0)
);
\DataTx_R_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]_0\(29),
R => \^sr\(0)
);
\DataTx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]_0\(2),
R => \^sr\(0)
);
\DataTx_R_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]_0\(30),
R => \^sr\(0)
);
\DataTx_R_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]_0\(31),
R => \^sr\(0)
);
\DataTx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]_0\(3),
R => \^sr\(0)
);
\DataTx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]_0\(4),
R => \^sr\(0)
);
\DataTx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]_0\(5),
R => \^sr\(0)
);
\DataTx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]_0\(6),
R => \^sr\(0)
);
\DataTx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]_0\(7),
R => \^sr\(0)
);
\DataTx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]_0\(8),
R => \^sr\(0)
);
\DataTx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]_0\(9),
R => \^sr\(0)
);
Inst_iis_deser: entity work.ip_design_zed_audio_ctrl_0_0_iis_deser
port map (
\DataRx_L_reg[23]\(23 downto 0) => ldata_reg(23 downto 0),
\DataRx_R_reg[23]\(23) => Inst_iis_deser_n_33,
\DataRx_R_reg[23]\(22) => Inst_iis_deser_n_34,
\DataRx_R_reg[23]\(21) => Inst_iis_deser_n_35,
\DataRx_R_reg[23]\(20) => Inst_iis_deser_n_36,
\DataRx_R_reg[23]\(19) => Inst_iis_deser_n_37,
\DataRx_R_reg[23]\(18) => Inst_iis_deser_n_38,
\DataRx_R_reg[23]\(17) => Inst_iis_deser_n_39,
\DataRx_R_reg[23]\(16) => Inst_iis_deser_n_40,
\DataRx_R_reg[23]\(15) => Inst_iis_deser_n_41,
\DataRx_R_reg[23]\(14) => Inst_iis_deser_n_42,
\DataRx_R_reg[23]\(13) => Inst_iis_deser_n_43,
\DataRx_R_reg[23]\(12) => Inst_iis_deser_n_44,
\DataRx_R_reg[23]\(11) => Inst_iis_deser_n_45,
\DataRx_R_reg[23]\(10) => Inst_iis_deser_n_46,
\DataRx_R_reg[23]\(9) => Inst_iis_deser_n_47,
\DataRx_R_reg[23]\(8) => Inst_iis_deser_n_48,
\DataRx_R_reg[23]\(7) => Inst_iis_deser_n_49,
\DataRx_R_reg[23]\(6) => Inst_iis_deser_n_50,
\DataRx_R_reg[23]\(5) => Inst_iis_deser_n_51,
\DataRx_R_reg[23]\(4) => Inst_iis_deser_n_52,
\DataRx_R_reg[23]\(3) => Inst_iis_deser_n_53,
\DataRx_R_reg[23]\(2) => Inst_iis_deser_n_54,
\DataRx_R_reg[23]\(1) => Inst_iis_deser_n_55,
\DataRx_R_reg[23]\(0) => Inst_iis_deser_n_56,
E(0) => data_rdy,
\FSM_onehot_iis_state_reg[0]\ => Inst_iis_deser_n_6,
\FSM_onehot_iis_state_reg[0]_0\ => Inst_iis_deser_n_8,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_I => SDATA_I,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
\bit_cntr_reg[4]_0\(0) => write_bit,
data_rdy_bit => \^data_rdy_bit\,
data_rdy_bit_reg => Inst_iis_deser_n_7,
lrclk_d1 => lrclk_d1,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
\rdata_reg_reg[23]_0\(0) => Inst_iis_deser_n_3,
sclk_d1 => sclk_d1,
sdata_reg_reg => Inst_iis_deser_n_5
);
Inst_iis_ser: entity work.ip_design_zed_audio_ctrl_0_0_iis_ser
port map (
\DataTx_L_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]\(23 downto 0),
\DataTx_R_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]_0\(23 downto 0),
E(0) => Inst_iis_deser_n_3,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
\clk_cntr_reg[4]\ => Inst_iis_deser_n_5,
lrclk_d1 => lrclk_d1,
lrclk_d1_reg => Inst_iis_deser_n_8,
lrclk_d1_reg_0 => Inst_iis_deser_n_6,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
sclk_d1 => sclk_d1,
sclk_d1_reg(0) => write_bit
);
\clk_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
O => \plusOp__0\(0)
);
\clk_cntr[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \clk_cntr_reg_n_0_[9]\,
I1 => \clk_cntr_reg_n_0_[7]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[6]\,
I4 => \clk_cntr_reg_n_0_[8]\,
I5 => \^q\(1),
O => \plusOp__0\(10)
);
\clk_cntr[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \clk_cntr[10]_i_2_n_0\
);
\clk_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
I1 => \clk_cntr_reg_n_0_[1]\,
O => \plusOp__0\(1)
);
\clk_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \clk_cntr_reg_n_0_[1]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[2]\,
O => \plusOp__0\(2)
);
\clk_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \clk_cntr_reg_n_0_[2]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[1]\,
I3 => \clk_cntr_reg_n_0_[3]\,
O => \plusOp__0\(3)
);
\clk_cntr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \clk_cntr_reg_n_0_[3]\,
I1 => \clk_cntr_reg_n_0_[1]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[2]\,
I4 => \^q\(0),
O => \plusOp__0\(4)
);
\clk_cntr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \plusOp__0\(5)
);
\clk_cntr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \clk_cntr[10]_i_2_n_0\,
I1 => \clk_cntr_reg_n_0_[6]\,
O => \plusOp__0\(6)
);
\clk_cntr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \clk_cntr_reg_n_0_[6]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[7]\,
O => \plusOp__0\(7)
);
\clk_cntr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \clk_cntr_reg_n_0_[7]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[6]\,
I3 => \clk_cntr_reg_n_0_[8]\,
O => \plusOp__0\(8)
);
\clk_cntr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \clk_cntr_reg_n_0_[8]\,
I1 => \clk_cntr_reg_n_0_[6]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[7]\,
I4 => \clk_cntr_reg_n_0_[9]\,
O => \plusOp__0\(9)
);
\clk_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(0),
Q => \clk_cntr_reg_n_0_[0]\,
R => '0'
);
\clk_cntr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(10),
Q => \^q\(1),
R => '0'
);
\clk_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(1),
Q => \clk_cntr_reg_n_0_[1]\,
R => '0'
);
\clk_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(2),
Q => \clk_cntr_reg_n_0_[2]\,
R => '0'
);
\clk_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(3),
Q => \clk_cntr_reg_n_0_[3]\,
R => '0'
);
\clk_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(4),
Q => \^q\(0),
R => '0'
);
\clk_cntr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(5),
Q => \clk_cntr_reg_n_0_[5]\,
R => '0'
);
\clk_cntr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(6),
Q => \clk_cntr_reg_n_0_[6]\,
R => '0'
);
\clk_cntr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(7),
Q => \clk_cntr_reg_n_0_[7]\,
R => '0'
);
\clk_cntr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(8),
Q => \clk_cntr_reg_n_0_[8]\,
R => '0'
);
\clk_cntr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(9),
Q => \clk_cntr_reg_n_0_[9]\,
R => '0'
);
data_rdy_bit_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Inst_iis_deser_n_7,
Q => \^data_rdy_bit\,
R => '0'
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXI_ARESETN,
O => \^sr\(0)
);
slv_ip2bus_data: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000400040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \s_axi_rdata_i_reg[24]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end ip_design_zed_audio_ctrl_0_0_axi_lite_ipif;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.ip_design_zed_audio_ctrl_0_0_slave_attachment
port map (
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\DataTx_R_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\DataTx_R_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\DataTx_R_reg[0]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\DataTx_R_reg[0]_3\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\DataTx_R_reg[0]_4\ => Bus_RNW_reg,
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(31 downto 0) => Q(31 downto 0),
SR(0) => SR(0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0_i2s_ctrl is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_i2s_ctrl : entity is "i2s_ctrl";
end ip_design_zed_audio_ctrl_0_0_i2s_ctrl;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_i2s_ctrl is
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal DataRx_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataRx_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataTx_L : STD_LOGIC_VECTOR ( 31 downto 0 );
signal DataTx_R : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal USER_LOGIC_I_n_0 : STD_LOGIC;
signal USER_LOGIC_I_n_69 : STD_LOGIC;
signal data_rdy_bit : STD_LOGIC;
begin
AXI_LITE_IPIF_I: entity work.ip_design_zed_audio_ctrl_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\DataRx_L_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => DataRx_R(23 downto 0),
\DataTx_L_reg[0]\(0) => AXI_LITE_IPIF_I_n_12,
\DataTx_L_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
E(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => USER_LOGIC_I_n_0,
Q(31 downto 0) => DataTx_R(31 downto 0),
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => AXI_LITE_IPIF_I_n_8,
data_rdy_bit_reg_0 => AXI_LITE_IPIF_I_n_13
);
USER_LOGIC_I: entity work.ip_design_zed_audio_ctrl_0_0_user_logic
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI_LITE_IPIF_I_n_13,
Q(1 downto 0) => \out\(1 downto 0),
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
data_rdy_bit => data_rdy_bit,
\s_axi_rdata_i_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\s_axi_rdata_i_reg[23]_0\(23 downto 0) => DataRx_R(23 downto 0),
\s_axi_rdata_i_reg[24]\ => USER_LOGIC_I_n_0,
\s_axi_rdata_i_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
\s_axi_rdata_i_reg[31]_0\(31 downto 0) => DataTx_R(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_zed_audio_ctrl_0_0 is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_zed_audio_ctrl_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_zed_audio_ctrl_0_0 : entity is "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ip_design_zed_audio_ctrl_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ip_design_zed_audio_ctrl_0_0 : entity is "i2s_ctrl,Vivado 2017.3";
end ip_design_zed_audio_ctrl_0_0;
architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
attribute max_fanout : string;
attribute max_fanout of S_AXI_ACLK : signal is "10000";
attribute sigis : string;
attribute sigis of S_AXI_ACLK : signal is "Clk";
attribute x_interface_info : string;
attribute x_interface_info of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of S_AXI_ACLK : signal is "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute max_fanout of S_AXI_ARESETN : signal is "10000";
attribute sigis of S_AXI_ARESETN : signal is "Rst";
attribute x_interface_info of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST";
attribute x_interface_parameter of S_AXI_ARESETN : signal is "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of S_AXI_AWADDR : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_WREADY <= \^s_axi_awready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.ip_design_zed_audio_ctrl_0_0_i2s_ctrl
port map (
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(4 downto 2),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(4 downto 2),
S_AXI_AWREADY => \^s_axi_awready\,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
S_AXI_WVALID => S_AXI_WVALID,
\out\(1) => LRCLK,
\out\(0) => BCLK
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral; |
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the next line
s_register <= (0 => "1111X00Z", 1 => x"e1", 2 => x"d2", 3 => x"c3",
4 => x"b4", 5 => x"a5", 6 => x"96", 7 => x"87");
val <= s_register(7) & s_register(6) & s_register(5) & s_register(4)
& s_register(3) & s_register(2) & s_register(1) & s_register(0);
end architecture beh;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:48:55 01/25/2014
-- Design Name: Nicolas Primeau
-- Module Name: booth_multiplier - Behavioral
-- Project Name: Booth Multiplier
-- Target Devices: Xilinx Spartan 6
-- Tool versions:
-- Description: A simple hardware implementation of a booth multiplier
--
-- Dependencies: ieee libraries
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity booth_multiplier is
generic(
n: integer:=4 -- number of bits per vector
);
port(
multiplicand: in std_logic_vector(n-1 downto 0);
multiplier: in std_logic_vector(n-1 downto 0);
result: out std_logic_vector(n*2 -1 downto 0);
clk,enable,load: in std_logic
);
end booth_multiplier;
architecture Behavioral of booth_multiplier is
signal Q: std_logic_vector(n-1 downto 0) := multiplier;
signal M: std_logic_vector(n-1 downto 0) := multiplicand;
signal notM: std_logic_vector(n-1 downto 0):= not(multiplier);
signal A: std_logic_vector(n-1 downto 0) := (others => '0');
signal Qright: std_logic:='0';
begin
process(clk,enable,load,Q,M,notM,A,Qright) is
variable cRes,nRes: std_logic_vector(n*2 -1 downto 0);
begin
if(clk' event and clk = '1') then
if(enable = '1') then
if(load = '1') then
nRes(n*2 -1 downto n) := A;
nRes(n-1 downto 0) := Q;
else
for I in n to 1 loop
if(cRes(0) = '0' AND Qright = '1') then
A <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) + to_integer(unsigned(M))),n));
elsif (cRes(0) = '1' AND Qright = '0') then
A <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) + to_integer(unsigned(notM))),n));
end if;
nRes(n*2 -2 downto n-1) := A; -- technically an arith shift right
nRes(n-2 downto 0):=cRes(n-1 downto 1); -- ^
Qright <= cRes(0);
end loop;
end if;
end if;
cRes := nRes;
result <= nRes;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.defs.all;
--a one-instruction-set instruction computer
entity subleq is
port(
CLK_50: in std_logic;
LED: out std_logic_vector(7 downto 2);
SEVENSEG_SEL: out std_logic_vector(3 downto 0); --which 7seg display is active
SEVENSEG_DAT: out std_logic_vector(0 to 7) --what 7seg data should be displayed
);
end entity;
architecture beh of subleq is
--memory mapped addresses
constant SEVENSEG_01_ADDR : std_logic_vector := x"F0";
constant SEVENSEG_23_ADDR : std_logic_vector := x"F1";
signal instruction_memory_addr : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal instruction_memory_data_out: std_logic_vector(INSTRUCTION_BUS_SIZE - 1 downto 0);
signal data_memory_addr_a : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal data_memory_data_out_a : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_a : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_memory_addr_b : std_logic_vector(ADDR_BUS_SIZE - 1 downto 0);
signal data_memory_data_out_b : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_memory_write_en_b : std_logic;
signal data_b : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_processor_out : std_logic_vector(DATA_BUS_SIZE - 1 downto 0);
signal data_write : std_logic;
signal sevenseg_01_write : std_logic;
signal sevenseg_23_write : std_logic;
signal sevenseg_01_data : std_logic_vector(7 downto 0);
signal sevenseg_23_data : std_logic_vector(7 downto 0);
signal reset : std_logic;
signal clk : std_logic;
signal cur_count : std_logic_vector(27 downto 0);
begin
--LED(7 downto 2) <= not(cur_count(27 downto 22));
LED(7 downto 2) <= not(cur_count(5 downto 0));
reset <= '0';
--All the components
clock_divider: entity work.clk_div
port map(
CLK_50 => CLK_50,
CLK_SLOW => clk
);
process(clk)
begin
if rising_edge(clk) then
cur_count <= cur_count + 1;
end if;
end process;
processor_core: entity work.core
generic map(
ADDR_SIZE => ADDR_BUS_SIZE,
INSTRUCTION_SIZE => INSTRUCTION_BUS_SIZE,
DATA_SIZE => DATA_BUS_SIZE
)
port map(
CLK => clk,
RESET => reset,
INSTRUCTION_MEMORY_ADDR => instruction_memory_addr,
INSTRUCTION_MEMORY_DATA_OUT => instruction_memory_data_out,
DATA_MEMORY_ADDR_A => data_memory_addr_a,
DATA_MEMORY_DATA_OUT_A => data_a,
DATA_MEMORY_ADDR_B => data_memory_addr_b,
DATA_MEMORY_DATA_OUT_B => data_b,
DATA_MEMORY_DATA_IN_B => data_processor_out,
DATA_MEMORY_WRITE_EN_B => data_write
);
instruction_memory: entity work.single_port_memfile
generic map(
ADDR_WIDTH => ADDR_BUS_SIZE,
DATA_WIDTH => INSTRUCTION_BUS_SIZE,
MEM_LENGTH => INSTRUCTION_MEMORY_LENGTH
)
port map(
CLK => clk,
WRITE_EN => '0',
ADDR => instruction_memory_addr,
DATA_IN => (others => '0'),
DATA_OUT => instruction_memory_data_out
);
data_memory: entity work.dual_port_memfile
generic map(
ADDR_WIDTH => ADDR_BUS_SIZE,
DATA_WIDTH => DATA_BUS_SIZE,
MEM_LENGTH => DATA_MEMORY_LENGTH
)
port map(
CLK => clk,
WRITE_EN_A => '0',
ADDR_A => data_memory_addr_a,
DATA_IN_A => (others => '0'),
DATA_OUT_A => data_memory_data_out_a,
WRITE_EN_B => data_memory_write_en_b,
ADDR_B => data_memory_addr_b,
DATA_IN_B => data_processor_out,
DATA_OUT_B => data_memory_data_out_b
);
seg01 : entity work.genericregister
generic map(
NUMBITS => 8
)
port map(
CLK => clk,
EN => sevenseg_01_write,
RESET => reset,
DATA_IN => data_processor_out(7 downto 0),
DATA_OUT => sevenseg_01_data
);
seg23 : entity work.genericregister
generic map(
NUMBITS => 8
)
port map(
CLK => clk,
EN => sevenseg_23_write,
RESET => reset,
DATA_IN => data_processor_out(7 downto 0),
DATA_OUT => sevenseg_23_data
);
segdecoder : entity work.hex_lcd_driver
port map(
CLK => CLK_50, --needs fast clock due to persistence of vision
DIG0 => sevenseg_01_data(3 downto 0),
DIG1 => sevenseg_01_data(7 downto 4),
DIG2 => instruction_memory_addr(3 downto 0),
DIG3 => instruction_memory_addr(7 downto 4),
SEVENSEG_SELECT => SEVENSEG_SEL,
SEVENSEG_DATA => SEVENSEG_DAT
);
--the address translation stuff
data_memory_write_en_b <= '1' when data_memory_addr_b < DATA_MEMORY_LENGTH and data_write = '1' else '0';
sevenseg_01_write <= '1' when data_memory_addr_b = SEVENSEG_01_ADDR and data_write = '1' else '0';
sevenseg_23_write <= '1' when data_memory_addr_b = SEVENSEG_23_ADDR and data_write = '1' else '0';
data_a <=
data_memory_data_out_a when data_memory_addr_a < DATA_MEMORY_LENGTH else
x"00" & sevenseg_01_data when data_memory_addr_a = SEVENSEG_01_ADDR else
x"00" & sevenseg_23_data when data_memory_addr_a = SEVENSEG_23_ADDR else
(others => '0');
data_b <=
data_memory_data_out_b when data_memory_addr_b < DATA_MEMORY_LENGTH else
x"00" & sevenseg_01_data when data_memory_addr_b = SEVENSEG_01_ADDR else
x"00" & sevenseg_23_data when data_memory_addr_b = SEVENSEG_23_ADDR else
(others => '0');
end architecture beh;
|
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Sincronizador de señal de entrada con clk.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xsync : out std_logic
);
end synchronizer;
architecture rtl of synchronizer is
signal xp : std_logic;
begin
clock : process(clk,rst)
begin
if(rst = '0') then
xp <= '1';
xsync <= '1';
elsif(rising_edge(clk)) then
xp <= x;
xsync <= xp;
end if;
end process;
end rtl;
|
-- ----------------------------------------------------------------------------
-- Entity for implementation of Sourdis_Bispo NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity SOURDIS_BISPO_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity SOURDIS_BISPO_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of SOURDIS_BISPO_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
-- local_reset <= RESET or ACK;
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
sclk : in std_ulogic
);
end;
architecture rtl of dcache is
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(ilramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, icache, memory, sysr); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
end record;
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(dlinesize - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(3 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
forcemiss : std_ulogic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
-- variable ddatain : std_logic_vector(31 downto 0);
variable ddatainv, rdatav, align_datav : cdatatype;
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, validraw, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_ulogic;
variable snoopset2 : integer range 0 to DSETS-1;
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= "000") or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
mds := '1'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
ddatainv := (others => (others => '0')); tag := (others => (others => '0'));
v.flush2 := r.flush;
rdatasel := ddata; -- read data from cache as default
vs.readbpx := (others => '0'); rbphit := '0';
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop; -- and hcache;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (r.xaddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
-- vh.set := std_logic_vector(conv_unsigned(i, SETBITS));
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0; snoophit := (others => '0');
snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and not r.flush2; validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then
vset := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(3 downto 0);
end if;
-- Store buffer
-- wdata := r.wb.data1;
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn;
v.forcemiss := forcemiss; sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := "101"; v.ilramen := '1'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
-- setrepl := std_logic_vector(conv_unsigned(set, SETBITS));
if dci.read = '1' then -- read access
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if (not ((r.cctrl.dcs(0) = '1') and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := "100"; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
-- if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
if (r.cctrl.dcs(0) = '1') and (((hit and dci.size(1)) or validraw) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if r.stpend = '0' then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))); twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and ((r.cctrl.dcs(0) = '1') or (dlram = 1)) then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.req) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi;
end if;
end if;
if DSNOOP /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000";
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
v.wb.data2 := dci.edata;
end if;
when "101" => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read; v.ilramen := '0';
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.req) = '1') then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
-- when ASI_UINST | ASI_SINST =>
when others =>
end case;
end if;
rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, 0);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- ddatain := ddatainv(set);
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (dlinesize - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = "000" then
-- vmask := dcramov.dtramout(set).valid or vmaskraw;
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to DSETS-1 loop tag(i)(dlinesize-1 downto 0) := vmask(i); end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
v.valid := vmask;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- cache flush
if ((dci.flush or flush) = '1') and (dcen /= 0) then
v.flush := '1'; v.faddr := (others => '0');
end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= "000") then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = "001") and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
end loop;
dcrami.tag <= tag;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable;--vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr) and not mcdo.scanen;
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
dcrami.dpar <= (others => (others => '0'));
dcrami.tpar <= (others => (others => '0'));
dcrami.ctx <= (others => (others => '0'));
dcrami.ptag <= (others => (others => '0'));
dcrami.tpwrite <= (others => '0');
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs) and not r.forcemiss;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
dco.icdiag.pflush <= '0';
dco.icdiag.ctx <= '0';
dco.icdiag.ilock <= (others => '0');
dco.icdiag.pflushaddr <= (others => '0');
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if rst = '0' then r.wb.lock <= '0'; end if;
--sync reset for wb.lock must be generated here to make
--gate level simulations possible with some synthesis tools
end if;
end process;
sn2 : if DSNOOP /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
nosn3 : if DSNOOP /= 2 generate
rh.hit <= (others => (others => '0')); rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
sclk : in std_ulogic
);
end;
architecture rtl of dcache is
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(ilramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, icache, memory, sysr); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
end record;
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(dlinesize - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
mexc : std_ulogic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(3 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
forcemiss : std_ulogic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
-- variable ddatain : std_logic_vector(31 downto 0);
variable ddatainv, rdatav, align_datav : cdatatype;
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, validraw, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_ulogic;
variable snoopset2 : integer range 0 to DSETS-1;
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= "000") or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
mds := '1'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
if (dlram = 1) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
ddatainv := (others => (others => '0')); tag := (others => (others => '0'));
v.flush2 := r.flush;
rdatasel := ddata; -- read data from cache as default
vs.readbpx := (others => '0'); rbphit := '0';
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop; -- and hcache;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (r.xaddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
-- vh.set := std_logic_vector(conv_unsigned(i, SETBITS));
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0; snoophit := (others => '0');
snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and not r.flush2; validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then
vset := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(3 downto 0);
end if;
-- Store buffer
-- wdata := r.wb.data1;
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (dlram = 1) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram = 1) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn;
v.forcemiss := forcemiss; sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram = 1) then v.dstate := "101"; v.ilramen := '1'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
-- setrepl := std_logic_vector(conv_unsigned(set, SETBITS));
if dci.read = '1' then -- read access
if (dlram = 1) and (lramen = '1') then
lramrd := '1';
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if (not ((r.cctrl.dcs(0) = '1') and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
end if;
end if;
else -- write access
if (dlram = 1) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := "100"; v.xaddress(2) := '1';
end if;
elsif (ilram = 1) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := "101"; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
-- if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
if (r.cctrl.dcs(0) = '1') and (((hit and dci.size(1)) or validraw) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if r.stpend = '0' then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))); twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and ((r.cctrl.dcs(0) = '1') or (dlram = 1)) then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.req) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi;
end if;
end if;
if DSNOOP /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000";
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram = 1) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
v.wb.data2 := dci.edata;
end if;
when "101" => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read; v.ilramen := '0';
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.req) = '1') then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
if (dlram = 1) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
-- when ASI_UINST | ASI_SINST =>
when others =>
end case;
end if;
rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, dlram, dlramsize, dlramstart, 0);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- ddatain := ddatainv(set);
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (dlinesize - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = "000" then
-- vmask := dcramov.dtramout(set).valid or vmaskraw;
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to DSETS-1 loop tag(i)(dlinesize-1 downto 0) := vmask(i); end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
v.valid := vmask;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- cache flush
if ((dci.flush or flush) = '1') and (dcen /= 0) then
v.flush := '1'; v.faddr := (others => '0');
end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= "000") then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = "001") and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
end loop;
dcrami.tag <= tag;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable;--vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr) and not mcdo.scanen;
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
dcrami.dpar <= (others => (others => '0'));
dcrami.tpar <= (others => (others => '0'));
dcrami.ctx <= (others => (others => '0'));
dcrami.ptag <= (others => (others => '0'));
dcrami.tpwrite <= (others => '0');
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs) and not r.forcemiss;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
dco.icdiag.pflush <= '0';
dco.icdiag.ctx <= '0';
dco.icdiag.ilock <= (others => '0');
dco.icdiag.pflushaddr <= (others => '0');
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if rst = '0' then r.wb.lock <= '0'; end if;
--sync reset for wb.lock must be generated here to make
--gate level simulations possible with some synthesis tools
end if;
end process;
sn2 : if DSNOOP /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
nosn3 : if DSNOOP /= 2 generate
rh.hit <= (others => (others => '0')); rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
entity proc11 is
end entity;
architecture test of proc11 is
function count_bits(x : in bit_vector) return natural is
variable r : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
r := r + 1;
end if;
end loop;
return r;
end function;
procedure proc(signal x : in bit_vector) is
begin
wait for 1 ns;
assert count_bits(x) = 0;
wait for 5 ns;
assert count_bits(x) = 4;
end procedure;
signal s : bit_vector(1 to 8);
begin
s <= X"aa" after 2 ns;
proc(s);
end architecture;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fpulib
-- File: fpulib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: package containing LEON
------------------------------------------------------------------------------
-- Version control:
-- 16-08-1999: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package fpulib is
component fpu
port (
ss_clock : in clk_type;
FpInst : in std_logic_vector(9 downto 0);
FpOp : in std_logic;
FpLd : in std_logic;
Reset : in std_logic;
fprf_dout1 : in std_logic_vector(63 downto 0);
fprf_dout2 : in std_logic_vector(63 downto 0);
RoundingMode : in std_logic_vector(1 downto 0);
FpBusy : out std_logic;
FracResult : out std_logic_vector(54 downto 3);
ExpResult : out std_logic_vector(10 downto 0);
SignResult : out std_logic;
SNnotDB : out std_logic;
Excep : out std_logic_vector(5 downto 0);
ConditionCodes : out std_logic_vector(1 downto 0);
ss_scan_mode : in std_logic;
fp_ctl_scan_in : in std_logic;
fp_ctl_scan_out : out std_logic
);
end component;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fpulib
-- File: fpulib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: package containing LEON
------------------------------------------------------------------------------
-- Version control:
-- 16-08-1999: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package fpulib is
component fpu
port (
ss_clock : in clk_type;
FpInst : in std_logic_vector(9 downto 0);
FpOp : in std_logic;
FpLd : in std_logic;
Reset : in std_logic;
fprf_dout1 : in std_logic_vector(63 downto 0);
fprf_dout2 : in std_logic_vector(63 downto 0);
RoundingMode : in std_logic_vector(1 downto 0);
FpBusy : out std_logic;
FracResult : out std_logic_vector(54 downto 3);
ExpResult : out std_logic_vector(10 downto 0);
SignResult : out std_logic;
SNnotDB : out std_logic;
Excep : out std_logic_vector(5 downto 0);
ConditionCodes : out std_logic_vector(1 downto 0);
ss_scan_mode : in std_logic;
fp_ctl_scan_in : in std_logic;
fp_ctl_scan_out : out std_logic
);
end component;
end;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_implication is
constant assert_name : string := "OVL_IMPLICATION";
constant path : string := rtl'path_name;
constant coverage_level_ctrl : ovl_coverage_level := ovl_get_ctrl_val(coverage_level, controls.coverage_level_default);
constant cover_basic : boolean := cover_item_set(coverage_level_ctrl, OVL_COVER_BASIC);
signal reset_n : std_logic;
signal clk : std_logic;
signal fatal_sig : std_logic;
signal antecedent_expr_x01 : std_logic;
signal consequent_expr_x01 : std_logic;
shared variable error_count : natural;
shared variable cover_count : natural;
begin
antecedent_expr_x01 <= to_x01(antecedent_expr);
consequent_expr_x01 <= to_x01(consequent_expr);
------------------------------------------------------------------------------
-- Gating logic --
------------------------------------------------------------------------------
reset_gating : entity work.std_ovl_reset_gating
generic map
(reset_polarity => reset_polarity, gating_type => gating_type, controls => controls)
port map
(reset => reset, enable => enable, reset_n => reset_n);
clock_gating : entity work.std_ovl_clock_gating
generic map
(clock_edge => clock_edge, gating_type => gating_type, controls => controls)
port map
(clock => clock, enable => enable, clk => clk);
------------------------------------------------------------------------------
-- Initialization message --
------------------------------------------------------------------------------
ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate
ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls);
end generate ovl_init_msg_gen;
------------------------------------------------------------------------------
-- Assertion - 2-STATE --
------------------------------------------------------------------------------
ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate
ovl_assert_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(0) <= '0';
elsif ((antecedent_expr_x01 = '1') and (consequent_expr_x01 = '0')) then
fire(0) <= '1';
ovl_error_proc("Antecedent does not have consequent", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(0) <= '0';
end if;
end if;
end process ovl_assert_p;
ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig);
end generate ovl_assert_on_gen;
ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate
fire(0) <= '0';
end generate ovl_assert_off_gen;
------------------------------------------------------------------------------
-- Assertion - X-CHECK --
------------------------------------------------------------------------------
ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
ovl_xcheck_p : process (clk)
begin
if (rising_edge(clk)) then
fatal_sig <= 'Z';
if (reset_n = '0') then
fire(1) <= '0';
elsif ((consequent_expr_x01 = '0') and ovl_is_x(antecedent_expr_x01)) then
fire(1) <= '1';
ovl_error_proc("antecedent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
elsif ((antecedent_expr_x01 = '1') and (ovl_is_x(consequent_expr_x01))) then
fire(1) <= '1';
ovl_error_proc("consequent_expr contains X, Z, U, W or -", severity_level, property_type,
assert_name, msg, path, controls, fatal_sig, error_count);
else
fire(1) <= '0';
end if;
end if;
end process ovl_xcheck_p;
end generate ovl_xcheck_on_gen;
ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate
fire(1) <= '0';
end generate ovl_xcheck_off_gen;
------------------------------------------------------------------------------
-- Coverage --
------------------------------------------------------------------------------
ovl_cover_on_gen : if ((controls.cover_ctrl = OVL_ON) and cover_basic) generate
ovl_cover_p : process (clk)
begin
if (rising_edge(clk)) then
if (reset_n = '0') then
fire(2) <= '0';
elsif (antecedent_expr_x01 = '1') then
fire(2) <= '1';
ovl_cover_proc("antecedent covered", assert_name, path, controls, cover_count);
end if;
end if;
end process ovl_cover_p;
end generate ovl_cover_on_gen;
ovl_cover_off_gen : if ((controls.cover_ctrl = OVL_OFF) or (not cover_basic)) generate
fire(2) <= '0';
end generate ovl_cover_off_gen;
end architecture rtl;
|
-- NEED RESULT: ENT00198: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00198
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00198(ARCH00198)
-- ENT00198_Test_Bench(ARCH00198_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00198 is
generic (G : integer) ;
port (
s_st_int1 : inout st_int1
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00198 ;
--
--
architecture ARCH00198 of ENT00198 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_int1 : inout st_int1
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_int1 : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_int1 <= transport
c_st_int1_2 after 10 ns ;
wait until s_st_int1 =
c_st_int1_2 ;
Test_Report (
"ENT00198",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1 =
c_st_int1_2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
counter := counter + 1;
chk_st_int1 <= transport counter after (1 us - savtime) ;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns;
begin
Proc1 (
s_st_int1
, counter
, correct
, savtime
, chk_st_int1
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00198 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00198_Test_Bench is
end ENT00198_Test_Bench ;
--
--
architecture ARCH00198_Test_Bench of ENT00198_Test_Bench is
begin
L1:
block
signal s_st_int1 : st_int1 := c_st_int1_1 ;
--
--
component UUT
generic (G : integer) ;
port (
s_st_int1 : inout st_int1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00198 ( ARCH00198 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_int1
)
;
end block L1 ;
end ARCH00198_Test_Bench ;
|
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_5 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
--library lib_fifo_v1_0_7;
--use lib_fifo_v1_0_7.lib_fifo_pkg.all;
--use lib_fifo_v1_0_7.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
Constant C_EN_SAFETY_CKT_1 : integer := if_then_else(C_USE_BLOCKMEM = 1,C_EN_SAFETY_CKT,0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal Full_int : std_logic;
signal Almost_full_int : std_logic;
begin --(architecture implementation)
full_gen: if (C_EN_SAFETY_CKT_1 = 1) generate
begin
Full <= Full_int or WR_RST_BUSY;
Almost_full <= Almost_full_int or WR_RST_BUSY;
end generate full_gen;
full_gen1: if (C_EN_SAFETY_CKT_1 = 0) generate
begin
Full <= Full_int;
Almost_full <= Almost_full_int;
end generate full_gen1;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full_int,
almost_full => Almost_full_int,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full_int, -- : OUT std_logic;
almost_full => Almost_full_int, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
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-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
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-- ** expressly prohibited. **
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-- ** done at the users sole risk and will be unsupported. **
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-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
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-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_3
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq" and FAMILY_TO_USE /= "spartan7") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq" or FAMILY_TO_USE = "spartan7") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_5 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
--library lib_fifo_v1_0_7;
--use lib_fifo_v1_0_7.lib_fifo_pkg.all;
--use lib_fifo_v1_0_7.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
Constant C_EN_SAFETY_CKT_1 : integer := if_then_else(C_USE_BLOCKMEM = 1,C_EN_SAFETY_CKT,0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal Full_int : std_logic;
signal Almost_full_int : std_logic;
begin --(architecture implementation)
full_gen: if (C_EN_SAFETY_CKT_1 = 1) generate
begin
Full <= Full_int or WR_RST_BUSY;
Almost_full <= Almost_full_int or WR_RST_BUSY;
end generate full_gen;
full_gen1: if (C_EN_SAFETY_CKT_1 = 0) generate
begin
Full <= Full_int;
Almost_full <= Almost_full_int;
end generate full_gen1;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full_int,
almost_full => Almost_full_int,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full_int, -- : OUT std_logic;
almost_full => Almost_full_int, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** and/or disclosed only pursuant to the terms of a valid **
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-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_3
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq" and FAMILY_TO_USE /= "spartan7") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq" or FAMILY_TO_USE = "spartan7") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_5 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
--library lib_fifo_v1_0_7;
--use lib_fifo_v1_0_7.lib_fifo_pkg.all;
--use lib_fifo_v1_0_7.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
Constant C_EN_SAFETY_CKT_1 : integer := if_then_else(C_USE_BLOCKMEM = 1,C_EN_SAFETY_CKT,0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal Full_int : std_logic;
signal Almost_full_int : std_logic;
begin --(architecture implementation)
full_gen: if (C_EN_SAFETY_CKT_1 = 1) generate
begin
Full <= Full_int or WR_RST_BUSY;
Almost_full <= Almost_full_int or WR_RST_BUSY;
end generate full_gen;
full_gen1: if (C_EN_SAFETY_CKT_1 = 0) generate
begin
Full <= Full_int;
Almost_full <= Almost_full_int;
end generate full_gen1;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full_int,
almost_full => Almost_full_int,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full_int, -- : OUT std_logic;
almost_full => Almost_full_int, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** and/or disclosed only pursuant to the terms of a valid **
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-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
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-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_3
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq" and FAMILY_TO_USE /= "spartan7") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq" or FAMILY_TO_USE = "spartan7") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
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`protect end_protected
|
----------------------------------------------------------------------------------
--
-- Lab session #2: edge detector
--
-- Detects raising edges and ouputs a one-period pulse.
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity edgeDetectorRiseFall is
port( clk: in STD_LOGIC;
reset: in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC;
detected: out STD_LOGIC );
end edgeDetectorRiseFall;
architecture Behavioral of edgeDetectorRiseFall is
begin
process( clk, reset)
variable currentState: STD_LOGIC;
variable previousState: STD_LOGIC;
begin
-- Reset
if reset = '1' then
currentState := '0';
previousState := '0';
detected <= '0';
-- Synchronous behaviour
elsif clk'Event and clk = '1' then
if enable = '1' then
-- Update states
previousState := currentState;
currentState := input;
-- If the current state is different from the previous one,
-- an edge has arrived:
detected <= currentState xor previousState;
end if;
end if;
end process;
end Behavioral;
|
entity repro2 is
end;
architecture behav of repro2 is
type bv_array is array (natural range <>) of bit_vector;
subtype byte_array is bv_array(open)(7 downto 0);
type mrec is record
b : boolean;
data : byte_array;
end record;
signal s : mrec (data(0 to 3));
begin
process
variable a : mrec (data(1 to 4));
begin
s <= a; -- after 1 ns;
wait for 2 ns;
s <= s;
wait;
end process;
end behav;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0);
clock : in std_logic;
a : in std_logic_vector(widthA-1 downto 0);
aclr : in std_logic;
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 16
);
port (
a : in std_logic_vector(16-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector(8-1 downto 0);
clock : in std_logic;
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
begin
alt_dspbuilder_bus_concat_GNWZPLIVXS_0: if ((WIDTHB = 8) and (WIDTHA = 16)) generate
inst_alt_dspbuilder_bus_concat_GNWZPLIVXS_0: alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map(WIDTHB => 8, WIDTHA => 16)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 8) and (WIDTHA = 16)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0);
clock : in std_logic;
a : in std_logic_vector(widthA-1 downto 0);
aclr : in std_logic;
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 16
);
port (
a : in std_logic_vector(16-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector(8-1 downto 0);
clock : in std_logic;
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
begin
alt_dspbuilder_bus_concat_GNWZPLIVXS_0: if ((WIDTHB = 8) and (WIDTHA = 16)) generate
inst_alt_dspbuilder_bus_concat_GNWZPLIVXS_0: alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map(WIDTHB => 8, WIDTHA => 16)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 8) and (WIDTHA = 16)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_7_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_7_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_7_rtl_conf / inst_shadow_7_e
--
configuration inst_shadow_7_rtl_conf of inst_shadow_7_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_7_rtl_conf;
--
-- End of Generated Configuration inst_shadow_7_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end deslocador;
architecture deslocador of deslocador is
begin
c <= a(31 downto 0) when desl = '0' else
'0' & a(31 downto 1) when lado = '0' else
a(30 downto 0) & '0';
cout <= a(30) when lado = '1' and desl = '1' else '0';
end deslocador;
-----------------------------------------------------------------------
--------------------------------MUX A----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1A is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end Mux8x1A;
architecture Mux8x1A of Mux8x1A is
component deslocador
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal temp: std_logic_vector (31 downto 0);
signal tdesl, tz: std_logic;
begin
--seleciona o valor de saída baseado na escolha de entrada XYZ
--as primeiras condições são para operações em lógica booleana
--receberá o valor de A caso seja feita alguma operação algébrica
--ou deslocamento de bits
temp <= a and b when x = '0' and y = '1' and z = '0' else
a nor b when x = '0' and y = '1' and z = '1' else
a or b when x = '1' and y = '0' and z = '0' else a;
--só irá efetuar deslocamento de bits caso xyz = 101 ou 110
tdesl <= '1' when x = '1' and ( ( y = '0' and z = '1') or ( y = '1' and z = '0' ) ) else '0';
--tz armazena o lado para qual será efetuado o deslocamento
tz <= z;
desloc: deslocador port map (temp, tdesl, tz, c, cout);
end Mux8x1A;
-----------------------------------------------------------------------
--------------------------------MUX B----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1B is
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end Mux8x1B;
architecture Mux8x1B of Mux8x1B is
begin
c <= "00000000000000000000000000000000" when (x = '1' or y = '1') else
a when z = '0' else not a;
end Mux8x1B;
-----------------------------------------------------------------------
--------------------------------MUX C----------------------------------
---------------------------comparador----------------------------------
--Identifica se está fazendo subtração para CIN p/ conversão em complemento de 2
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1C is
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end Mux8x1C;
architecture Mux8x1C of Mux8x1C is
begin
c <= '1' when (x = '0' and y = '0' and z = '1') else '0';-- or
-- (x = '1' and y = '1' and z = '0') else '0';
end Mux8x1C;
-----------------------------------------------------------------------
---------------------------COMPONENTE LÓGICO---------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CompLog is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector(31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic; --p/ conversão em complemento de 2
Cout: out std_logic --p/ identificar overflow na multiplicação
);
end CompLog;
architecture CompLog of CompLog is
component Mux8x1A
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
component Mux8x1B
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end component;
component Mux8x1C
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end component;
begin
mux8x1a0: Mux8x1A port map (a, b, x, y, z, ia, Cout);
-- ia <= "01001001";
mux8x1b0: Mux8x1B port map (b, x, y, z, ib);
mux8x1c0: Mux8x1C port map (x, y, z, Cin);
end CompLog;
-----------------------------------------------------------------------
--------------------------SOMADOR 1 BIT--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador1bit is
port (
a: in std_logic;
b: in std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic
);
end somador1bit;
architecture somador1bit of somador1bit is
begin
cout <= (cin and a) or (cin and b) or (a and b);
s <= (not cin and not a and b) or (not cin and a and not b)
or (cin and not a and not b) or (cin and a and b);
end somador1bit;
-----------------------------------------------------------------------
--------------------------SOMADOR 16 BITS-------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador16bits is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end somador16bits;
architecture somador16bits of somador16bits is
component somador1bit
port (
a, b, cin: in std_logic;
s, cout: out std_logic
);
end component;
signal ta, tb, ts: std_logic_vector(31 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16,
c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31: std_logic;
begin
ta <= a;
tb <= b;
s8b0: somador1bit port map (a(0), b(0), cin, ts(0), c0);
s8v1: somador1bit port map (a(1), b(1), c0, ts(1), c1);
s8v2: somador1bit port map (a(2), b(2), c1, ts(2), c2);
s8v3: somador1bit port map (a(3), b(3), c2, ts(3), c3);
s8v4: somador1bit port map (a(4), b(4), c3, ts(4), c4);
s8v5: somador1bit port map (a(5), b(5), c4, ts(5), c5);
s8v6: somador1bit port map (a(6), b(6), c5, ts(6), c6);
s8v7: somador1bit port map (a(7), b(7), c6, ts(7), c7);
s8b8: somador1bit port map (a(8), b(8), c7, ts(8), c8);
s8v9: somador1bit port map (a(9), b(9), c8, ts(9), c9);
s8v10: somador1bit port map (a(10), b(10), c9, ts(10), c10);
s8v11: somador1bit port map (a(11), b(11), c10, ts(11), c11);
s8v12: somador1bit port map (a(12), b(12), c11, ts(12), c12);
s8v13: somador1bit port map (a(13), b(13), c12, ts(13), c13);
s8v14: somador1bit port map (a(14), b(14), c13, ts(14), c14);
s8v15: somador1bit port map (a(15), b(15), c14, ts(15), c15);
s8v16: somador1bit port map (a(16), b(16), c15, ts(16), c16);
s8v17: somador1bit port map (a(17), b(17), c16, ts(17), c17);
s8v18: somador1bit port map (a(18), b(18), c17, ts(18), c18);
s8v19: somador1bit port map (a(19), b(19), c18, ts(19), c19);
s8v20: somador1bit port map (a(20), b(20), c19, ts(20), c20);
s8v21: somador1bit port map (a(21), b(21), c20, ts(21), c21);
s8v22: somador1bit port map (a(22), b(22), c21, ts(22), c22);
s8v23: somador1bit port map (a(23), b(23), c22, ts(23), c23);
s8v24: somador1bit port map (a(24), b(24), c23, ts(24), c24);
s8v25: somador1bit port map (a(25), b(25), c24, ts(25), c25);
s8v26: somador1bit port map (a(26), b(26), c25, ts(26), c26);
s8v27: somador1bit port map (a(27), b(27), c26, ts(27), c27);
s8v28: somador1bit port map (a(28), b(28), c27, ts(28), c28);
s8v29: somador1bit port map (a(29), b(29), c28, ts(29), c29);
s8v30: somador1bit port map (a(30), b(30), c29, ts(30), c30);
s8v31: somador1bit port map (a(31), b(31), c30, ts(31), c31);
--verifica overflow e underflow
cout <= (not a(31) and not b(31) and ts(31)) or (a(31) and b(31) and not ts(31));
s <= ts;
end somador16bits;
-----------------------------------------------------------------------
-----------------------------ULA-PO------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_po is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end ula_po;
architecture ula_po of ula_po is
component CompLog
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector (31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic;
Cout: out std_logic
);
end component;
component somador16bits
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal ia, ib: std_logic_vector(31 downto 0);
signal cin, cout, cout2: std_logic;
begin
complog0: CompLog port map (a, b, x, y, z, ia, ib, cin, cout);
somador8b0: somador16bits port map (ia, ib, cin, s, cout2);
couterro <= cout or cout2;
end ula_po;
-----------------------------------------------------------------------
-----------------------------ULA-PC------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_pc IS
port ( clk, do_op : in std_logic;
done, state: out std_logic
);
end ula_pc;
architecture ula_pc of ula_pc is
constant STDOINGOP: std_logic := '0';
constant STOPDONE: std_logic := '1';
signal st: std_logic;
begin
--espera um ciclo de clock para ter certeza que as operações
--se estabilizaram
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
case st is
when STOPDONE =>
if (do_op = '1') then
st <= STDOINGOP;
end if;
when others =>
st <= STOPDONE;
end case;
end if;
end process;
done <= '1' when st = STOPDONE else '0';
state <= st;
end ula_pc;
-----------------------------------------------------------------------
-------------------------------ULA-------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro, done, state: out std_logic
);
end ula;
architecture ula of ula is
component ula_po
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end component;
component ula_pc
port (
clk, do_op : in std_logic;
done, state: out std_logic
);
end component;
begin
ulapo: ula_po port map (a, b, x, y, z, s, couterro);
ulapc: ula_pc port map (clk, do_op, done, state);
end ula;
|
----------------------------------------------------------------------
-- brdConst_pkg (for EmCraft SoC FG896 Kit)
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Package to declare board specific constants.
--
-- LEDs & PushButton SW polarity XOR constants
-- Handling examples :
-- constant c_lex : std_logic := BRD_LED_POL;
-- constant c_pbx : std_logic := BRD_BTN_POL;
--
-- LED0 <= c_lex xor s_led(0);
-- LED2 <= c_lex; -- force idle LEDs OFF on all boards
-- s_pb1 <= c_pbx xor PB1; -- force '1' only if pressed
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
package brdConst_pkg is
constant BRD_OSC_CLK_MHZ : positive;
constant BRD_LED_POL : std_logic;
constant BRD_BTN_POL : std_logic;
end brdConst_pkg;
----------------------------------------------------------------------
package body brdConst_pkg is
-- Frequency of signal o_clk from brdRstClk to system
constant BRD_OSC_CLK_MHZ : positive := 50_000_000; -- direct
--constant BRD_OSC_CLK_MHZ : positive := 25_000_000; -- divided
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
constant BRD_LED_POL : std_logic := '0';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
constant BRD_BTN_POL : std_logic := '1';
end brdConst_pkg;
----------------------------------------------------------------------
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mul_dw is
generic (
latency : natural := 1;
src1_bits : positive := 32;
src2_bits : positive := 32
);
port (
clk : in std_ulogic;
valid : in std_ulogic;
unsgnd : in std_ulogic;
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src2_bits-1 downto 0);
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0)
);
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:35:50 05/31/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/arp1/arp_tb.vhd
-- Project Name: arp1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: arp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added tests for ARP timeout
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.arp_types.all;
ENTITY arp_tb IS
END arp_tb;
ARCHITECTURE behavior OF arp_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_in_last : std_logic := '0';
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal data_out_ready : std_logic;
signal data_out_valid : std_logic;
signal data_out_first : std_logic;
signal data_out_last : std_logic;
signal data_out : std_logic_vector (7 downto 0);
signal req_count : STD_LOGIC_VECTOR(7 downto 0);
signal arp_req_req : arp_req_req_type;
signal arp_req_rslt : arp_req_rslt_type;
signal mac_tx_req : std_logic;
signal mac_tx_granted : std_logic;
signal control : arp_control_type;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arp generic map (
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing
ARP_TIMEOUT => 20
)
PORT MAP (
-- lookup request mappings
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- rx mappings
data_in_clk => clk,
reset => reset,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- tx mappings
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_clk => clk,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system mappings
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control,
req_count => req_count
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
mac_tx_granted <= '1'; -- FIXME 0
control.clear_cache <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
assert mac_tx_req = '0' report "mac_tx_req asserted on reset";
-- insert stimulus here
arp_req_req.lookup_req <= '0';
arp_req_req.ip <= (others => '0');
data_out_ready <= '1';
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
-- check tx arbitration signals
assert mac_tx_req = '1' report "T1: mac_tx_req not set";
-- ready to tx
data_out_ready <= '1';
mac_tx_granted <= '1';
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*50;
report "T2: Send another ARP request: who has 192.168.5.9? Tell 192.168.5.1, holding off transmitter";
data_out_ready <= '0';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
-- ready to tx
wait for clk_period*10;
data_out_ready <= '1';
wait for clk_period*50;
report "T3 Send a request for the IP that is already cached";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T3: should have got mac";
assert arp_req_rslt.mac = x"00231829267c" report "T3: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T3: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period;
wait for clk_period*10;
wait for clk_period*20;
assert mac_tx_req = '0' report "T3: should not be requesting TX channel";
report "T4: Request 192.168.5.3 (not cached= and Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54";
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T4: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T4: should have got mac";
assert arp_req_rslt.mac = x"021203230454" report "T4: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T4: should not have got err";
wait for clk_period*10;
report "T5: Request 192.168.5.4 (not cached), dont send a reply and wait for timeout";
arp_req_req.ip <= x"c0a80504";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T5: should be requesting TX channel";
wait for clk_period*200;
assert arp_req_rslt.got_mac = '0' report "T5: should not have got mac";
assert arp_req_rslt.got_err = '1' report "T5: should have got err";
report "T6: Request 192.168.5.7 (not cached= and Send an ARP reply: 192.168.5.7 has mac 02:15:03:23:04:54";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T6: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T6: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T6: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T6: should have got mac";
assert arp_req_rslt.mac = x"021503230454" report "T6: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T6: should not have got err";
wait for clk_period*10;
report "T7: Request 192.168.5.7 again an expect it to be in the cache";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T7: should have mac";
assert arp_req_rslt.got_err = '0' report "T7: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
report "T8: Clear the cache, Request 192.168.5.7 again an expect a 'who has' to be sent";
control.clear_cache <= '1';
wait for clk_period;
control.clear_cache <= '0';
wait for clk_period;
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T8: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T8: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T8: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T8: should have got mac";
assert arp_req_rslt.mac = x"021503235554" report "T8: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T8: should not have got err";
wait for clk_period*10;
report "--- end of tests ---";
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc924.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p20n03i00924pkg is
type primary is ( red, green, blue );
end c10s03b00x00p20n03i00924pkg;
ENTITY c10s03b00x00p20n03i00924ent IS
type primary is ( yellow, pink, orange );
END c10s03b00x00p20n03i00924ent;
ARCHITECTURE c10s03b00x00p20n03i00924arch OF c10s03b00x00p20n03i00924ent IS
procedure xxx is
use work.c10s03b00x00p20n03i00924pkg.all;
variable x : work.c10s03b00x00p20n03i00924pkg.primary;
begin
x := red;
assert NOT( x=red )
report "***PASSED TEST: c10s03b00x00p20n03i00924"
severity NOTE;
assert ( x=red )
report "***FAILED TEST: c10s03b00x00p20n03i00924 - A use clause can make a declaration visible and hide a local declaration."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p20n03i00924arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc924.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p20n03i00924pkg is
type primary is ( red, green, blue );
end c10s03b00x00p20n03i00924pkg;
ENTITY c10s03b00x00p20n03i00924ent IS
type primary is ( yellow, pink, orange );
END c10s03b00x00p20n03i00924ent;
ARCHITECTURE c10s03b00x00p20n03i00924arch OF c10s03b00x00p20n03i00924ent IS
procedure xxx is
use work.c10s03b00x00p20n03i00924pkg.all;
variable x : work.c10s03b00x00p20n03i00924pkg.primary;
begin
x := red;
assert NOT( x=red )
report "***PASSED TEST: c10s03b00x00p20n03i00924"
severity NOTE;
assert ( x=red )
report "***FAILED TEST: c10s03b00x00p20n03i00924 - A use clause can make a declaration visible and hide a local declaration."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p20n03i00924arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc924.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s03b00x00p20n03i00924pkg is
type primary is ( red, green, blue );
end c10s03b00x00p20n03i00924pkg;
ENTITY c10s03b00x00p20n03i00924ent IS
type primary is ( yellow, pink, orange );
END c10s03b00x00p20n03i00924ent;
ARCHITECTURE c10s03b00x00p20n03i00924arch OF c10s03b00x00p20n03i00924ent IS
procedure xxx is
use work.c10s03b00x00p20n03i00924pkg.all;
variable x : work.c10s03b00x00p20n03i00924pkg.primary;
begin
x := red;
assert NOT( x=red )
report "***PASSED TEST: c10s03b00x00p20n03i00924"
severity NOTE;
assert ( x=red )
report "***FAILED TEST: c10s03b00x00p20n03i00924 - A use clause can make a declaration visible and hide a local declaration."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s03b00x00p20n03i00924arch;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
----------------------------------------------------------------------------------
-- BRAM8k32bit.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Single Ported RAM, 32bit wide, 8k deep.
--
-- Instantiates 16 BRAM, each being 8k deep and 2 bit wide. These are
-- concatenated to form a 32bit wide, 8k deep RAM.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity BRAM6k36bit is
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end BRAM6k36bit;
architecture Behavioral of BRAM6k36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
--signal WEB : std_logic_vector(2**(ADDR'length-9)-1 downto 0);
signal WEB : std_logic_vector(11 downto 0);
begin
-- BlockRAMS: for i in 0 to 11 generate
-- RAMB16_S2_inst : RAMB16_S2
-- generic map (
-- INIT => X"0", -- Value of output RAM registers at startup
-- SRVAL => X"0", -- Ouput value upon SSR assertion
-- WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- )
-- port map (
-- DO => DOUT(2*i+1 downto 2*i), -- 2-bit Data Output
-- ADDR => ADDR, -- 13-bit Address Input
-- CLK => CLK, -- Clock
-- DI => DIN(2*i+1 downto 2*i), -- 2-bit Data Input
-- EN => '1', -- RAM Enable Input
-- SSR => '0', -- Synchronous Set/Reset Input
-- WE => WE -- Write Enable Input
-- );
-- end generate;
BlockRAMS: for i in 0 to 11 generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
--------------------------------------------------------------------------
-- Version 2.0 (lpm 220) Date 01/04/00
--
-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
-- read in values from LPM_FILE (*.hex) when the DATA width is greater
-- than 16 bits.
-- 2. Explicit sign conversions are added to standard logic vector
-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
-- LPM_COMPARE.
-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
-- 5. Fixed LPM_DIVIDE to divide correctly.
--------------------------------------------------------------------------
-- Version 1.9 (lpm 220) Date 11/30/99
--
-- 1. Fixed UNUSED file not found problem and initialization problem
-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
-- 2. Fixed LPM_MULT when SUM port is not used.
-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
-- at the same time.
-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
-- and counter is incrementing.
-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
-- simulating LPM_COUNTER.
--------------------------------------------------------------------------
-- Version 1.8 (lpm 220) Date 10/25/99
--
-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
-- changes.
--------------------------------------------------------------------------
-- Version 1.7 (lpm 220) Date 07/13/99
--
-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
-- Quartus behaviour and LPM220-compliant behaviour.
--------------------------------------------------------------------------
-- Version 1.6 (lpm 220) Date 06/15/99
--
-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
-- comply with the specfication.
-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
-- LPM_FIFO_DC; they are all initialized to 0's.
--------------------------------------------------------------------------
-- Version 1.5 (lpm 220) Date 05/10/99
--
-- Changed LPM_MODULUS from string type to integer.
--------------------------------------------------------------------------
-- Version 1.4 (lpm 220) Date 02/05/99
--
-- 1. Added LPM_DIVIDE module.
-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
-- and LPM_COMPARE
-- 3. Replaced the constants holding string with the actual string.
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_FSM and LPM_TTABLE
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
use std.textio.all;
entity LPM_RAM_DQ is
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when 'A' =>
digit := 10;
when 'a' =>
digit := 10;
when 'B' =>
digit := 11;
when 'b' =>
digit := 11;
when 'C' =>
digit := 12;
when 'c' =>
digit := 12;
when 'D' =>
digit := 13;
when 'd' =>
digit := 13;
when 'E' =>
digit := 14;
when 'e' =>
digit := 14;
when 'F' =>
digit := 15;
when 'f' =>
digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l, stmp);
end if;
end;
end LPM_RAM_DQ;
architecture LPM_SYN of lpm_ram_dq is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0);
signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
signal we_tmp, we_reg : std_logic;
begin
sync: process(data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
else
address_tmp <= address;
we_tmp <= we;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
else
data_tmp <= data;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
else
q <= q_tmp;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
memory: process(data_tmp, we_tmp, address_tmp)
variable mem_data : lpm_memory;
variable mem_data_tmp : integer := 0;
variable mem_init: boolean := false;
variable i,j,k,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE unused_file: TEXT IS OUT "UNUSED";
FILE mem_data_file: TEXT IS IN LPM_FILE;
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE = "UNUSED") then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY WARNING;
else
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
shrink_line(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := hex_str_to_int(byte);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length);
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := hex_str_to_int(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
else
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_tmp := 0;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
end loop;
i := i + k;
mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + hex_str_to_int(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
end loop;
ibase := ibase * 16;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if we_tmp = '1' then
mem_data (to_integer(unsigned(address_tmp))) := data_tmp;
end if;
q_tmp <= mem_data(to_integer(unsigned(address_tmp)));
end process;
end LPM_SYN;
-- pragma translate_off
configuration lpm_ram_dq_c0 of lpm_ram_dq is
for lpm_syn
end for;
end lpm_ram_dq_c0;
-- pragma translate_on
|
--------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
--------------------------------------------------------------------------
-- Version 2.0 (lpm 220) Date 01/04/00
--
-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
-- read in values from LPM_FILE (*.hex) when the DATA width is greater
-- than 16 bits.
-- 2. Explicit sign conversions are added to standard logic vector
-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
-- LPM_COMPARE.
-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
-- 5. Fixed LPM_DIVIDE to divide correctly.
--------------------------------------------------------------------------
-- Version 1.9 (lpm 220) Date 11/30/99
--
-- 1. Fixed UNUSED file not found problem and initialization problem
-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
-- 2. Fixed LPM_MULT when SUM port is not used.
-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
-- at the same time.
-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
-- and counter is incrementing.
-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
-- simulating LPM_COUNTER.
--------------------------------------------------------------------------
-- Version 1.8 (lpm 220) Date 10/25/99
--
-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
-- changes.
--------------------------------------------------------------------------
-- Version 1.7 (lpm 220) Date 07/13/99
--
-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
-- Quartus behaviour and LPM220-compliant behaviour.
--------------------------------------------------------------------------
-- Version 1.6 (lpm 220) Date 06/15/99
--
-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
-- comply with the specfication.
-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
-- LPM_FIFO_DC; they are all initialized to 0's.
--------------------------------------------------------------------------
-- Version 1.5 (lpm 220) Date 05/10/99
--
-- Changed LPM_MODULUS from string type to integer.
--------------------------------------------------------------------------
-- Version 1.4 (lpm 220) Date 02/05/99
--
-- 1. Added LPM_DIVIDE module.
-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
-- and LPM_COMPARE
-- 3. Replaced the constants holding string with the actual string.
--------------------------------------------------------------------------
-- Version 1.3 Date 07/30/96
--
-- Modification History
--
-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
-- and LPM_PVALUE
--
-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
--------------------------------------------------------------------------
-- Excluded Functions:
--
-- LPM_FSM and LPM_TTABLE
--
--------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
use std.textio.all;
entity LPM_RAM_DQ is
generic (LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
function int_to_str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function hex_str_to_int( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in len downto 1 loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when 'A' =>
digit := 10;
when 'a' =>
digit := 10;
when 'B' =>
digit := 11;
when 'b' =>
digit := 11;
when 'C' =>
digit := 12;
when 'c' =>
digit := 12;
when 'D' =>
digit := 13;
when 'd' =>
digit := 13;
when 'E' =>
digit := 14;
when 'e' =>
digit := 14;
when 'F' =>
digit := 15;
when 'f' =>
digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal character "& str(i) & "in Intel Hex File! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
procedure Shrink_line(L : inout LINE; pos : in integer) is
subtype nstring is string(1 to pos);
variable stmp : nstring;
begin
if pos >= 1 then
read(l, stmp);
end if;
end;
end LPM_RAM_DQ;
architecture LPM_SYN of lpm_ram_dq is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0);
signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
signal we_tmp, we_reg : std_logic;
begin
sync: process(data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
else
address_tmp <= address;
we_tmp <= we;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
else
data_tmp <= data;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
else
q <= q_tmp;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
memory: process(data_tmp, we_tmp, address_tmp)
variable mem_data : lpm_memory;
variable mem_data_tmp : integer := 0;
variable mem_init: boolean := false;
variable i,j,k,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE unused_file: TEXT IS OUT "UNUSED";
FILE mem_data_file: TEXT IS IN LPM_FILE;
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE = "UNUSED") then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY WARNING;
else
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
shrink_line(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := hex_str_to_int(byte);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length);
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := hex_str_to_int(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
else
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_tmp := 0;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
end loop;
i := i + k;
mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + hex_str_to_int(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
end loop;
ibase := ibase * 16;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if we_tmp = '1' then
mem_data (to_integer(unsigned(address_tmp))) := data_tmp;
end if;
q_tmp <= mem_data(to_integer(unsigned(address_tmp)));
end process;
end LPM_SYN;
-- pragma translate_off
configuration lpm_ram_dq_c0 of lpm_ram_dq is
for lpm_syn
end for;
end lpm_ram_dq_c0;
-- pragma translate_on
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_ch_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity ch_09_03 is
end entity ch_09_03;
----------------------------------------------------------------
architecture test of ch_09_03 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_09_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_09_2_b;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_ch_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity ch_09_03 is
end entity ch_09_03;
----------------------------------------------------------------
architecture test of ch_09_03 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_09_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_09_2_b;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_ch_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package system_types is
-- code from book
type system_status is (idle, active, overloaded);
-- end code from book
end package system_types;
entity ch_09_03 is
end entity ch_09_03;
----------------------------------------------------------------
architecture test of ch_09_03 is
-- code from book
alias status_type is work.system_types.system_status;
-- end code from book
begin
process_09_2_b : process is
variable status : status_type := idle;
begin
wait for 10 ns;
status := active;
wait for 10 ns;
status := overloaded;
wait;
end process process_09_2_b;
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
cos : out std_logic_vector(7 downto 0);
sin : out std_logic_vector(7 downto 0));
end top;
architecture rtl of top is
--
signal reset_reg : std_logic;
signal pre_cos, pre_sin : std_logic_vector(7 downto 0);
--
attribute dont_touch : string;
attribute dont_touch of reset_reg : signal is "true";
attribute dont_touch of pre_cos : signal is "true";
attribute dont_touch of pre_sin : signal is "true";
--
begin
regs_proc: process
begin
wait until rising_edge(clk);
reset_reg <= reset;
cos <= pre_cos;
sin <= pre_sin;
end process;
uut: entity work.chirp_gen
port map (
clk => clk,
reset => reset_reg,
cos => pre_cos,
sin => pre_sin);
end rtl;
|
-------------------------------------------------------------------------------
-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $
-------------------------------------------------------------------------------
configuration ram_loader_rtl_c0 of ram_loader is
for rtl
end for;
end ram_loader_rtl_c0;
|
--! @file trig_table_ea.vhd
--! @brief sin/cos lookup table generator
--! @author Scott Teal ([email protected])
--! @date 2013-09-30
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
use work.util_pkg.all;
--! Sin & Cos lookup table.
--! Outputs cos(2*pi*angle) and sin(2*pi*angle), where 0 <= angle < 1. By
--! default, it uses a quarter-wave table lookup. This uses up 1/4 the memory of
--! a full lookup table with no loss in fidelity, provided that the number of
--! output fractional bits is at least twice the number of fraction angle bits
--! plus 5.
--!
--!
--! ## Quarter Wave Lookup Table Details ##
--!
--! For quarter-wave table, the assumption that needs to hold is:
--! sine'low > 2*angle'low + 5.3030
--!
--! In fractional bits, this is: # fractional sine bits < 2*(angle bits) - 5.3030
--! Simple Table of Requirement:
--!
--! | angle'low | min sin'low |
--! | -5 | -4 |
--! | -6 | -6 |
--! | -7 | -8 |
--! | -8 | -10 |
--! | -9 | -12 |
--! | -10 | -14 |
--! | -11 | -16 |
--! | -12 | -18 |
--! | -13 | -20 |
--! | -14 | -22 |
--! | -15 | -24 |
--!
--! Derivation:
--! The quarter-wave sine table implementation does not work if the delta
--! between angle=0.25 and angle=0.25+LSB creates a difference greater than 1/2
--! the LSB value of the output. If it is greater, then the sine table will
--! never output 1.0 for sin(pi/2), cos(0), etc.
--! This can be expressed as 1-cos(2*pi*2^-n) < 2^(-m-1), where n is the number
--! of fractional angle bits, and m is the number of fractional output bits.
--! Using the small-angle approximation cos(x) = 1 - x^2/2 and simplifying, we
--! get the resultant equation m < 2*n - log2(pi^2) - 2, or m < 2*n - 5.3030.
--!
entity trig_table is
generic (
QUARTER_WAVE : boolean := true --! Use quarter-wave table
);
port (
clk : in std_logic; --! Clock line
rst : in std_logic; --! Reset Line
angle : in ufixed; --! Normalized angle (0 <= angle < 1)
sine : out sfixed; --! sin(2*pi*angle)
cosine : out sfixed --! cos(2*pi*angle)
);
end entity;
--! Uses two lookup tables to find sin & cos. Future version will use
--! quarter-wave lookup tables as default.
architecture rtl of trig_table is
--! Function for generating sine lookup table
function sine_table (angle_width : natural; sine_high, sine_low : integer) return sfixed_vector is
--! Size of lookup table - 1
constant table_high : positive := 2**angle_width - 1;
--! Working copy of lookup table to return
variable table : sfixed_vector(table_high downto 0)
(sine_high downto sine_low);
--! Working value of sine to convert for lookup table
variable sine_real : real;
begin
for i in 0 to table_high loop
sine_real := sin(math_2_pi * (real(i) / real(table_high + 1)));
table(i) := to_sfixed(sine_real, sine_high, sine_low);
end loop;
return table;
end function;
--! Function for generating cosine lookup table
function cosine_table (angle_width : natural; cosine_high, cosine_low : integer) return sfixed_vector is
--! Size of lookup table - 1
constant table_high : positive := 2**angle_width - 1;
--! Working copy of lookup table to return
variable table : sfixed_vector(table_high downto 0)
(cosine_high downto cosine_low);
--! Working value of cosine to convert for lookup table
variable cosine_real : real;
begin
for i in 0 to table_high loop
cosine_real := cos(math_2_pi * (real(i) / real(table_high + 1)));
table(i) := to_sfixed(cosine_real, cosine_high, cosine_low);
end loop;
return table;
end function;
--! Function for generating quarter-wave sine lookup table
function quarter_sine_table (angle_width : natural; sine_high, sine_low : integer) return ufixed_vector is
--! Size of lookup table - 1
constant table_high : positive := 2**(angle_width-2) - 1;
--! Working copy of lookup table to return
variable table : ufixed_vector(table_high downto 0)
(sine_high-1 downto sine_low);
--! Working value of sine to convert for lookup table
variable sine_real : real;
begin
for i in 0 to table_high loop
sine_real := sin(math_2_pi * (real(i) / real(table_high + 1)));
table(i) := to_ufixed(sine_real, sine_high-1, sine_low);
end loop;
return table;
end function;
--! Total width of useful angle bits (-1 downto angle'low)
constant angle_width : positive := 0 - angle'low;
constant sine_lookup_table : sfixed_vector := sine_table(angle_width, sine'high, sine'low);
constant cosine_lookup_table : sfixed_vector := cosine_table(angle_width, cosine'high, cosine'low);
constant quarter_sine_lookup_table : sfixed_vector := quarter_sine_table(angle_width,
max(sine'high, cosine'high),
minimum(sine'low, cosine'low));
--! std_logic_vector version of angle for lookup table
signal lookup_bits : std_logic_vector((angle_width - 1) downto 0);
begin
--! State assumptions
assert (angle'low < 0)
report "Angle to trig table should be a fraction from 0 to 1"
severity warning;
assert (angle'high < 0)
report "Any integer bits in the input angle will be unused"
severity warning;
assert (sine'high < 2)
report "Sine will range from 1 to -1; more integer bits not necessary"
severity warning;
assert (cosine'high < 2)
report "Sine will range from 1 to -1; more integer bits not necessary"
severity warning;
assert (minimum(sine'low,cosine'low) > (2*angle'low + 5))
report "Quarter wave table will never return 1.0"
severity warning;
--! Casts the ufixed angle value as a std_logic_vector for the lookup table.
--! @todo There's got to be a more elegant way of doing this.
--! remap_lookup_bits : for i in lookup_bits'range generate
--! lookup_bits(i) <= std_logic(angle(i - angle_width));
--! end generate;
lookup_bits <= to_slv(angle);
--! Pipeline to look up values
data_pipeline : process (clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
sine <= to_sfixed(0.0, sine);
cosine <= to_sfixed(0.0, cosine);
else
if (not QUARTER_WAVE) then
sine <= sine_lookup_table(to_integer(unsigned(lookup_bits)));
cosine <= cosine_lookup_table(to_integer(unsigned(lookup_bits)));
else
case (lookup_bits(lookup_bits'high downto (lookup_bits'high-1))) is
when b"00" =>
sine <= sine_lookup_table(to_integer(unsigned(
lookup_bits((lookup_bits'high-2) downto 0))));
cosine <= cosine_lookup_table(to_integer(unsigned(
not lookup_bits((lookup_bits'high-2) downto 0))));
when b"01" =>
sine <= sine_lookup_table(to_integer(unsigned(
not lookup_bits((lookup_bits'high-2) downto 0))));
cosine <= -cosine_lookup_table(to_integer(unsigned(
lookup_bits((lookup_bits'high-2) downto 0))));
when b"10" =>
sine <= -sine_lookup_table(to_integer(unsigned(
lookup_bits((lookup_bits'high-2) downto 0))));
cosine <= -cosine_lookup_table(to_integer(unsigned(
not lookup_bits((lookup_bits'high-2) downto 0))));
when b"11" =>
sine <= -sine_lookup_table(to_integer(unsigned(
not lookup_bits((lookup_bits'high-2) downto 0))));
cosine <= cosine_lookup_table(to_integer(unsigned(
lookup_bits((lookup_bits'high-2) downto 0))));
when others =>
sine <= to_sfixed(0.0, sine);
cosine <= to_sfixed(0.0, cosine);
end case;
end if;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN;
end Logic; |
--This should pass
context c1 is
end context c1;
--This should fail
context c1 is
end context c1;
context c1 is
end context c1;
context c1 is
end context c1;
-- This should pass
context c1 is
end context ;
-- Split declaration across lines
context
c1
is
end
context
c1
;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
---------------------------------------------------------------------------
-- Package TEXTIO as defined in Chapter 14 of the IEEE Standard VHDL
-- Language Reference Manual (IEEE Std. 1076-1987), as modified
-- by the Issues Screening and Analysis Committee (ISAC), a subcommittee
-- of the VHDL Analysis and Standardization Group (VASG) on
-- 10 November, 1988. See "The Sense of the VASG", October, 1989.
---------------------------------------------------------------------------
-- Version information: %W% %G%
---------------------------------------------------------------------------
package TEXTIO is
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
-- changed for vhdl92 syntax:
file input : TEXT open read_mode is "STD_INPUT";
file output : TEXT open write_mode is "STD_OUTPUT";
-- changed for vhdl92 syntax (and now a built-in):
procedure READLINE(file f: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
-- changed for vhdl92 syntax (and now a built-in):
procedure WRITELINE(file f : TEXT; L : inout LINE);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
-- is implicit built-in:
-- function ENDFILE(file F : TEXT) return boolean;
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
--
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
end;
|
-------------------------------------------------------------------------------
-- axi_master_lite_reset.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_master_lite_reset.vhd
--
-- Description:
--
-- This VHDL file implements the reset module for the AXI Master lite.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_lite_reset.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.1 $
-- Date: $12/01/2010$
--
-- History:
-- DET 12/01/2010 Initial Version
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_lite_reset is
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
axi_aresetn : in std_logic ;
-----------------------------------------------------------------------
-- IPIC Reset Input
-----------------------------------------------------------------------
ip2bus_mst_reset : In std_logic ;
-----------------------------------------------------------------------
-- Combined Reset Output
-----------------------------------------------------------------------
rst2ip_reset_out : out std_logic
);
end entity axi_master_lite_reset;
architecture implementation of axi_master_lite_reset is
-- Signals
signal sig_axi_reset : std_logic := '0';
signal sig_ipic_reset : std_logic := '0';
signal sig_combined_reset : std_logic := '0';
begin --(architecture implementation)
-- Assign the output port
rst2ip_reset_out <= sig_combined_reset;
-- Generate an active high combined reset from the
-- axi reset input and the IPIC reset input
sig_axi_reset <= not(axi_aresetn);
sig_ipic_reset <= ip2bus_mst_reset;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RST_REG
--
-- Process Description:
-- Implements the register for the combined reset output.
--
-------------------------------------------------------------
IMP_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_reset = '1') then
sig_combined_reset <= '1';
else
sig_combined_reset <= sig_axi_reset or sig_ipic_reset;
end if;
end if;
end process IMP_RST_REG;
end implementation;
|
library verilog;
use verilog.vl_types.all;
entity select2_5 is
port(
in1 : in vl_logic_vector(4 downto 0);
in2 : in vl_logic_vector(4 downto 0);
choose : in vl_logic;
\out\ : out vl_logic_vector(4 downto 0)
);
end select2_5;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(6 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is
signal tmp_product : std_logic_vector(14 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(6 - 1 downto 0);
signal p_tmp : std_logic_vector(14 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
tmp_product <= std_logic_vector(resize(unsigned(a_i) * unsigned(b_i), 14));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
p_tmp <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 is
component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1_U : component nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
--
-- Ken Chapman - Xilinx Ltd.
--
-- 20th August 2014 - Initial version for KC705 board using Vivado 2014.2
--
--
-- INTRODUCTION
--
-- The primary purpose of this reference design is to show how KCPSM6 can communicate with
-- the Internal Configuration Access Port (ICAPE2) inside a 7-Series device. Some specific
-- interfacing defined in this file is required to facilitate fundamental communication and
-- then all transactions are implemented by KCPSM6. Please see the descriptions contained
-- in the PSM files for more details concerning the various transactions.
--
-- The code presented implements a reasonable set of operations and should provide adequate
-- reference material for those wanting to implement other procedures (e.g. MultiBoot
-- schemes also require interaction with the configuration registers and KCPSM6 would be
-- and idea way to implement the ICAP communication as well as the MultiBoot control).
-- Please refer to the '7 Series FPGA Configuration User Guide' (UG470) for more details.
-- Although this reference design is not intended to be a definitive description of how
-- ICAP transactions are implemented, the fact that this is a known good working example
-- can help to add 'colour' to the official documentation!
--
-- The design shows the ability to read and write configuration registers. It also shows
-- how to read and write complete frames of configuration memory. Note that YOU are
-- RESPONSIBLE for the consequences of any modifications that you make to the configuration
-- of a live device.
--
-- Due to the size of a configuration frame, a BRAM has also been connected to KCPSM6 to
-- provide a 4096 bytes of RAM storage. Although this design only needs to use some of that
-- space, this is also a useful reference example for reuse in other applications.
--
-- This design should also be useful for those interested in Soft Error Upsets (SEU). The
-- 7-Series devices have built-in Readback CRC circuits for the detection of SEU as well
-- as built-in error correction circuits. The features implemented by KCPSM6 in this design
-- can enable you to enable and disable these built-in features, monitor their behaviour
-- and inject configuration errors to test them and your designs (i.e. modify configuration
-- in the way that an SEU might do). Note that Xilinx provide the Soft Error Mitigation
-- (SEM) IP core which you should also investigate (see PG036). However, even users of this
-- core could find it useful to experiment with this design. For example, this design can
-- generate a complete 'memory map' of the Readback CRC scan of a device.
--
-- This design is based on the 'uart6_kc705.vhd' reference design provided in the KCPSM6
-- package. Please see the 'UART_and_PicoTerm' section for documentation and code
-- containing longer descriptions and educational code relating to the UART communications.
-- In this case, the design has been set to operate with a clock frequency of 100MHz and
-- KCPSM6 then determines the clock division factor required to implement UART
-- communication at 115200 BAUD.
--
-- The KC705 board provides a 200MHz clock to the Kintex-7 device. The maximum clock
-- frequency that can be applied to ICAPE2 is 100MHz so in this design the 200HMz is
-- divided by two to form a 100MHz clock that is distributed to all circuits. The
-- 'clock_frequency_in_MHz' constant has been set to 100 and is read by KCPSM6 which
-- uses this information to define a UART communication BAUD rate of 115200.
--
-- Whilst the design is presented as a working example for the XC7K325TFFG900-2 device on
-- the KC705 Evaluation Board (www.xilinx.com) it could be used with any 7-Series device.
--
-- Please note that PicoTerm must be used with this design. KCPSM6 makes use of some
-- unique PicoTerm features such as being able to open a LOG file.
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
--
entity kc705_kcpsm6_icap is
Port ( uart_rx : in std_logic;
uart_tx : out std_logic;
cpu_rst : in std_logic;
led : out std_logic_vector(7 downto 0);
clk200_p : in std_logic;
clk200_n : in std_logic);
end kc705_kcpsm6_icap;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of kc705_kcpsm6_icap is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- Development Program Memory
--
component icap_control
generic( C_FAMILY : string := "7S";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
component uart_tx6
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx6
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- 4096 x 8-bit RAM
--
component ram_4096x8 is
Port ( address : in std_logic_vector(11 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
--
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
--
-- Signals used to create 100MHz clock from 200MHz differential clock
--
signal clk200 : std_logic;
signal clk100 : std_logic := '0';
signal clk : std_logic;
--
-- Constant to specify the clock frequency in megahertz.
--
constant clock_frequency_in_MHz : integer range 0 to 255 := 100;
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
-- Signals used to connect UART_TX6
--
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_logic;
signal uart_tx_data_present : std_logic;
signal uart_tx_half_full : std_logic;
signal uart_tx_full : std_logic;
signal uart_tx_reset : std_logic;
--
-- Signals used to connect UART_RX6
--
signal uart_rx_data_out : std_logic_vector(7 downto 0);
signal read_from_uart_rx : std_logic := '0';
signal uart_rx_data_present : std_logic;
signal uart_rx_half_full : std_logic;
signal uart_rx_full : std_logic;
signal uart_rx_reset : std_logic;
--
-- Signals used to define baud rate
--
signal set_baud_rate : std_logic_vector(7 downto 0) := "00000000";
signal baud_rate_counter : std_logic_vector(7 downto 0) := "00000000";
signal en_16_x_baud : std_logic := '0';
--
-- Signals used to connect 4096 Byte RAM
--
signal ram_address : std_logic_vector(11 downto 0) := "000000000000";
signal ram_data_in : std_logic_vector(7 downto 0);
signal ram_we : std_logic;
signal ram_data_out : std_logic_vector(7 downto 0);
--
--
-- Signals to interface with ICAPE2
--
signal icap_i : std_logic_vector(31 downto 0);
signal icap_o : std_logic_vector(31 downto 0);
signal icap_csib : std_logic := '1';
signal icap_rdwrb : std_logic := '0';
signal icap_din : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
signal enable_icap : std_logic := '1';
signal icap_o_reg : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal icap_csib_dly1 : std_logic := '1';
signal icap_csib_dly2 : std_logic := '1';
signal icap_o_reg_en : std_logic := '0';
signal icap_dout : std_logic_vector(31 downto 0);
--
-- Signals to interface with FRAME_ECCE2
--
signal frame_ecc_crcerr : std_logic;
signal frame_ecc_eccerr : std_logic;
signal frame_ecc_eccerrsingle : std_logic;
signal frame_ecc_far : std_logic_vector(25 downto 0);
signal frame_ecc_synbit : std_logic_vector(4 downto 0);
signal frame_ecc_syndrome : std_logic_vector(12 downto 0);
signal frame_ecc_syndromevalid : std_logic;
signal frame_ecc_synword : std_logic_vector(6 downto 0);
--
-- signals to monitor Readback CRC scanning activity
--
signal scan_counter : std_logic_vector(7 downto 0) := "00000000";
signal end_of_scan : std_logic := '0';
signal end_of_frame : std_logic := '0';
--
signal syndrome_counter : std_logic_vector(23 downto 0) := "000000000000000000000000";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
--
-----------------------------------------------------------------------------------------
-- Create 100MHz clock from 200MHz differential clock
-----------------------------------------------------------------------------------------
--
-- The maximum clock frequency that can be applied to ICAP is 100MHz. To simplify all
-- communication with ICAP, all circuits including KCPSM6 will be operated at 100MHz.
-- This single clock, fully synchronous arrangement will also ensure reliable operation.
--
--
-- Receive the 200MHz differential clock from the oscillator on the board.
--
diff_clk_buffer: IBUFGDS
port map ( I => clk200_p,
IB => clk200_n,
O => clk200);
--
-- In this case a simple 1-bit toggle flip-flop is used to divide the clock by two
-- which is then distributed by a global clock buffer. Just like the physical external
-- 200MHz oscillator, this internally generated 100MHz has no particular phase
-- relationship with any of the input or outputs signals of the design. As such, there
-- was no reason to expend an MMCM to implement such a simple clock division although
-- one could be used if it were desirable for multiple clocks to have a defined phase
-- relationship.
--
clock_generation: process(clk200)
begin
if clk200'event and clk200 = '1' then
clk100 <= not(clk100);
end if;
end process clock_generation;
--
-- BUFG used to reach the entire device with 100MHz
--
buffer100: BUFG
port map ( I => clk100,
O => clk);
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter.
--
processor: kcpsm6
generic map ( hwbuild => X"41", -- 41 hex is ASCII Character "A"
interrupt_vector => X"FFF",
scratch_pad_memory_size => 256)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
--
-- Reset by press button or JTAG Loader enabled Program Memory
--
kcpsm6_reset <= rdl or cpu_rst;
--
-- Unused signals tied off until required.
-- Tying to other signals used to minimise warning messages.
--
kcpsm6_sleep <= write_strobe and k_write_strobe; -- Always '0'
interrupt <= interrupt_ack;
--
-- Development Program Memory
-- JTAG Loader enabled for rapid code development.
--
program_rom: icap_control
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 4,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Transmitter with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Write to buffer in UART Transmitter at port address 01 hex
--
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => uart_tx_data_present,
buffer_half_full => uart_tx_half_full,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Receiver with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Read from buffer in UART Receiver at port address 01 hex.
--
-- When KCPMS6 reads data from the receiver a pulse must be generated so that the
-- FIFO buffer presents the next character to be read and updates the buffer flags.
--
rx: uart_rx6
port map ( serial_in => uart_rx,
en_16_x_baud => en_16_x_baud,
data_out => uart_rx_data_out,
buffer_read => read_from_uart_rx,
buffer_data_present => uart_rx_data_present,
buffer_half_full => uart_rx_half_full,
buffer_full => uart_rx_full,
buffer_reset => uart_rx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART baud rate
-----------------------------------------------------------------------------------------
--
-- The baud rate is defined by the frequency of 'en_16_x_baud' pulses. These should occur
-- at 16 times the desired baud rate. KCPSM6 computes and sets an 8-bit value into
-- 'set_baud_rate' which is used to divide the clock frequency appropriately.
--
-- For example, if the clock frequency is 200MHz and the desired serial communication
-- baud rate is 115200 then PicoBlaze will set 'set_baud_rate' to 6C hex (108 decimal).
-- This circuit will then generate an 'en_16_x_baud' pulse once every 109 clock cycles
-- (note that 'baud_rate_counter' will include state zero). This would actually result
-- in a baud rate of 114,679 baud but that is only 0.45% low and well within limits.
--
baud_rate: process(clk)
begin
if clk'event and clk = '1' then
if baud_rate_counter = set_baud_rate then
baud_rate_counter <= "00000000";
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_rate_counter <= baud_rate_counter + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
--
-----------------------------------------------------------------------------------------
-- 4096 x 8-bit RAM
-----------------------------------------------------------------------------------------
--
ram: ram_4096x8
port map ( address => ram_address,
data_in => ram_data_in,
data_out => ram_data_out,
we => ram_we,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
input_ports: process(clk)
begin
if clk'event and clk = '1' then
case port_id(4 downto 0) is
-- Read UART status at port address 00 hex
when "00000" => in_port(0) <= uart_tx_data_present;
in_port(1) <= uart_tx_half_full;
in_port(2) <= uart_tx_full;
in_port(3) <= uart_rx_data_present;
in_port(4) <= uart_rx_half_full;
in_port(5) <= uart_rx_full;
-- Read UART_RX6 data at port address 01 hex
-- (see 'buffer_read' pulse generation below)
when "00001" => in_port <= uart_rx_data_out;
-- Read clock frequency contant at port address 02 hex
when "00010" => in_port <= conv_std_logic_vector(clock_frequency_in_MHz, 8);
-- Read 32-bit data from ICAPE2 at addresses 04, 05, 06 and 07 hex
when "00100" => in_port <= icap_dout(7 downto 0);
when "00101" => in_port <= icap_dout(15 downto 8);
when "00110" => in_port <= icap_dout(23 downto 16);
when "00111" => in_port <= icap_dout(31 downto 24);
-- Read status signals from FRAME_ECCE2 at port addresse 08 hex
-- (Only 'crcerr' is currently used in the KCPSM6 program provided)
when "01000" => in_port(0) <= frame_ecc_crcerr; -- device CRC error
in_port(1) <= frame_ecc_eccerr; -- frame ECC error
in_port(2) <= frame_ecc_eccerrsingle; -- single bit error detected
in_port(3) <= frame_ecc_syndromevalid; -- syndrome output is valid
-- Read 7-bit syndrome word from FRAME_ECCE2 at port addresse 09 hex
-- (Not currently used in the KCPSM6 program provided)
when "01001" => in_port(6 downto 0) <= frame_ecc_synword; -- word address of error
-- Read 5-bit syndrome bit from FRAME_ECCE2 at port addresse 0A hex
-- (Not currently used in the KCPSM6 program provided)
when "01010" => in_port(4 downto 0) <= frame_ecc_synbit; -- bit address of error
-- Read 13-bit syndrome from FRAME_ECCE2 at ports addresse 0C and 0D hex
-- (Not currently used in the KCPSM6 program provided)
when "01100" => in_port(7 downto 0) <= frame_ecc_syndrome(7 downto 0);
when "01101" => in_port(4 downto 0) <= frame_ecc_syndrome(12 downto 8);
-- Read 26-bit Frame Address from FRAME_ECCE2 at port addresses 10, 11, 12 and 13 hex
when "10000" => in_port(7 downto 0) <= frame_ecc_far(7 downto 0);
when "10001" => in_port(7 downto 0) <= frame_ecc_far(15 downto 8);
when "10010" => in_port(7 downto 0) <= frame_ecc_far(23 downto 16);
when "10011" => in_port(1 downto 0) <= frame_ecc_far(25 downto 24);
-- Read the RAM at the defined 'ram_address' at port address 14 hex.
when "10100" => in_port <= ram_data_out;
-- Read 'end_of_frame' and 'end_of_scan' pulse at port address 15 hex
when "10101" => in_port(0) <= end_of_scan;
in_port(1) <= end_of_frame;
-- Specify don't care for all other inputs to obtain optimum implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Generate 'buffer_read' pulse following read of UART data from port address 01
if (read_strobe = '1') and (port_id(4 downto 0) = "00001") then
read_from_uart_rx <= '1';
else
read_from_uart_rx <= '0';
end if;
end if;
end process input_ports;
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
-- Note that the assignment and decoding of 'port_id' is a mixture of one-hot and
-- encoded resulting in the minimum number of signals actually being decoded for a
-- fast and optimum implementation.
--
-- Port port_id Purpose
--
-- 01 xxxx x0x1 Write to UART
-- 02 xxxx x01x Set BAUD rate
-- 04 xxxx x100 Set icap_din(7 downto 0)
-- 05 xxxx x101 Set icap_din(15 downto 8)
-- 06 xxxx x110 Set icap_din(23 downto 16)
-- 07 xxxx x111 Set icap_din(31 downto 24)
-- 08 xxxx 1xxx Set ram_address(7 downto 0)
-- 10 xxx1 xxxx Set ram_address(11 downto 8)
-- 20 xx1x xxxx Write to RAM
-- 80 1xxx xxxx Set LEDs < Disconnected
--
output_ports: process(clk)
begin
if clk'event and clk = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Write to UART at port addresses 01 hex
-- See below this clocked process for the combinatorial decode required.
-- Write to 'set_baud_rate' at port addresses 02 hex
-- This value is set by KCPSM6 to define the BAUD rate of the UART.
-- See the 'UART baud rate' section for details.
if ((port_id(2) = '0') and (port_id(1) = '1')) then
set_baud_rate <= out_port;
end if;
-- Set 32-bit data for writing to ICAPE2 at port addresses 04, 05, 06 and 07.
-- port_id(2) is the general selection and then port_id(1:0) selects byte.
if port_id(2 downto 0) = "100" then
icap_din(7 downto 0) <= out_port;
end if;
if port_id(2 downto 0) = "101" then
icap_din(15 downto 8) <= out_port;
end if;
if port_id(2 downto 0) = "110" then
icap_din(23 downto 16) <= out_port;
end if;
if port_id(2 downto 0) = "111" then
icap_din(31 downto 24) <= out_port;
end if;
-- Set 12-bit address presented to the 4096 x 8-bit RAM at port addresses 08 and 10.
if port_id(3) = '1' then
ram_address(7 downto 0) <= out_port;
end if;
if port_id(4) = '1' then
ram_address(11 downto 8) <= out_port(3 downto 0);
end if;
-- Write data to 4096 x 8-bit RAM at port addresses 20 hex
-- See below this clocked process for the combinatorial decode required.
-- Write to general purpose LEDs at port addresses 80 hex
--if (port_id(7) = '1') then
-- led <= out_port;
--end if;
end if;
end if;
end process output_ports;
--
-- Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
-- Note the direct connection of 'out_port' to the UART transmitter macro and the
-- way that a single clock cycle write pulse is generated to capture the data.
--
uart_tx_data_in <= out_port;
write_to_uart_tx <= '1' when (write_strobe = '1') and (port_id(2) = '0') and (port_id(0) = '1')
else '0';
--
-- Write data directly in to the RAM at the defined 'ram_address' at port address 20 hex.
-- Note the direct connection of 'out_port' to 'ram_data_in' and the way that a single
-- clock cycle write pulse is generated to store the data.
--
ram_data_in <= out_port;
ram_we <= '1' when (write_strobe = '1') and (port_id(5) = '1')
else '0';
--
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
--
--
constant_output_ports: process(clk)
begin
if clk'event and clk = '1' then
if k_write_strobe = '1' then
-- Reset FIFO buffers in UART macros at constant port address 1 hex.
if port_id(0) = '1' then
uart_tx_reset <= out_port(0);
uart_rx_reset <= out_port(1);
end if;
-- Initiate ICAPE2 operation at constant port address 2 hex
-- Bit0 defines the value applied to RDWRB; read(1) or write(0) operation.
-- OUTPUTK to this port will also generate a single clock cycle active
-- Low ICAPE2 enable pulse to CSIB (see below).
if port_id(1) = '1' then
icap_rdwrb <= out_port(0);
else
icap_rdwrb <= icap_rdwrb;
end if;
end if;
-- Generate a single clock cycle active Low ICAPE2 enable pulse to CSIB
-- when OUTPUTK instruction to constant port address 2 hex.
if (k_write_strobe = '1') and (port_id(1) = '1') then
icap_csib <= '0';
else
icap_csib <= '1';
end if;
end if;
end process constant_output_ports;
--
-----------------------------------------------------------------------------------------
-- ICAPE2 primitive and Interfacing
-----------------------------------------------------------------------------------------
--
-- This primitive is used to supply the clock to the Readback CRC circuitry as well
-- provide access to the configuration state machine and configuration memory.
--
-- The 'DEVICE_ID' has been set to reflect the XC7K325T device on the KC705 board but
-- this definition is only used by the simulation model when simulating a design. Note
-- also that the '0' at the start of the defined value would probably be a different
-- value when reading the real device ID from a XC7K325T device because this is the
-- silicon revision field.
--
icap: ICAPE2
generic map( DEVICE_ID => X"03651093", -- IDCODE for a 7K325T device
ICAP_WIDTH => "X32", -- native 32-bit interface
SIM_CFG_FILE_NAME => "NONE")
port map( I => icap_i, -- data input
O => icap_o, -- data output
CSIB => icap_csib, -- enable (active Low)
RDWRB => icap_rdwrb, -- read(1) write(0)
CLK => clk ); -- clock also used by Readback CRC
--
-- KCPSM6 uses a constant optimised output port to set the RDWRB input to either read(1)
-- or write(0) a 32-bit word to or from ICAP. The act of setting the RDWRD signal will
-- also result in the generation of a single cycle active Low pulse that will be applied
-- to the CSIB input of ICAP to initiate the read or write operation.
--
-- In order that KCPSM6 can read a 32-bit word from ICAP, the following circuit captures
-- the output from ICAP into a 32-bit register that holds the value static so that KCPSM6
-- can read it one byte at a time. Although CSIB is an 'enable' signal, the output of
-- ICAP does not remain static when CSIB is inactive (1). Furthermore, a read of ICAP
-- involves a latency of 3 clock cycles so the 32-bit register has to be enabled 3 clock
-- cycles after ICAP has been enabled in order to sample and capture the correct value.
--
icap_interface: process(clk)
begin
if clk'event and clk = '1' then
-- Enable capture of ICAP output data 3 clock cycles after ICAPE2 is enabled
-- Note that CSIB is active Low so an inversion is required.
icap_csib_dly1 <= icap_csib;
icap_csib_dly2 <= icap_csib_dly1;
icap_o_reg_en <= not(icap_csib_dly2);
-- Register to capture ICAP output data
if icap_o_reg_en = '1' then
icap_o_reg <= icap_o;
else
icap_o_reg <= icap_o_reg;
end if;
end if;
end process icap_interface;
--
-- Connections to ICAPE2 configured in 32-bit access mode requires bit reversal within
-- each byte to produce values with a more logical format (i.e. like those described
-- and shown in UG470).
--
-- Although the following code could be written in a more concise form it is presented
-- and defined in this way to make it absolutely clear which bits are being swapped.
--
-- Meaningful data to ICAPE2 is called icap_din with the twisted version called icap_i
-- corresponding with the port name on the ICAP primitive.
--
-- Meaningful data from ICAPE2 is called icap_dout which is derived from the twisted
-- version icap_o_reg which is a direct capture of the icap_o output from the port
-- with a corresponding name on the ICAPE2 primitive.
--
-- Data to ICAP
icap_i(0) <= icap_din(7);
icap_i(1) <= icap_din(6);
icap_i(2) <= icap_din(5);
icap_i(3) <= icap_din(4);
icap_i(4) <= icap_din(3);
icap_i(5) <= icap_din(2);
icap_i(6) <= icap_din(1);
icap_i(7) <= icap_din(0);
icap_i(8) <= icap_din(15);
icap_i(9) <= icap_din(14);
icap_i(10) <= icap_din(13);
icap_i(11) <= icap_din(12);
icap_i(12) <= icap_din(11);
icap_i(13) <= icap_din(10);
icap_i(14) <= icap_din(9);
icap_i(15) <= icap_din(8);
icap_i(16) <= icap_din(23);
icap_i(17) <= icap_din(22);
icap_i(18) <= icap_din(21);
icap_i(19) <= icap_din(20);
icap_i(20) <= icap_din(19);
icap_i(21) <= icap_din(18);
icap_i(22) <= icap_din(17);
icap_i(23) <= icap_din(16);
icap_i(24) <= icap_din(31);
icap_i(25) <= icap_din(30);
icap_i(26) <= icap_din(29);
icap_i(27) <= icap_din(28);
icap_i(28) <= icap_din(27);
icap_i(29) <= icap_din(26);
icap_i(30) <= icap_din(25);
icap_i(31) <= icap_din(24);
-- Data from ICAP
icap_dout(0) <= icap_o_reg(7);
icap_dout(1) <= icap_o_reg(6);
icap_dout(2) <= icap_o_reg(5);
icap_dout(3) <= icap_o_reg(4);
icap_dout(4) <= icap_o_reg(3);
icap_dout(5) <= icap_o_reg(2);
icap_dout(6) <= icap_o_reg(1);
icap_dout(7) <= icap_o_reg(0);
icap_dout(8) <= icap_o_reg(15);
icap_dout(9) <= icap_o_reg(14);
icap_dout(10) <= icap_o_reg(13);
icap_dout(11) <= icap_o_reg(12);
icap_dout(12) <= icap_o_reg(11);
icap_dout(13) <= icap_o_reg(10);
icap_dout(14) <= icap_o_reg(9);
icap_dout(15) <= icap_o_reg(8);
icap_dout(16) <= icap_o_reg(23);
icap_dout(17) <= icap_o_reg(22);
icap_dout(18) <= icap_o_reg(21);
icap_dout(19) <= icap_o_reg(20);
icap_dout(20) <= icap_o_reg(19);
icap_dout(21) <= icap_o_reg(18);
icap_dout(22) <= icap_o_reg(17);
icap_dout(23) <= icap_o_reg(16);
icap_dout(24) <= icap_o_reg(31);
icap_dout(25) <= icap_o_reg(30);
icap_dout(26) <= icap_o_reg(29);
icap_dout(27) <= icap_o_reg(28);
icap_dout(28) <= icap_o_reg(27);
icap_dout(29) <= icap_o_reg(26);
icap_dout(30) <= icap_o_reg(25);
icap_dout(31) <= icap_o_reg(24);
--
-----------------------------------------------------------------------------------------
-- FRAME_ECCE2 Primitive
-----------------------------------------------------------------------------------------
--
frame_ecc: FRAME_ECCE2
generic map( FARSRC => "EFAR",
FRAME_RBT_IN_FILENAME => "NONE")
port map( CRCERROR => frame_ecc_crcerr, -- device CRC error
ECCERROR => frame_ecc_eccerr, -- frame ECC error
ECCERRORSINGLE => frame_ecc_eccerrsingle, -- single bit error detected
FAR => frame_ecc_far, -- frame address register value
SYNBIT => frame_ecc_synbit, -- bit address of error
SYNDROME => frame_ecc_syndrome, -- frame syndrome
SYNDROMEVALID => frame_ecc_syndromevalid, -- syndrome output is valid
SYNWORD => frame_ecc_synword); -- word address of error
--
-----------------------------------------------------------------------------------------
-- Readback CRC Monitor
-----------------------------------------------------------------------------------------
--
-- 'SYNDROMEVALID' output of FRAME_ECCE2
--
-- This signal will pulse High (1) every time a configuration frame has been read and
-- indicates that the value being presented on the 'SYNDROME' output is valid and ready
-- for inspection (if required). When Readback CRC scanning of the device is enabled, a
-- configuration frame is read every 101 clock cycles and therefore 'SYNDROMEVALID'
-- typically pulses High for one clock cycle in every 101 clock cycles. The steady
-- generation of 'SYNDROMEVALID' pulses is a perfect way to confirm when Readback CRC
-- scanning is active (i.e. vital for those demanding SEU detection).
--
-- When the Readback CRC scan reaches the end of the device there is a slightly larger
-- gap of 140 clock cycles between the reading of the last frame of one scan and the
-- first frame of the next scan. This additional 39 clock cycles can be detected and
-- used to identify the end/start of each device scan.
--
-- KCPSM6 cannot reliably observe single clock cycle pulses so the following counter
-- based circuit is used to stretch the 'SYNDROMEVALID' pulses as well as generate a
-- reasonably long pulse indicating the end of a device scan.
--
-- An 8-bit counter is generally free to increment every clock cycle but it will be
-- reset by each 'SYNDROMEVALID' pulse. In this way the counter typically reaches 100
-- (64 hex) and then resets (00 hex). However, at the end of each device scan, the
-- counter will exceed 100 (64 hex), so when it does reach 101 (65 hex) an 'end_of_scan'
-- signal is set. providing Readback CRC scanning is active, the next 'SYNDROMEVALID'
-- pulse will occur 39 clock cycles later resetting the counter and clearing the
-- 'end_of_scan' signal. The 'end_of_scan' pulse is long enough to be seen by KCPSM6.
--
-- If no 'SYNDROMEVALID' pulse occurs for 255 clock cycles the 8-bit counter will
-- saturate at FF hex avoiding false indication of Readback CRC activity. This will
-- happen if Readback CRC scanning is disabled or if ICAP is being accessed by KCPSM6.
--
-- So that KCPSM6 can reliably observe 'SYNDROMEVALID' pulses, an 'end_of_frame' pulse
-- with a duration of 16 clock cycles is generated for each 'SYNDROMEVALID' pulse that
-- is generated by FRAME_ECCE2.
--
-- Note that KCPSM6 must poll the input port associated with reading the 'end_of_scan'
-- and 'end_of_frame' signals at an adequate rate to avoid missing them (at least when
-- they are relevant to the task). Furthermore, KCPSM6 has a maximum of 101 clock cycles
-- between 'end_of_frames' to perform any tasks and this equates to the execution of a
-- maximum of 50 instructions.
--
scan_monitor: process(clk)
begin
if clk'event and clk = '1' then
if frame_ecc_syndromevalid = '1' then
-- Reset counter, clear 'end_of_scan' and set 'end_of_frame'
scan_counter <= "00000000";
end_of_scan <= '0';
end_of_frame <= '1';
else
-- Increment counter unless saturated
if scan_counter = "11111111" then
scan_counter <= scan_counter;
else
scan_counter <= scan_counter + 1;
end if;
-- Set end_of_scan when counter goes above 100 (64 hex)
if scan_counter = "01100100" then
end_of_scan <= '1';
else
end_of_scan <= end_of_scan;
end if;
-- Clear 'end_of_frame' when counter reaches 16 (10 hex)
if scan_counter(4) = '1' then
end_of_frame <= '0';
else
end_of_frame <= end_of_frame;
end if;
end if;
end if;
end process scan_monitor;
--
-----------------------------------------------------------------------------------------
-- Independent Readback CRC Scan Active Indicator
-----------------------------------------------------------------------------------------
--
-- The SYNDROMEVALID output of FRAME_ECCE2 will pulse High as the Readback CRC mechanism
-- reads each frame comprising 101 words. A 24-bit counter is used to count and divide
-- the pulses observed such that bit16 will have a frequency of ~15Hz and bit23 will have
-- a frequency of ~0.06Hz (i.e. a period of ~16.9 seconds) when the clock is 100MHz.
--
-- The most significant 8-bits are provided to 'scan_indicator' output and are ideal
-- for connection to 8 LEDs which will provide an instant visual indication of scanning
-- activity. Note that the PSM code will initially prompt the user to grant the SEM IP
-- access to ICAP so Readback CRC scanning will only become active once permission has
-- been granted.
--
-- SYNDROMEVALID pulse rate will be 990,099Hz when using a 100MHz clock.
--
scan_indicator: process(clk)
begin
if clk'event and clk = '1' then
if frame_ecc_syndromevalid = '1' then
syndrome_counter <= syndrome_counter + 1;
else
syndrome_counter <= syndrome_counter;
end if;
end if;
end process scan_indicator;
led <= syndrome_counter(23 downto 16);
--
-----------------------------------------------------------------------------------------
--
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE kc705_kcpsm6_icap.vhd
--
-------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: EX_MEM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EX_MEM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END EX_MEM_exdes;
ARCHITECTURE xilinx OF EX_MEM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT EX_MEM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : EX_MEM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
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